From nobody Thu Nov 14 19:37:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A88EC43334 for ; Wed, 29 Jun 2022 16:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233847AbiF2QBV (ORCPT ); Wed, 29 Jun 2022 12:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234252AbiF2QAa (ORCPT ); Wed, 29 Jun 2022 12:00:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B691221E11; Wed, 29 Jun 2022 09:00:29 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 692CD660198D; Wed, 29 Jun 2022 17:00:27 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518428; bh=etvqQ1Sf4L9KOJ6PfLg/qIPZJ2SbAA+l1UyPzPWGVwY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vp86zMw2GSlDu1PAFaueC5lnum0u0hTa4z3UyfBNZDukkMJJnem88oC876mYn+2TP ob9W5WbSl0j237TWLhuN2RXo7IDzA5pQhTGJLWba2FrqQqekpRsV7RPlgF3wGF+PPS V14L4WzyEPibYHKM5/ShK6sp2PwEW8EB0x+cz2idB0kC0/wdSRSn1skW6RlvpbsO5i N3G09TpbZ1h0EjWdrOvpQ9rvmZaoeQEK9AbR6zh9UIoueBG/rjFggRLSk16tIx5q1V mfttr/sLp8bVGga4vW5c3mAiQxYso0bWbL0+tk95f2shNXYgXJIE97CDTwjbgCQOt5 hwmcC3ZuCoBMg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC Date: Wed, 29 Jun 2022 11:59:54 -0400 Message-Id: <20220629155956.1138955-18-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable both MMC controllers present on Asurada. MMC0 is for non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't used on all machines, but in those cases the CD interrupt is never triggered and thus it is basically as if it was disabled. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index d56c73e37633..7b89f6e552c5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -170,6 +170,46 @@ &i2c7 { pinctrl-0 =3D <&i2c7_pins>; }; =20 +&mmc0 { + status =3D "okay"; + + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + hs400-ds-delay =3D <0x12814>; + no-sdio; + no-sd; + non-removable; +}; + +&mmc1 { + status =3D "okay"; + + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_default_pins>; + pinctrl-1 =3D <&mmc1_uhs_pins>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cd-gpios =3D <&pio 17 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&mt6360_ldo5_reg>; + vqmmc-supply =3D <&mt6360_ldo3_reg>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-sdio; + no-mmc; +}; + /* for CORE */ &mt6359_vgpu11_buck_reg { regulator-always-on; @@ -503,6 +543,115 @@ pins-bus { }; }; =20 + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <10>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <10>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <10>; + bias-pull-down =3D ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-insert { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + input-enable; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + }; + pcie_pins: pcie-default-pins { pins-pcie-wake { pinmux =3D ; --=20 2.36.1