From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A5F4C43334 for ; Wed, 29 Jun 2022 16:00:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234310AbiF2QAJ (ORCPT ); Wed, 29 Jun 2022 12:00:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231494AbiF2QAH (ORCPT ); Wed, 29 Jun 2022 12:00:07 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E6021BEA5; Wed, 29 Jun 2022 09:00:05 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id B8925660192A; Wed, 29 Jun 2022 17:00:02 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518404; bh=jfOGEhGUqzgWmNYEYTwDX2UHrYEvnOH9l69P1HilBiI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ajEpttGlWG9Yi6MtxofEuvbhb1OcH5iXhy1fbYzMq7DzDIhlEinzUN9CPTWm/XWGH RCLGiSySMglgzSODPSIiJp83O+8KkqgbjfYP2AfRaYh100uvGeuVLpZMT7Kt5Qm83j LiC8n0DmILsRG/vVGbevT5x03v2asvGjNA4QtG1rPIz6FpYRqH0cTH7vGHKNQ9vgQO hL56sJEq4+3npq4+DtMpFeIVB1ySbU7IGbt9l0Z8pfVI+FT8RBvfFYh8bK70nuUQoq n/zYcWpvuE9BvIft0Jc/cTB/+a8x/AQEya0UhxrkYTOTvxv225artM+eC7GzNhPvm4 CIqyy3p8yD4dg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Allen-KH Cheng , Fabien Parent , Hsin-Yi Wang , Krzysztof Kozlowski , Maxim Kutnij , Rob Herring , Sam Shih , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 01/19] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion Date: Wed, 29 Jun 2022 11:59:38 -0400 Message-Id: <20220629155956.1138955-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for the Google Spherion board, which is used for Acer Chromebook 514 (CB514-2H). Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Acked-by: Rob Herring --- (no changes since v2) Changes in v2: - Added this patch Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 5a29b7b381ef..1f9535097a60 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,14 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - description: Google Spherion (Acer Chromebook 514) + items: + - const: google,spherion-rev3 + - const: google,spherion-rev2 + - const: google,spherion-rev1 + - const: google,spherion-rev0 + - const: google,spherion + - const: mediatek,mt8192 - items: - enum: - mediatek,mt8186-evb --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 620F3C43334 for ; Wed, 29 Jun 2022 16:00:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233594AbiF2QAO (ORCPT ); Wed, 29 Jun 2022 12:00:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233848AbiF2QAI (ORCPT ); Wed, 29 Jun 2022 12:00:08 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BD4A1C924; Wed, 29 Jun 2022 09:00:07 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id B9EE86601947; Wed, 29 Jun 2022 17:00:04 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518406; bh=XpyEub610YnsHC64VXOfExg4aKEWhPEsupxIb1vB3IE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X6+wKWuzrjtOkqr78Fyi6hOyp2uZ8SogvLHfNlUmit+gi0Tp3/Z7dLflDlruLDrTq wR1/YluBvz4Dtpwmg9CgxTqNGTRaoJ2SPw6T7YY3p2Lni96uyBI6PYD+cBA3KtlMQR weE0gGWW50+Rt96ia4GTwN39GagN6B7La5vN9Fw0QSbC9SM/duV3DCd4boJcK4JTq2 DZ2PDcg8mW0wpiSWDF+5mXLnV4AqfpgjpbUzxAlQxDuvgCh3F5bIZHhE/HWMCO81oc 8QENu+K34KTY5F/7+LnV3JVFctQe5u8g1R6pXKqCIOlgPgyUn9T1Wx92qJY3Vk2x+p kk7pziTk0ZynQ== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Allen-KH Cheng , Hsin-Yi Wang , Krzysztof Kozlowski , Luca Weiss , Maxim Kutnij , Rob Herring , Sam Shih , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 02/19] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato Date: Wed, 29 Jun 2022 11:59:39 -0400 Message-Id: <20220629155956.1138955-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for the Google Hayato board. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Acked-by: Rob Herring --- (no changes since v2) Changes in v2: - Added this patch Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 1f9535097a60..dd6c6e8011f9 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,11 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - description: Google Hayato + items: + - const: google,hayato-rev1 + - const: google,hayato + - const: mediatek,mt8192 - description: Google Spherion (Acer Chromebook 514) items: - const: google,spherion-rev3 --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60B9ECCA480 for ; Wed, 29 Jun 2022 16:00:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234185AbiF2QAS (ORCPT ); Wed, 29 Jun 2022 12:00:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234316AbiF2QAK (ORCPT ); Wed, 29 Jun 2022 12:00:10 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 097901C914; Wed, 29 Jun 2022 09:00:09 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id BDAA86601948; Wed, 29 Jun 2022 17:00:06 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518407; bh=7FWouNZ6jxRvkXEGGYykyUzgA0FsaeEdzAQhsdSPeQs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ICPLGRrsFmfJiv67vOjuykNSlEi/3AMFS5RWsC1OOpYtw5QGTrSW6RMtl07jl0+Ny ahlJtwU78hOLHfseudm9WRWJarMXzz+xoQ52DFGlxHSPhefFCXRiZM+5Oyv0FxqCiY dzTMvH/lGpjztpUkVU03Ef+RhDvPOArVPxvuGXdCp6x20bE8kEs8YKqd9cPpoHXQ9H d2zTveIpfcm13EvYLih80XYnY3Ejavsl/dzxGpmT/FGZCxJkwVWaPHhMGrA2OSIgOX swfCcrbNCR5pGRvYhUuEht12JsLegGNZ5Lqol1uF/HNjyp5K2q62wxOSpUopBHej78 oKReKgY9SYaqw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 03/19] arm64: dts: mediatek: Introduce MT8192-based Asurada board family Date: Wed, 29 Jun 2022 11:59:40 -0400 Message-Id: <20220629155956.1138955-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce the MT8192 Asurada Chromebook platform, including the Asurada Spherion and Asurada Hayato boards. This is enough configuration to get serial output working on Spherion and Hayato. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v2) Changes in v2: - Changed model name prefix from Mediatek to Google on Hayato and Spherion dts arch/arm64/boot/dts/mediatek/Makefile | 2 ++ .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 11 ++++++++ .../mediatek/mt8192-asurada-spherion-r0.dts | 13 ++++++++++ .../boot/dts/mediatek/mt8192-asurada.dtsi | 26 +++++++++++++++++++ 4 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.d= ts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0= .dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 50a2c58c5f56..b52058965a0d 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,6 +38,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/ar= ch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts new file mode 100644 index 000000000000..00c76709a055 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" + +/ { + model =3D "Google Hayato rev1"; + compatible =3D "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/= arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts new file mode 100644 index 000000000000..d384d584bbcf --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" + +/ { + model =3D "Google Spherion (rev0 - 3)"; + compatible =3D "google,spherion-rev3", "google,spherion-rev2", + "google,spherion-rev1", "google,spherion-rev0", + "google,spherion", "mediatek,mt8192"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi new file mode 100644 index 000000000000..277bd38943fe --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8192.dtsi" + +/ { + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EAEDC43334 for ; Wed, 29 Jun 2022 16:00:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234393AbiF2QAX (ORCPT ); Wed, 29 Jun 2022 12:00:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234058AbiF2QAP (ORCPT ); Wed, 29 Jun 2022 12:00:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7872E1CFF9; Wed, 29 Jun 2022 09:00:10 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 38617660192F; Wed, 29 Jun 2022 17:00:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518409; bh=fiBaCyrf7h8x5bjTRdPMlGfXIm342Oj/a4cpeBrl3sU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ablb9biVRLjSiJrDQ/KRWyJAw6wtsoaZnnD3ZyMIh0p5nIzhVeDOcyLT6HEEshSXg lZutaoZu1LyPnZnVZwuLroEXNk5EWriHP/zvQIAMV5yd4sOgTetJSQeGnUUbcu5zk3 4WcjbFqzeAVw+HbXVZ7dWlv1Amh1D6B8ssudvsnD2qR9Vl4ALJr6n/B0mV3o5jXFWL wk48SnFeqSk9WDUCesoK9Tsaj0Q2mPIQTDFUhSrQYewZyTx42570Rp+9eTeBVTAbVL jpluzX61xGD7Zj7zOIB07Lo472jeGzGihO53gTXcd1yOOchzCjhvkSR7og8FA/M/lq 7mIx731ef+2xQ== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 04/19] arm64: dts: mediatek: asurada: Document GPIO names Date: Wed, 29 Jun 2022 11:59:41 -0400 Message-Id: <20220629155956.1138955-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the gpio-line-names property to gpio-controller in order to document the usage of GPIOs on the Asurada platform. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 277bd38943fe..e10636298639 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -21,6 +21,234 @@ memory@40000000 { }; }; =20 +&pio { + /* 220 lines */ + gpio-line-names =3D "I2S_DP_LRCK", + "IS_DP_BCLK", + "I2S_DP_MCLK", + "I2S_DP_DATAOUT", + "SAR0_INT_ODL", + "EC_AP_INT_ODL", + "EDPBRDG_INT_ODL", + "DPBRDG_INT_ODL", + "DPBRDG_PWREN", + "DPBRDG_RST_ODL", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAIN", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TRACKPAD_INT_ODL", + "EC_AP_HPD_OD", + "SD_CD_ODL", + "HP_INT_ODL_ALC", + "EN_PP1000_DPBRDG", + "AP_GPIO20", + "TOUCH_INT_L_1V8", + "UART_BT_WAKE_ODL", + "AP_GPIO23", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "EN_PP3300_DPBRDG_DX", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO", + "I2S_HP_DATAOUT", + "AP_GPIO30", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_DATAOUT", + "AP_SPI_H1_TPM_CLK", + "AP_SPI_H1_TPM_CS_L", + "AP_SPI_H1_TPM_MISO", + "AP_SPI_H1_TPM_MOSI", + "BL_PWM", + "EDPBRDG_PWREN", + "EDPBRDG_RST_ODL", + "EN_PP3300_HUB", + "HUB_RST_L", + "", + "", + "", + "", + "", + "", + "SD_CLK", + "SD_CMD", + "SD_DATA3", + "SD_DATA0", + "SD_DATA2", + "SD_DATA1", + "", + "", + "", + "", + "", + "", + "PCIE_WAKE_ODL", + "PCIE_RST_L", + "PCIE_CLKREQ_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SPMI_SCL", + "SPMI_SDA", + "AP_GOOD", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "UART_AP_TX_BT_RX", + "UART_BT_TX_AP_RX", + "MIPI_DPI_D0_R", + "MIPI_DPI_D1_R", + "MIPI_DPI_D2_R", + "MIPI_DPI_D3_R", + "MIPI_DPI_D4_R", + "MIPI_DPI_D5_R", + "MIPI_DPI_D6_R", + "MIPI_DPI_D7_R", + "MIPI_DPI_D8_R", + "MIPI_DPI_D9_R", + "MIPI_DPI_D10_R", + "", + "", + "MIPI_DPI_DE_R", + "MIPI_DPI_D11_R", + "MIPI_DPI_VSYNC_R", + "MIPI_DPI_CLK_R", + "MIPI_DPI_HSYNC_R", + "PCM_BT_DATAIN", + "PCM_BT_SYNC", + "PCM_BT_DATAOUT", + "PCM_BT_CLK", + "AP_I2C_AUDIO_SCL", + "AP_I2C_AUDIO_SDA", + "SCP_I2C_SCL", + "SCP_I2C_SDA", + "AP_I2C_WLAN_SCL", + "AP_I2C_WLAN_SDA", + "AP_I2C_DPBRDG_SCL", + "AP_I2C_DPBRDG_SDA", + "EN_PP1800_DPBRDG_DX", + "EN_PP3300_EDP_DX", + "EN_PP1800_EDPBRDG_DX", + "EN_PP1000_EDPBRDG", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TRSTN", + "EN_PP3000_VMC_PMU", + "EN_PP3300_DISPLAY_DX", + "TOUCH_RST_L_1V8", + "TOUCH_REPORT_DISABLE", + "", + "", + "AP_I2C_TRACKPAD_SCL_1V8", + "AP_I2C_TRACKPAD_SDA_1V8", + "EN_PP3300_WLAN", + "BT_KILL_L", + "WIFI_KILL_L", + "SET_VMC_VOLT_AT_1V8", + "EN_SPK", + "AP_WARM_RST_REQ", + "", + "", + "EN_PP3000_SD_S3", + "AP_EDP_BKLTEN", + "", + "", + "", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_I2C_EDPBRDG_SCL", + "AP_I2C_EDPBRDG_SDA", + "MT6315_PROC_INT", + "MT6315_GPU_INT", + "UART_SERVO_TX_SCP_RX", + "UART_SCP_TX_SERVO_RX", + "BT_RTS_AP_CTS", + "AP_RTS_BT_CTS", + "UART_AP_WAKE_BT_ODL", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "H1_AP_INT_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MSDC0_CMD", + "MSDC0_DAT0", + "MSDC0_DAT2", + "MSDC0_DAT4", + "MSDC0_DAT6", + "MSDC0_DAT1", + "MSDC0_DAT5", + "MSDC0_DAT7", + "MSDC0_DSL", + "MSDC0_CLK", + "MSDC0_DAT3", + "MSDC0_RST_L", + "SCP_VREQ_VAO", + "AUD_DAT_MOSI2", + "AUD_NLE_MOSI1", + "AUD_NLE_MOSI0", + "AUD_DAT_MISO2", + "AP_I2C_SAR_SDA", + "AP_I2C_SAR_SCL", + "AP_I2C_PWR_SCL", + "AP_I2C_PWR_SDA", + "AP_I2C_TS_SCL_1V8", + "AP_I2C_TS_SDA_1V8", + "SRCLKENA0", + "SRCLKENA1", + "AP_EC_WATCHDOG_L", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "AP_RTC_CLK32K", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1"; +}; + &uart0 { status =3D "okay"; }; --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8206CCA47E for ; Wed, 29 Jun 2022 16:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234382AbiF2QAa (ORCPT ); Wed, 29 Jun 2022 12:00:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234208AbiF2QAP (ORCPT ); Wed, 29 Jun 2022 12:00:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F14AE1CB28; Wed, 29 Jun 2022 09:00:11 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id AEAF8660194A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add system-wide power supplies present on all of the boards in the Asurada family. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Acked-by: Krzysztof Kozlowski --- (no changes since v3) Changes in v3: - Renamed nodes to be generic .../boot/dts/mediatek/mt8192-asurada.dtsi | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index e10636298639..ca55dd095e80 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -19,6 +19,70 @@ memory@40000000 { device_type =3D "memory"; reg =3D <0 0x40000000 0 0x80000000>; }; + + /* system wide LDO 1.8V power rail */ + pp1800_ldo_g: regulator-1v8-g { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_ldo_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&pp3300_g>; + }; + + /* system wide switching 3.3V power rail */ + pp3300_g: regulator-3v3-g { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_ldo_z: regulator-3v3-z { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_ldo_z"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_u: regulator-3v3-u { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_u"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + /* enable pin wired to GPIO controlled by EC */ + vin-supply =3D <&pp3300_g>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_a: regulator-5v0-a { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp5000_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-var-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; }; =20 &pio { --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACE28C43334 for ; Wed, 29 Jun 2022 16:00:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232800AbiF2QAd (ORCPT ); Wed, 29 Jun 2022 12:00:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234238AbiF2QAP (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Asurada platform has five I2C controllers and two SPI controllers that are used. In preparation for enabling the devices connected to these controllers, enable and configure their busses. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Switched mediatek,drive-strength-adv for drive-strength-microamp - Switched mediatek,pull-up-adv for bias-pull-up .../boot/dts/mediatek/mt8192-asurada.dtsi | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index ca55dd095e80..72dc974fe6fc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -85,6 +85,47 @@ ppvar_sys: regulator-var-sys { }; }; =20 +&i2c0 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + status =3D "okay"; + + clock-frequency =3D <400000>; + clock-stretch-ns =3D <12600>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; +}; + +&i2c3 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&i2c7 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_pins>; +}; + &pio { /* 220 lines */ gpio-line-names =3D "I2S_DP_LRCK", @@ -311,6 +352,91 @@ &pio { "AUD_DAT_MOSI1", "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux =3D , + , + ; + bias-disable; + }; + + pins-miso { + pinmux =3D ; + bias-pull-down; + }; + }; + + spi5_pins: spi5-default-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; +}; + +&spi1 { + status =3D "okay"; + + mediatek,pad-select =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&spi5 { + status =3D "okay"; + + cs-gpios =3D <&pio 37 GPIO_ACTIVE_LOW>; + mediatek,pad-select =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi5_pins>; }; =20 &uart0 { --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8514CC43334 for ; Wed, 29 Jun 2022 16:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234415AbiF2QAi (ORCPT ); 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b=QPo0pCyMxI/iLHaKwWcVnw3c7woXm5YVQokd2ave3flD/4QZs1fWWNqU9oC/wiEkD gRW6nvkuGQTcacYGdI/6cuDAacCFUg5Lkf5XxE46PJzFpB3fIv3FKVjxOjLgi/Qblb LLc9JmHabKXntX1mAcxNEXNtY6zr5pG2Ru3IcKBJqjSJFWmdZM+R07OgcltUcNd6Ul sXMI4MWvSoD+fXM9OCghYO87R3iZ3uMkxVYxPpp860xB6p1pyA1mf2QQxpCGt/B0MO 21BFq8FqzHsabenQvn58ExHaAh+15UEy9c3sup7GQr+fpjZfaXQ8xZ+B7MVoSIBj55 yHzzfv+aZ/W9A== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 07/19] arm64: dts: mediatek: asurada: Add ChromeOS EC Date: Wed, 29 Jun 2022 11:59:44 -0400 Message-Id: <20220629155956.1138955-8-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the ChromeOS Embedded Controller present on the Asurada platform. It is connected through the SPI1 bus and offers several functionalities: base detection, PWM controller, I2C tunneling, regulators, Type-C connector management, keyboard and Smart Battery Metrics (SBS). Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v2) Changes in v2: - Renamed PWM subnode to avoid dt-binding warning (ec-pwm -> pwm) .../boot/dts/mediatek/mt8192-asurada.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 72dc974fe6fc..07405dea4d9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -353,6 +353,14 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; =20 + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux =3D , @@ -428,6 +436,74 @@ &spi1 { mediatek,pad-select =3D <0>; pinctrl-names =3D "default"; pinctrl-0 =3D <&spi1_pins>; + + cros_ec: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupts-extended =3D <&pio 5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency =3D <3000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cros_ec_int>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + base_detection: cbas { + compatible =3D "google,cros-cbas"; + }; + + cros_ec_pwm: pwm { + compatible =3D "google,cros-ec-pwm"; + #pwm-cells =3D <1>; + + status =3D "disabled"; + }; + + i2c_tunnel: i2c-tunnel { + compatible =3D "google,cros-ec-i2c-tunnel"; + google,remote-bus =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mt6360_ldo3_reg: regulator@0 { + compatible =3D "google,cros-ec-regulator"; + reg =3D <0>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + mt6360_ldo5_reg: regulator@1 { + compatible =3D "google,cros-ec-regulator"; + reg =3D <1>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + typec { + compatible =3D "google,cros-ec-typec"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_c0: connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + label =3D "left"; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + }; + + usb_c1: connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + label =3D "right"; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + }; + }; + }; }; =20 &spi5 { @@ -442,3 +518,6 @@ &spi5 { &uart0 { status =3D "okay"; }; + +#include +#include --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE0A4C43334 for ; Wed, 29 Jun 2022 16:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234474AbiF2QAp (ORCPT ); Wed, 29 Jun 2022 12:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234348AbiF2QAR (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Chromebooks' embedded keyboards differ from standard layouts for the top row in that they have shortcuts in place of the standard function keys. Map these keys to achieve the functionality that is pictured on the printouts. There's a minor difference between the keys present on Hayato, which uses an older layout, and Spherion, which uses a newer one. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v3) Changes in v3: - Moved keyboard layout definition to hayato and spherion dts files, instead of common one in asurada dtsi - Changed hayato layout to be the same as older Chromebooks like Kevin - Switched KEY_ZOOM for KEY_FULL_SCREEN, just for semantics - Updated commit message .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 29 +++++++++++++++++++ .../mediatek/mt8192-asurada-spherion-r0.dts | 29 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/ar= ch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index 00c76709a055..ca18fcf2ad4f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -9,3 +9,32 @@ / { model =3D "Google Hayato rev1"; compatible =3D "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; }; + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_FORWARD) + MATRIX_KEY(0x02, 0x02, KEY_REFRESH) + MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN) + MATRIX_KEY(0x03, 0x04, KEY_SCALE) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/= arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index d384d584bbcf..30b03895de41 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -11,3 +11,32 @@ / { "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; }; + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E0ADC433EF for ; Wed, 29 Jun 2022 16:00:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233827AbiF2QAt (ORCPT ); Wed, 29 Jun 2022 12:00:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234353AbiF2QAS (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Asurada platform has a Google Security Chip connected to the SPI5 bus. It runs the cr50 firmware and provides TPM functionality. Add support for it. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v1) .../arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 07405dea4d9d..fe626535ee5d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8192.dtsi" +#include =20 / { aliases { @@ -353,6 +354,13 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; =20 + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux =3D ; + input-enable; + }; + }; + cros_ec_int: cros-ec-irq-default-pins { pins-ec-ap-int-odl { pinmux =3D ; @@ -513,6 +521,15 @@ &spi5 { mediatek,pad-select =3D <0>; pinctrl-names =3D "default"; pinctrl-0 =3D <&spi5_pins>; + + cr50@0 { + compatible =3D "google,cr50"; + reg =3D <0>; + interrupts-extended =3D <&pio 171 IRQ_TYPE_EDGE_RISING>; + spi-max-frequency =3D <1000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cr50_int>; + }; }; =20 &uart0 { --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28393C433EF for ; Wed, 29 Jun 2022 16:00:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234409AbiF2QAx (ORCPT ); Wed, 29 Jun 2022 12:00:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234371AbiF2QAV (ORCPT ); Wed, 29 Jun 2022 12:00:21 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CECA1C91B; Wed, 29 Jun 2022 09:00:19 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0B60F66019D8; Wed, 29 Jun 2022 17:00:16 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518418; bh=o29vqqsWji0OFz7litVCz+HSv2vrNoGr04oOrOfn0YM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KA7L+82b3TQ37iIXoQ/ZOTFIuM2Ig0B5xZNl9IkANTbDCpSij0oVuahGvW1BjwMlO Vpn95jAVKnxoDGYxmCnUEGPW8WjJmeq6jRQdNArA2urpVCn9zT0GlVouBsXaQNjEag 0ChL6N7YeAm6eVth0++RyWz4A2w1mzUbgBYpeDJUTdcJ48zZ3lsci31vnO5b69YMVu fwiI/K2VWHoDeMe5/SAusfv2dTYVb4nIemEt+TkLmHIze+Svob+tX3J6VJWbAMLrPP tNz2nhV7T2rCTZbOVqOk9j4hCvXTo4gI2k2cOYo1SLVkAA7qLgtHZTDn1y3BZkppiH hKSi2BIbzhHTA== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 10/19] arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad Date: Wed, 29 Jun 2022 11:59:47 -0400 Message-Id: <20220629155956.1138955-11-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the Elan eKTH3000 i2c trackpad present on Asurada. It is connected to the I2C2 bus and has address 0x15. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Switched mediatek,pull-up-adv for bias-pull-up .../boot/dts/mediatek/mt8192-asurada.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index fe626535ee5d..4de4235cb768 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -109,6 +109,16 @@ &i2c2 { clock-stretch-ns =3D <12600>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c2_pins>; + + trackpad@15 { + compatible =3D "elan,ekth3000"; + reg =3D <0x15>; + interrupts-extended =3D <&pio 15 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&trackpad_pins>; + vcc-supply =3D <&pp3300_u>; + wakeup-source; + }; }; =20 &i2c3 { @@ -436,6 +446,14 @@ pins-bus { bias-disable; }; }; + + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux =3D ; + input-enable; + bias-pull-up =3D ; + }; + }; }; =20 &spi1 { --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B1D7C433EF for ; Wed, 29 Jun 2022 16:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234385AbiF2QBG (ORCPT ); Wed, 29 Jun 2022 12:01:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234372AbiF2QAV (ORCPT ); Wed, 29 Jun 2022 12:00:21 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB5441C91E; Wed, 29 Jun 2022 09:00:20 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7CD8E6601977; Wed, 29 Jun 2022 17:00:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518419; bh=4spTm+nSjWESSW3qtK2fAkjQznUiCUQIQixr1OG7tGg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OIyvFqwi7EKzy9XT184H158DbWBDB7JOhQ08VdfYt4F5mrlkQR81QZjh/owIfw382 6+KedYF88uUo+tKUxPm0XYJh6FWv2SZzvo/1L414dxp2AjBBLArzEbthknC29ZOa0e 8n1HzV21JpgAewjKYpUWSGCRldi8s1Yq5Q/HczZLcTa6Vq8X+/9u/Q5bieQrae0mQq V9SDFI/2uXYJXDTByXUhdS/Gemjmc5KMpqd4U1ynyZdyVIWYL8KvphnHKIgpQ4kE67 OcYtqyf0Lc0hdGjPVob2BC0GxGjIJcnGVdGAMnPl+lTAm08M0KEDpGG1E6OoEvn91V mN3JeqN2ZjX3A== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 11/19] arm64: dts: mediatek: asurada: Add I2C touchscreen Date: Wed, 29 Jun 2022 11:59:48 -0400 Message-Id: <20220629155956.1138955-12-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All machines of the Asurada platform have a touchscreen at address 0x10 in the I2C0 bus, but the devices vary: Spherion has the Elan eKTH3500 touchscreen, while Hayato has a generic HID-over-i2c touchscreen. Add common support for the touchscreens on the platform and the specifics in each board file. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v1) .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 7 ++++++ .../mediatek/mt8192-asurada-spherion-r0.dts | 4 +++ .../boot/dts/mediatek/mt8192-asurada.dtsi | 25 +++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/ar= ch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index ca18fcf2ad4f..1e91491945f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -38,3 +38,10 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) CROS_STD_MAIN_KEYMAP >; }; + +&touchscreen { + compatible =3D "hid-over-i2c"; + post-power-on-delay-ms =3D <10>; + hid-descr-addr =3D <0x0001>; + vdd-supply =3D <&pp3300_u>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/= arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index 30b03895de41..42db81e95fae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -40,3 +40,7 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) CROS_STD_MAIN_KEYMAP >; }; + +&touchscreen { + compatible =3D "elan,ekth3500"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 4de4235cb768..6eace280c14a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -92,6 +92,13 @@ &i2c0 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0_pins>; + + touchscreen: touchscreen@10 { + reg =3D <0x10>; + interrupts-extended =3D <&pio 21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touchscreen_pins>; + }; }; =20 &i2c1 { @@ -454,6 +461,24 @@ pins-int-n { bias-pull-up =3D ; }; }; + + touchscreen_pins: touchscreen-default-pins { + pins-irq { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux =3D ; + output-high; + }; + + pins-report-sw { + pinmux =3D ; + output-low; + }; + }; }; =20 &spi1 { --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6435CC43334 for ; Wed, 29 Jun 2022 16:01:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234509AbiF2QBC (ORCPT ); Wed, 29 Jun 2022 12:01:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234385AbiF2QAW (ORCPT ); Wed, 29 Jun 2022 12:00:22 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46E201D327; Wed, 29 Jun 2022 09:00:22 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 056F9660194A; Wed, 29 Jun 2022 17:00:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518421; bh=AvMwfFz84n7mWn1AEG/JaA3AcQAUeEhq/lBH3WEQF0Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SA5F9Nwmb4YhGCt4aWStx+ucdgcfUsoCrC+a+7taLH/LuIY9rnvb6IS2fWskA6jYU FeWEf4kMdyYs9x7sMMBiIGBUGgizYegRR62KiTH3eDlNTfmb3/mG/PUD7H3XrRAfVh p1MQV5QSYmarlwKGn0nH//LluaDfDXpkW32qf3rkOvcWBYF2nKNvL3Sw+lvpxDFczh LMkQYxbtHp2aFcYIpt/VVT33heBLeqWVOor/FGYqJbq4o1m9dZ8cWUl2mSXz6sdjc/ afJKjzYoE7YrVbcr6hXmsW0HWmVO24WorjLkD2KuFkH+INtj9+N4FnYGhJQe/dSUrH 9lZnlBiivFKPQ== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 12/19] arm64: dts: mediatek: spherion: Add keyboard backlight Date: Wed, 29 Jun 2022 11:59:49 -0400 Message-Id: <20220629155956.1138955-13-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Spherion board has keyboard backlight controlled by the PWM signal generated by the ChromeOS EC. Enable PWM output for ChromeOS EC and add a PWM controlled LED node for the keyboard backlight. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v1) .../dts/mediatek/mt8192-asurada-spherion-r0.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/= arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index 42db81e95fae..fa3d9573f37a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -4,12 +4,28 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include =20 / { model =3D "Google Spherion (rev0 - 3)"; compatible =3D "google,spherion-rev3", "google,spherion-rev2", "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; + + pwmleds { + compatible =3D "pwm-leds"; + + led { + function =3D LED_FUNCTION_KBD_BACKLIGHT; + color =3D ; + pwms =3D <&cros_ec_pwm 0>; + max-brightness =3D <1023>; + }; + }; +}; + +&cros_ec_pwm { + status =3D "okay"; }; =20 &keyboard_controller { --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45C17C43334 for ; Wed, 29 Jun 2022 16:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229778AbiF2QBA (ORCPT ); Wed, 29 Jun 2022 12:01:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234400AbiF2QAY (ORCPT ); Wed, 29 Jun 2022 12:00:24 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C538C1E3D3; Wed, 29 Jun 2022 09:00:23 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7DFDD66019A7; Wed, 29 Jun 2022 17:00:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518422; bh=WwpPbFWF71BcviKH9+5zJIkujt+1e+ShgiMHmhnibhI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=REkGP/3Av9tLCsMI1k+M+ZSrjZOnpWOzu8IjqUxciTUidm02mtNHXYb9iQvTKLTG8 FHRh+Uo2peZRsqaTmGqkr8uGsXH8HeHl7QpQBCFMFDKTMir9LuLq+WTs0hhNrqj+Pp OlvXOMI9IzIT2vjEedlAKEZ4pFAwQsZPJI1fCMxUaTJiUh7FkQLsDvRjmiO5l7m30p qQci6w3RY76KTQ2S5+7G7x2fdK8dzJJfSli85eMHtFaR+RcDqs9udMgu/8jcykC1PX 1Jcn64IAaQ/RrvuaV41+HdfaZnmWcypdwrGUgShdISMXgBng4QrK2fLG6HZBsZtAj7 HU1pF1JSe+xSA== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 13/19] arm64: dts: mediatek: asurada: Enable XHCI Date: Wed, 29 Jun 2022 11:59:50 -0400 Message-Id: <20220629155956.1138955-14-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable XHCI controller on the Asurada platform. This allows the use of the USB ports, and therefore a rootfs can be loaded and a usable shell reached from a live USB image. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v2) Changes in v2: - Added this patch arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 6eace280c14a..69bb43f7b346 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -579,5 +579,13 @@ &uart0 { status =3D "okay"; }; =20 +&xhci { + status =3D "okay"; + + wakeup-source; + vusb33-supply =3D <&pp3300_g>; + vbus-supply =3D <&pp5000_a>; +}; + #include #include --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58F36C433EF for ; Wed, 29 Jun 2022 16:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231933AbiF2QBK (ORCPT ); Wed, 29 Jun 2022 12:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234419AbiF2QA0 (ORCPT ); Wed, 29 Jun 2022 12:00:26 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52AE420BF2; Wed, 29 Jun 2022 09:00:25 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 057AA6601A28; Wed, 29 Jun 2022 17:00:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518424; bh=gqdq1+xz9/LOr4x7zjy0Q3+2j4Bwrp8jWZIH9ix1isE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nJB2DZI25Uezk14CTkd4yAkAz0+oE4+EXH2g0f59vZgs5JIdEd1epUZS0U8pJc0AI 65y+l2bKNEx8qd40agBs44u5rvqSjq2Z5h84khUSJUkp/SrPpIYj51E7xyiJXu6Bmn LPqkuuRFNlIYs7T3ArzN/CEN692EKy4FxevXo5v6W5fgDlBIf2f6bIQMYRamuA3wFK qDgJ0YqwGpmz34uNGYM1Y9wXrDKAthDGYvstTNdmxhQ2WMVcqiU6x6cyfwdvfK20KP 9NEckruvJi+YNtZNexa4Ka5DpjhK9fd92cEu9ieT/9eKMdxe1xssJBYERbBlpes0xU At69IliUbtFgg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi Date: Wed, 29 Jun 2022 11:59:51 -0400 Message-Id: <20220629155956.1138955-15-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable MT8192's PCIe controller and add support for the MT7921e WiFi card that is present on that bus for the Asurada platform. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v3) Changes in v3: - Renamed regulator node to be generic Changes in v2: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 69bb43f7b346..e59c178d3d26 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -66,6 +66,19 @@ pp3300_u: regulator-3v3-u { vin-supply =3D <&pp3300_g>; }; =20 + pp3300_wlan: regulator-3v3-wlan { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_wlan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp3300_wlan_pins>; + enable-active-high; + gpio =3D <&pio 143 GPIO_ACTIVE_HIGH>; + }; + /* system wide switching 5.0V power rail */ pp5000_a: regulator-5v0-a { compatible =3D "regulator-fixed"; @@ -84,6 +97,17 @@ ppvar_sys: regulator-var-sys { regulator-always-on; regulator-boot-on; }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + wifi_restricted_dma_region: wifi@c0000000 { + compatible =3D "restricted-dma-pool"; + reg =3D <0 0xc0000000 0 0x4000000>; + }; + }; }; =20 &i2c0 { @@ -144,6 +168,28 @@ &i2c7 { pinctrl-0 =3D <&i2c7_pins>; }; =20 +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; + + pcie0: pcie@0,0 { + device_type =3D "pci"; + reg =3D <0x0000 0 0 0 0>; + num-lanes =3D <1>; + bus-range =3D <0x1 0x1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + wifi: wifi@0,0 { + reg =3D <0x10000 0 0 0 0x100000>, + <0x10000 0 0x100000 0 0x100000>; + memory-region =3D <&wifi_restricted_dma_region>; + }; + }; +}; + &pio { /* 220 lines */ gpio-line-names =3D "I2S_DP_LRCK", @@ -430,6 +476,34 @@ pins-bus { }; }; =20 + pcie_pins: pcie-default-pins { + pins-pcie-wake { + pinmux =3D ; + bias-pull-up; + }; + + pins-pcie-pereset { + pinmux =3D ; + }; + + pins-pcie-clkreq { + pinmux =3D ; + bias-pull-up; + }; + + pins-wifi-kill { + pinmux =3D ; /* WIFI_KILL_L */ + output-high; + }; + }; + + pp3300_wlan_pins: pp3300-wlan-pins { + pins-pcie-en-pp3300-wlan { + pinmux =3D ; + output-high; + }; + }; + spi1_pins: spi1-default-pins { pins-cs-mosi-clk { pinmux =3D , --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2110C433EF for ; Wed, 29 Jun 2022 16:01:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234439AbiF2QBM (ORCPT ); Wed, 29 Jun 2022 12:01:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234421AbiF2QA1 (ORCPT ); Wed, 29 Jun 2022 12:00:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCD0B1C935; Wed, 29 Jun 2022 09:00:26 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 79AB36601956; Wed, 29 Jun 2022 17:00:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518425; bh=SNen9swPBsEHXS8P51GX0gG1JD4BO4FIhFQGHBNVKtk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=laJDhYt22pwi+Vo2pepUI0VbSlrpfKVE9+99pydYxucpyavxNZnYi1Nl2ACq9+HB+ LRthalCQTGrpqz4vz1LhnohwytS9H65MFhfJWynYGPl8JitDy6N6nMeqK/GgQci/d7 9+NHy6TnS3j9al0+kJPxKIYDf7+hTqttqLdBln177AoCoN9wFeyOOW4qL9SIkHd9l+ pa4IARvJxESVRcwEezNEZU+E6cx+IVHfxdxidjiNXV4cTOcIvwnaKreQbN/i4QJ15q NQqp/zGUiTGU4qhvr5Ls80JcQ95czf+deolJwGbmYQnRyxU37zRp+lZ7ZpZgAWs7jy cJ4cJHL66Yxcg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 15/19] arm64: dts: mediatek: asurada: Add MT6359 PMIC Date: Wed, 29 Jun 2022 11:59:52 -0400 Message-Id: <20220629155956.1138955-16-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT6359 is the primary PMIC present on the Asurada platform. Include its dtsi and configure properties specific for the platform. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- (no changes since v2) Changes in v2: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index e59c178d3d26..31c9d1f8c80a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8192.dtsi" +#include "mt6359.dtsi" #include =20 / { @@ -168,6 +169,31 @@ &i2c7 { pinctrl-0 =3D <&i2c7_pins>; }; =20 +/* for CORE */ +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-always-on; + regulator-min-microvolt =3D <575000>; + regulator-max-microvolt =3D <575000>; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,dmic-mode =3D <1>; /* one-wire */ + mediatek,mic-type-0 =3D <2>; /* DMIC */ + mediatek,mic-type-2 =3D <2>; /* DMIC */ +}; + &pcie { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie_pins>; @@ -555,6 +581,10 @@ pins-report-sw { }; }; =20 +&pmic { + interrupts-extended =3D <&pio 214 IRQ_TYPE_LEVEL_HIGH>; +}; + &spi1 { status =3D "okay"; =20 --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A141C433EF for ; Wed, 29 Jun 2022 16:01:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233338AbiF2QBR (ORCPT ); Wed, 29 Jun 2022 12:01:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231345AbiF2QA3 (ORCPT ); Wed, 29 Jun 2022 12:00:29 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 471DD1E3C1; Wed, 29 Jun 2022 09:00:28 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id E55406601A52; Wed, 29 Jun 2022 17:00:25 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518427; bh=vZ9XvC5lN6ld9CuAEKGg4eWU+inCLtaAJj3gykR2qRQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kroCAwD9EotEFf6ntWKGoMCnuT6MkbcPEdP2kmpMrqrG8CXL3qErgDCUhnc2ud6RQ E544H3FLOb3gThZbIrN6H3KBnrVc2kB7cTWu5eKjxCE9fo6Ad2SQ/NbbUvS5Sh9LER ywFTqBoG8ofREu/tdXUSQeXa2XPLirgxMo9LJY4yTEobT7dlwRSrscU2TZ5q5LOPyY 0wep5r8udr+0OLq09pHjk6wImA/R9UQdG6ZjJ41I22ipxR/jvVrmLXimNFgem6Dm6o X9o8hDdh4d4OHJaAYCpvFnZW/FLf46TJxaAnrugiUhfUrGrquTUU9ofACRZBd8TWxf hi4B5Rvf0J74w== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 16/19] arm64: dts: mediatek: asurada: Add SPMI regulators Date: Wed, 29 Jun 2022 11:59:53 -0400 Message-Id: <20220629155956.1138955-17-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Asurada platform uses regulators from MT6315 PMICs acessible through SPMI. Add support for them. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Updated Vgpu minimum voltage to appropriate value Changes in v2: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 31c9d1f8c80a..d56c73e37633 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -7,6 +7,7 @@ #include "mt8192.dtsi" #include "mt6359.dtsi" #include +#include =20 / { aliases { @@ -679,6 +680,54 @@ cr50@0 { }; }; =20 +&spmi { + #address-cells =3D <2>; + #size-cells =3D <0>; + + mt6315_6: pmic@6 { + compatible =3D "mediatek,mt6315-regulator"; + reg =3D <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible =3D "vbuck1"; + regulator-name =3D "Vbcpu"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-compatible =3D "vbuck3"; + regulator-name =3D "Vlcpu"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible =3D "mediatek,mt6315-regulator"; + reg =3D <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible =3D "vbuck1"; + regulator-name =3D "Vgpu"; + regulator-min-microvolt =3D <606250>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + }; + }; + }; +}; + &uart0 { status =3D "okay"; }; --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A88EC43334 for ; Wed, 29 Jun 2022 16:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233847AbiF2QBV (ORCPT ); Wed, 29 Jun 2022 12:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234252AbiF2QAa (ORCPT ); Wed, 29 Jun 2022 12:00:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B691221E11; Wed, 29 Jun 2022 09:00:29 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 692CD660198D; Wed, 29 Jun 2022 17:00:27 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518428; bh=etvqQ1Sf4L9KOJ6PfLg/qIPZJ2SbAA+l1UyPzPWGVwY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vp86zMw2GSlDu1PAFaueC5lnum0u0hTa4z3UyfBNZDukkMJJnem88oC876mYn+2TP ob9W5WbSl0j237TWLhuN2RXo7IDzA5pQhTGJLWba2FrqQqekpRsV7RPlgF3wGF+PPS V14L4WzyEPibYHKM5/ShK6sp2PwEW8EB0x+cz2idB0kC0/wdSRSn1skW6RlvpbsO5i N3G09TpbZ1h0EjWdrOvpQ9rvmZaoeQEK9AbR6zh9UIoueBG/rjFggRLSk16tIx5q1V mfttr/sLp8bVGga4vW5c3mAiQxYso0bWbL0+tk95f2shNXYgXJIE97CDTwjbgCQOt5 hwmcC3ZuCoBMg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC Date: Wed, 29 Jun 2022 11:59:54 -0400 Message-Id: <20220629155956.1138955-18-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable both MMC controllers present on Asurada. MMC0 is for non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't used on all machines, but in those cases the CD interrupt is never triggered and thus it is basically as if it was disabled. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index d56c73e37633..7b89f6e552c5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -170,6 +170,46 @@ &i2c7 { pinctrl-0 =3D <&i2c7_pins>; }; =20 +&mmc0 { + status =3D "okay"; + + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + hs400-ds-delay =3D <0x12814>; + no-sdio; + no-sd; + non-removable; +}; + +&mmc1 { + status =3D "okay"; + + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_default_pins>; + pinctrl-1 =3D <&mmc1_uhs_pins>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cd-gpios =3D <&pio 17 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&mt6360_ldo5_reg>; + vqmmc-supply =3D <&mt6360_ldo3_reg>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-sdio; + no-mmc; +}; + /* for CORE */ &mt6359_vgpu11_buck_reg { regulator-always-on; @@ -503,6 +543,115 @@ pins-bus { }; }; =20 + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <10>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <10>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <10>; + bias-pull-down =3D ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-insert { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + input-enable; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + }; + pcie_pins: pcie-default-pins { pins-pcie-wake { pinmux =3D ; --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D01FCCA47C for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518430; bh=KmNdf8Lk6p2VGyZm7KaMsN4jtyH8AqBYDyDnUr4zQv8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oFvFtIfBURHS3ZZHKugEn0//ZEcsdDsTrErP5vkTXbzEcdAbsOIwyazlkOyABX1he ER6r/KqucfUgDcuSYnU9gui98HdQI+juVDsi8+An/KpWk+5304ocKtlr4elPkS7uFb H4IFywTLAg/VtTN/8VzY9Wt+KUpYIdHwqDTVn1j6UBkytA8IjkxA+ahyoNR0gdUAp/ A8yqflPdo3ZoiU2GlKq3/CMnVMmjal7PBN4UarjnQQxnSsV9362Y5zNWqnwNCQrdIq dk45ILOlvXooKcWslEcJrX4tUR+ilpKGTBte1kptsMEfCQw+KvR/36CrNWI8pdXoB1 ns3qT56GKTOvw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 18/19] arm64: dts: mediatek: asurada: Enable SCP Date: Wed, 29 Jun 2022 11:59:55 -0400 Message-Id: <20220629155956.1138955-19-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable support for the SCP co-processor present on MT8192. It is used as part of the video encoding and decoding processes. A region of memory is carved out for its use, and remoteproc setup for communication with the ChromeOS EC. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 7b89f6e552c5..a5625b3cb317 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -105,6 +105,12 @@ reserved_memory: reserved-memory { #size-cells =3D <2>; ranges; =20 + scp_mem_reserved: scp@50000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x2900000>; + no-map; + }; + wifi_restricted_dma_region: wifi@c0000000 { compatible =3D "restricted-dma-pool"; reg =3D <0 0xc0000000 0 0x4000000>; @@ -680,6 +686,12 @@ pins-pcie-en-pp3300-wlan { }; }; =20 + scp_pins: scp-pins { + pins-vreq-vao { + pinmux =3D ; + }; + }; + spi1_pins: spi1-default-pins { pins-cs-mosi-clk { pinmux =3D , @@ -735,6 +747,20 @@ &pmic { interrupts-extended =3D <&pio 214 IRQ_TYPE_LEVEL_HIGH>; }; =20 +&scp { + status =3D "okay"; + + firmware-name =3D "mediatek/mt8192/scp.img"; + memory-region =3D <&scp_mem_reserved>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&scp_pins>; + + cros-ec { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; +}; + &spi1 { status =3D "okay"; =20 --=20 2.36.1 From nobody Sat Sep 21 23:09:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64314C433EF for ; Wed, 29 Jun 2022 16:01:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234353AbiF2QB3 (ORCPT ); Wed, 29 Jun 2022 12:01:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234058AbiF2QAm (ORCPT ); Wed, 29 Jun 2022 12:00:42 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48CE42C644; Wed, 29 Jun 2022 09:00:33 -0700 (PDT) Received: from notapiano.myfiosgateway.com (pool-98-113-53-228.nycmny.fios.verizon.net [98.113.53.228]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 61E6E66019AC; Wed, 29 Jun 2022 17:00:30 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1656518431; bh=fWpLVNkaRd2J8/GN0NiVTcm+/j+WzfBVE0/fxSI1x5A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DY92GFjN3oeuKinw8Ew49bJgJxgOWoEzUt8A8bZVJPRHE59LO3545axbqRbXd5QI6 NOvolx1mgJgf+roEOHSN7NuOJQ0r6maVhCTo9p/20oueU1YT8lQYaE3TusW4e13aqr Wgu7phTuv8d70Zc6IPA7puSWOvI4bWE4Ja98bu7eOeSwM4CGQ9n6g4oCbh/YlShGuW KJ69HN2yvBHPBnC+GdC/nehh+L3J4vxiQ25nRQYnVCiERoBvR/UOVrNpAmN9USsz9c G6OHQ6n+q17lHnOZDCbgPHHs/6yvDDjHN52lMDHILXCKmiCK5/ReyFXGzmOYbOelxW TGpBJe7lQUP0g== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 19/19] arm64: dts: mediatek: asurada: Add SPI NOR flash memory Date: Wed, 29 Jun 2022 11:59:56 -0400 Message-Id: <20220629155956.1138955-20-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629155956.1138955-1-nfraprado@collabora.com> References: <20220629155956.1138955-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the SPI NOR flash memory present on the Asurada platform. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- Changes in v4: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index a5625b3cb317..4b314435f8fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -241,6 +241,23 @@ &mt6359codec { mediatek,mic-type-2 =3D <2>; /* DMIC */ }; =20 +&nor_flash { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_flash_pins>; + assigned-clocks =3D <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6_D8>; + + flash@0 { + compatible =3D "winbond,w25q64jwm", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <52000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + }; +}; + &pcie { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie_pins>; @@ -658,6 +675,29 @@ pins-clk { }; }; =20 + nor_flash_pins: nor-flash-default-pins { + pins-cs-io1 { + pinmux =3D , + ; + input-enable; + bias-pull-up; + drive-strength =3D <10>; + }; + + pins-io0 { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <10>; + }; + + pins-clk { + pinmux =3D ; + input-enable; + bias-pull-up; + drive-strength =3D <10>; + }; + }; + pcie_pins: pcie-default-pins { pins-pcie-wake { pinmux =3D ; --=20 2.36.1