From nobody Sun Apr 19 15:23:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6832CCCA487 for ; Wed, 29 Jun 2022 09:17:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232030AbiF2JRa (ORCPT ); Wed, 29 Jun 2022 05:17:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232448AbiF2JR1 (ORCPT ); Wed, 29 Jun 2022 05:17:27 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F18392CDDE for ; Wed, 29 Jun 2022 02:17:25 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id d17so15799660wrc.10 for ; Wed, 29 Jun 2022 02:17:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9d56+qD56YHFFQAE+2WwcEsFKc57gJBmjSIIl+R37lQ=; b=lxV8eW9VPicdRuK1A8Kd7B/y7bhJ3TgYzKMeOC8FYef8Qqt1ieGWtgusL72CSC6iYm 9RwTdG58eCR5zsPKbHDn5jqKigQTSOh8cq7sTnZYAlqpRMb9HnhLAkE1whMMT+tFixm/ eQTaNTmM3/IsNdYX2EUlMWK0gFWv+aS0Cz0k+jAY0hzwDVBHfrnzrm3ArNuFXsqT4HLE L/eVLMsKecTcLpwAWcG17lV7C7gBq9s1E2Xeft6JR+8Y+tm3pHW9Nys7RvWxrbkkcyNU 3ZeiHIvsldjryRoXq0Yz5khC+Mg2G4UeknM069sLDamFyaNlGyhDtRCgoeb7bpKaJylL 4xPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9d56+qD56YHFFQAE+2WwcEsFKc57gJBmjSIIl+R37lQ=; b=xCk/7eWUmiP0pHYOt4tN+k5/zSVkvQK0tw2ckq8AuJvnSpN3zyTCd15AmH9YDgvdeE 6Dd7hI9cNzXfn6R0+T2S5A76mYW3u3x+fOQaVHg4z5LgRieVbecVCB0CTlp8hS1x9QEM y9CocfVg3zmCwiXf84auaQulxpzQLtklIEuEEWsgSaBZLT4m623aVQoOwMAlJaJiG+Mh giZJZkREcAIZqtUcw+zSxFgAO31/wQAshlwIekNao8vLNykkeBzfdSXCVbuHLgjBiupV Zf+A8y28QrMnZybDTSIW5Cg21uJpf8jKeIqFW6S5xLSQ+z/fGHrCr5x4B2Y7frTSAsyr a6OQ== X-Gm-Message-State: AJIora+F7C1xgrKC3W+tUPHwKHF+J/ek7ClYEWtcJVy5Ti0WCIcvE777 7ZtTBkJCEH0B8cWpl7NLUM+DcQ== X-Google-Smtp-Source: AGRyM1tqehhbHavpAmwF3OC2TUC2FdkUf9Z1g0NMG/efzBXL5Dqo7aiPTlaYcqdns7tuK7jnMCj4cg== X-Received: by 2002:a05:6000:904:b0:21a:3dca:4297 with SMTP id bz4-20020a056000090400b0021a3dca4297mr2009210wrb.487.1656494244029; Wed, 29 Jun 2022 02:17:24 -0700 (PDT) Received: from srini-hackbase.lan (cpc90716-aztw32-2-0-cust825.18-1.cable.virginm.net. [86.26.103.58]) by smtp.gmail.com with ESMTPSA id t18-20020a05600c199200b003a03a8475bfsm2896443wmq.16.2022.06.29.02.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 02:17:23 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, linus.walleij@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sm8450 lpass lpi pinctrl bindings Date: Wed, 29 Jun 2022 10:17:15 +0100 Message-Id: <20220629091716.68771-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629091716.68771-1-srinivas.kandagatla@linaro.org> References: <20220629091716.68771-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree binding Documentation details for Qualcomm SM8450 LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. Signed-off-by: Srinivas Kandagatla --- .../qcom,sm8450-lpass-lpi-pinctrl.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8450-l= pass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 000000000000..b49d70b9ba9a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8450-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 23 + + function: + enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, + dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, + dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, + qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_= ws, + i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, + wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data, + slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data, + ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d, + ext_mclk1_e ] + + description: + Specify the alternative function to be configured for the specif= ied + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@3440000 { + compatible =3D "qcom,sm8450-lpass-lpi-pinctrl"; + reg =3D <0x3440000 0x20000>, + <0x34d0000 0x10000>; + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPL= E_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE= _NO>; + clock-names =3D "core", "audio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpi_tlmm 0 0 23>; + }; --=20 2.25.1 From nobody Sun Apr 19 15:23:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12B7FC433EF for ; Wed, 29 Jun 2022 09:17:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232536AbiF2JRe (ORCPT ); Wed, 29 Jun 2022 05:17:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231831AbiF2JR2 (ORCPT ); Wed, 29 Jun 2022 05:17:28 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 325642CDF1 for ; Wed, 29 Jun 2022 02:17:27 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id m184so8943622wme.1 for ; Wed, 29 Jun 2022 02:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fGzsSbhePCvlbCCPw/IqM5avct7w4V5zMeMb12IcdyU=; b=mG0wG4qjmKMk4StUY06VuS8kxxjkwd0El67xTIHh8025crOCogWI+lxiO3cs4hzhIi x9qO3yxq7lbp9lCbayIRcoqxXbeudfrBdjCd8diYXXb+KH7rzWSak+/9E+1C1MbL/cQD 8W1fkzzCxEeFpVzF7KrRA6qwy/Wa/HjKDYT8n1SBxB5XZMNHOnAy6/PK/ANcobjyJC3H xkb6zvIJ9r3uhSqrOFbp7WysUAWCHySHiCTVUBlNG2aZArOeJ9j3u+LfFo4OvMurUZAJ s56431xJuaxsmdnP8deV323OFChtFwYyrFczHGpMFQqJpGzBeiIHwjW6HPyf5pSSTg45 DnEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fGzsSbhePCvlbCCPw/IqM5avct7w4V5zMeMb12IcdyU=; b=E99ZjSg84MSAF0hG+lp1mzH2cHUPrjB8eFy90VfBIqojmUF48M7/kxSYuKr5aYa5v/ ge4H4gGLrIToGOD7vVbdoM5gdpzAJfTD7ldbHws9kIwSuEG5vLIrQgc9LpgDipTirGc+ UU4H/e+2hxmwMhxJ3xpXo2jbrDVZxBk5z7gfQqIXBghmMd/cLIjQQPXse+QzRWDmUxJp 6DDcUiPYiXhMNBSU4AsrxKfRMKuRuiCrMHF0q8IVxpfI8fIR93pgZSUkJgCruIFBXcHB k2hTBKOVpHfHbGO9+H7V503jW2HCkTT2eN1FcKcjkfIyxTt6VJWAHQQFy/EpZVzyg3q3 W95w== X-Gm-Message-State: AJIora85RHm2fB5IfJqFoW0j1CZAj4niy5IqKN4FtxQRiD2U0EJne9Xe DPlJ87r8zDaOB3RBOY+VPrNDwn8q+E4TN7cO X-Google-Smtp-Source: AGRyM1sQWP9tn/Cvmm8ojk9Iyih7EZQ3PdnEIvrYPyhbMZtF7+IDieHwRiacJaFLeBuoLWLU3LZTYA== X-Received: by 2002:a1c:19c3:0:b0:39c:6479:3ca with SMTP id 186-20020a1c19c3000000b0039c647903camr4269385wmz.27.1656494246739; Wed, 29 Jun 2022 02:17:26 -0700 (PDT) Received: from srini-hackbase.lan (cpc90716-aztw32-2-0-cust825.18-1.cable.virginm.net. [86.26.103.58]) by smtp.gmail.com with ESMTPSA id t18-20020a05600c199200b003a03a8475bfsm2896443wmq.16.2022.06.29.02.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 02:17:25 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, linus.walleij@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/2] pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver Date: Wed, 29 Jun 2022 10:17:16 +0100 Message-Id: <20220629091716.68771-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629091716.68771-1-srinivas.kandagatla@linaro.org> References: <20220629091716.68771-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8450. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 240 ++++++++++++++++++ 3 files changed, 250 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 3daeb9772391..c4d6089bf38c 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -373,6 +373,15 @@ config PINCTRL_SM8450 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8450 platform. =20 +config PINCTRL_SM8450_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller drive= r" + depends on GPIOLIB + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8450 platfo= rm. + config PINCTRL_LPASS_LPI tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" select PINMUX diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4f0ee7597f81..e3de2cd6e1d8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,4 +43,5 @@ obj-$(CONFIG_PINCTRL_SM8250) +=3D pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) +=3D pinctrl-sm8250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8350) +=3D pinctrl-sm8350.o obj-$(CONFIG_PINCTRL_SM8450) +=3D pinctrl-sm8450.o +obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) +=3D pinctrl-sm8450-lpass-lpi.o obj-$(CONFIG_PINCTRL_LPASS_LPI) +=3D pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8450-lpass-lpi.c new file mode 100644 index 000000000000..c3c8c34148f1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_i2s4_clk, + LPI_MUX_i2s4_data, + LPI_MUX_i2s4_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] =3D { 0 }; +static int gpio1_pins[] =3D { 1 }; +static int gpio2_pins[] =3D { 2 }; +static int gpio3_pins[] =3D { 3 }; +static int gpio4_pins[] =3D { 4 }; +static int gpio5_pins[] =3D { 5 }; +static int gpio6_pins[] =3D { 6 }; +static int gpio7_pins[] =3D { 7 }; +static int gpio8_pins[] =3D { 8 }; +static int gpio9_pins[] =3D { 9 }; +static int gpio10_pins[] =3D { 10 }; +static int gpio11_pins[] =3D { 11 }; +static int gpio12_pins[] =3D { 12 }; +static int gpio13_pins[] =3D { 13 }; +static int gpio14_pins[] =3D { 14 }; +static int gpio15_pins[] =3D { 15 }; +static int gpio16_pins[] =3D { 16 }; +static int gpio17_pins[] =3D { 17 }; +static int gpio18_pins[] =3D { 18 }; +static int gpio19_pins[] =3D { 19 }; +static int gpio20_pins[] =3D { 20 }; +static int gpio21_pins[] =3D { 21 }; +static int gpio22_pins[] =3D { 22 }; + +static const struct pinctrl_pin_desc sm8450_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2", "gp= io14" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5", "gp= io15" }; +static const char * const dmic1_clk_groups[] =3D { "gpio6" }; +static const char * const dmic1_data_groups[] =3D { "gpio7" }; +static const char * const dmic2_clk_groups[] =3D { "gpio8" }; +static const char * const dmic2_data_groups[] =3D { "gpio9" }; +static const char * const dmic4_clk_groups[] =3D { "gpio17" }; +static const char * const dmic4_data_groups[] =3D { "gpio18" }; +static const char * const i2s2_clk_groups[] =3D { "gpio10" }; +static const char * const i2s2_ws_groups[] =3D { "gpio11" }; +static const char * const dmic3_clk_groups[] =3D { "gpio12" }; +static const char * const dmic3_data_groups[] =3D { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] =3D { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] =3D { "gpio1" }; +static const char * const qua_mi2s_data_groups[] =3D { "gpio2", "gpio3", "= gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] =3D { "gpio6" }; +static const char * const i2s1_ws_groups[] =3D { "gpio7" }; +static const char * const i2s1_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] =3D { "gpio10" }; +static const char * const wsa_swr_data_groups[] =3D { "gpio11" }; +static const char * const wsa2_swr_clk_groups[] =3D { "gpio15" }; +static const char * const wsa2_swr_data_groups[] =3D { "gpio16" }; +static const char * const i2s2_data_groups[] =3D { "gpio15", "gpio16" }; +static const char * const i2s4_ws_groups[] =3D { "gpio13" }; +static const char * const i2s4_clk_groups[] =3D { "gpio12" }; +static const char * const i2s4_data_groups[] =3D { "gpio17", "gpio18" }; +static const char * const slimbus_clk_groups[] =3D { "gpio19"}; +static const char * const i2s3_clk_groups[] =3D { "gpio19"}; +static const char * const i2s3_ws_groups[] =3D { "gpio20"}; +static const char * const i2s3_data_groups[] =3D { "gpio21", "gpio22"}; +static const char * const slimbus_data_groups[] =3D { "gpio20"}; +static const char * const ext_mclk1_c_groups[] =3D { "gpio5" }; +static const char * const ext_mclk1_b_groups[] =3D { "gpio9" }; +static const char * const ext_mclk1_a_groups[] =3D { "gpio13" }; +static const char * const ext_mclk1_d_groups[] =3D { "gpio14" }; +static const char * const ext_mclk1_e_groups[] =3D { "gpio22" }; + +static const struct lpi_pingroup sm8450_groups[] =3D { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s4_clk, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s4_ws, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _), + LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s4_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s4_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, ext_mclk1_e, _, _), +}; + +static const struct lpi_function sm8450_functions[] =3D { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(i2s4_clk), + LPI_FUNCTION(i2s4_data), + LPI_FUNCTION(i2s4_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), +}; + +static const struct lpi_pinctrl_variant_data sm8450_lpi_data =3D { + .pins =3D sm8450_lpi_pins, + .npins =3D ARRAY_SIZE(sm8450_lpi_pins), + .groups =3D sm8450_groups, + .ngroups =3D ARRAY_SIZE(sm8450_groups), + .functions =3D sm8450_functions, + .nfunctions =3D ARRAY_SIZE(sm8450_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sm8450-lpass-lpi-pinctrl", + .data =3D &sm8450_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1