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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id t2-20020a056402020200b00437db6acaeesm432173edv.95.2022.06.29.00.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 00:52:55 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring Subject: [PATCH v5 1/4] dt-bindings: interconnect: qcom,msm8998-cpu-bwmon: add BWMON device Date: Wed, 29 Jun 2022 09:52:47 +0200 Message-Id: <20220629075250.17610-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> References: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings for the Qualcomm Bandwidth Monitor device providing performance data on interconnects. The bindings describe only BWMON CPU (version 4), e.g. the instance which appeared for the first on Qualcomm MSM8998 SoC and is also used on SDM845. This BWMON device sits between CPU and Last Level Cache Controller. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Acked-by: Georgi Djakov --- .../interconnect/qcom,msm8998-cpu-bwmon.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm= 8998-cpu-bwmon.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-cp= u-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-= cpu-bwmon.yaml new file mode 100644 index 000000000000..b6ced53b92f7 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-cpu-bwmon= .yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8998-cpu-bwmon.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Interconnect Bandwidth Monitor + +maintainers: + - Krzysztof Kozlowski + +description: + Bandwidth Monitor measures current throughput on buses between various N= oC + fabrics and provides information when it crosses configured thresholds. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,sdm845-cpu-bwmon + - const: qcom,msm8998-cpu-bwmon + - const: qcom,msm8998-cpu-bwmon # BWMON v4 + + interconnects: + maxItems: 1 + + interrupts: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + reg: + # Currently described BWMON v4 and v5 use one register address space. + # BWMON v2 uses two register spaces - not yet described. + maxItems: 1 + +required: + - compatible + - interconnects + - interrupts + - operating-points-v2 + - opp-table + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + pmu@1436400 { + compatible =3D "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon"; + reg =3D <0x01436400 0x600>; + interrupts =3D ; + interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLA= VE_LLCC 3>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + opp-0 { + opp-peak-kBps =3D <4800000>; + }; + opp-1 { + opp-peak-kBps =3D <9216000>; + }; + opp-2 { + opp-peak-kBps =3D <15052800>; + }; + opp-3 { + opp-peak-kBps =3D <20889600>; + }; + opp-4 { + opp-peak-kBps =3D <25497600>; + }; + }; + }; --=20 2.34.1 From nobody Sun Apr 26 10:55:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 016E6C433EF for ; Wed, 29 Jun 2022 07:53:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232016AbiF2Hxc (ORCPT ); Wed, 29 Jun 2022 03:53:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232608AbiF2HxL (ORCPT ); Wed, 29 Jun 2022 03:53:11 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4E3A39B8F for ; Wed, 29 Jun 2022 00:52:59 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id fd6so20999592edb.5 for ; Wed, 29 Jun 2022 00:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NVOkXLmoRORRDlnK8ZUeIL+gfaMag/9GYHUkDD1/2+A=; b=GFAIyXPMCvtmzn/WTlueMGio4NTjs+kt73DyQldj8eYka+NV2PVXWMl5APQ5wLoJsN A4aHo3W6cQl+o94595z4m5XTe8WS6/8ZUu2pT5RRg2/3AxUDgLMsG0ZIy2H8/k+FGu1e 4zmIEb271W0mvHMvRoEWAqu+kjHSLvhI8uSO8HlzPJDPb5hdzrmnHM2riAwvPfrnr/qA e3XxqcSafwqGUiJzoFZt98rI8Uy/XRYiy8ohlA+oCMCKqJEMxmbSbxtCXqHGPY/HPLyV PoBpMp1y9si1V3MBA4fnj0YI7a/CcUCfFsiOAzH8Y0iNBVL/smFeFRssx4+0uBb9+VdH w0ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NVOkXLmoRORRDlnK8ZUeIL+gfaMag/9GYHUkDD1/2+A=; b=Hm/ohm/IJPNhR6QWKsos9xa9Ng8kTsvB4KcLeaMKYYFbnS6BtG7IJL3QFokMaKDDyK Su/2KNharaknpHsr259/Dy7vUVsoeqKpLctHgHVvg3BZNtb7y5h/87tVrTeDlYPANFwu QhVSsBtJrrt4t2ugZTlhW/mYihttkkG0NI3vERhmGtaRqe5lM4/Nct1IQhWuuiMUnrYK LUcT3YfHKAwPo6tnOthUeQaM+78baFD9+QoZdTAdeurt9eokBQrJALMAIkCtYwzIxZil 6uRkrojJU8wVgEhHd9aBkDobJ2OhZAdA0kZnwFuq8x8pvCZU2jOjvYZBm6+OT+I2vcRU jMxg== X-Gm-Message-State: AJIora+MJO6OZWb4N3924D+c7yMhUSKqPMkTQRDgZbGs1W46WW8JJM4R kqHbCKwiWgMJv8cxng42QrLhpA== X-Google-Smtp-Source: AGRyM1uXsU6gydS3qaBCPRY0yUuaB5FrBB9jqOH9EHysNs8uKnwjsvft604h6lNls6tkVN9bupQQmA== X-Received: by 2002:a05:6402:2741:b0:434:fe8a:1f96 with SMTP id z1-20020a056402274100b00434fe8a1f96mr2513145edd.331.1656489177835; Wed, 29 Jun 2022 00:52:57 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id t2-20020a056402020200b00437db6acaeesm432173edv.95.2022.06.29.00.52.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 00:52:56 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thara Gopinath Subject: [PATCH v5 2/4] soc: qcom: icc-bwmon: Add bandwidth monitoring driver Date: Wed, 29 Jun 2022 09:52:48 +0200 Message-Id: <20220629075250.17610-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> References: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Bandwidth monitoring (BWMON) sits between various subsytems like CPU, GPU, Last Level caches and memory subsystem. The BWMON can be configured to monitor the data throuhput between memory and other subsytems. The throughput is measured within specified sampling window and is used to vote for corresponding interconnect bandwidth. Current implementation brings support for BWMON v4, used for example on SDM845 to measure bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Co-developed-by: Thara Gopinath Signed-off-by: Thara Gopinath Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 7 + drivers/soc/qcom/Kconfig | 15 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/icc-bwmon.c | 421 +++++++++++++++++++++++++++++++++++ 4 files changed, 444 insertions(+) create mode 100644 drivers/soc/qcom/icc-bwmon.c diff --git a/MAINTAINERS b/MAINTAINERS index 6157e706ed02..968a0494d768 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16376,6 +16376,13 @@ S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt F: drivers/i2c/busses/i2c-qcom-cci.c =20 +QUALCOMM INTERCONNECT BWMON DRIVER +M: Krzysztof Kozlowski +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/interconnect/qcom,msm8998-cpu-bwmon.y= aml +F: drivers/soc/qcom/icc-bwmon.c + QUALCOMM IOMMU M: Rob Clark L: iommu@lists.linux-foundation.org diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e718b8735444..35c5192dcfc7 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -228,4 +228,19 @@ config QCOM_APR application processor and QDSP6. APR is used by audio driver to configure QDSP6 ASM, ADM and AFE modules. + +config QCOM_ICC_BWMON + tristate "QCOM Interconnect Bandwidth Monitor driver" + depends on ARCH_QCOM || COMPILE_TEST + select PM_OPP + help + Sets up driver monitoring bandwidth on various interconnects and + based on that voting for interconnect bandwidth, adjusting their + speed to current demand. + Current implementation brings support for BWMON v4, used for example + on SDM845 to measure bandwidth between CPU (gladiator_noc) and Last + Level Cache (memnoc). Usage of this BWMON allows to remove fixed + bandwidth votes from cpufreq (CPU nodes) thus achieve high memory + throughput even with lower CPU frequencies. + endmenu diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 70d5de69fd7b..d66604aff2b0 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_QCOM_LLCC) +=3D llcc-qcom.o obj-$(CONFIG_QCOM_RPMHPD) +=3D rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) +=3D rpmpd.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=3D kryo-l2-accessors.o +obj-$(CONFIG_QCOM_ICC_BWMON) +=3D icc-bwmon.o diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c new file mode 100644 index 000000000000..1eed075545db --- /dev/null +++ b/drivers/soc/qcom/icc-bwmon.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021-2022 Linaro Ltd + * Author: Krzysztof Kozlowski , based on + * previous work of Thara Gopinath and msm-4.9 downstream sources. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The BWMON samples data throughput within 'sample_ms' time. With three + * configurable thresholds (Low, Medium and High) gives four windows (call= ed + * zones) of current bandwidth: + * + * Zone 0: byte count < THRES_LO + * Zone 1: THRES_LO < byte count < THRES_MED + * Zone 2: THRES_MED < byte count < THRES_HIGH + * Zone 3: THRES_HIGH < byte count + * + * Zones 0 and 2 are not used by this driver. + */ + +/* Internal sampling clock frequency */ +#define HW_TIMER_HZ 19200000 + +#define BWMON_GLOBAL_IRQ_STATUS 0x0 +#define BWMON_GLOBAL_IRQ_CLEAR 0x8 +#define BWMON_GLOBAL_IRQ_ENABLE 0xc +#define BWMON_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) + +#define BWMON_IRQ_STATUS 0x100 +#define BWMON_IRQ_STATUS_ZONE_SHIFT 4 +#define BWMON_IRQ_CLEAR 0x108 +#define BWMON_IRQ_ENABLE 0x10c +#define BWMON_IRQ_ENABLE_ZONE1_SHIFT 5 +#define BWMON_IRQ_ENABLE_ZONE2_SHIFT 6 +#define BWMON_IRQ_ENABLE_ZONE3_SHIFT 7 +#define BWMON_IRQ_ENABLE_MASK (BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT) | \ + BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT)) + +#define BWMON_ENABLE 0x2a0 +#define BWMON_ENABLE_ENABLE BIT(0) + +#define BWMON_CLEAR 0x2a4 +#define BWMON_CLEAR_CLEAR BIT(0) + +#define BWMON_SAMPLE_WINDOW 0x2a8 +#define BWMON_THRESHOLD_HIGH 0x2ac +#define BWMON_THRESHOLD_MED 0x2b0 +#define BWMON_THRESHOLD_LOW 0x2b4 + +#define BWMON_ZONE_ACTIONS 0x2b8 +/* + * Actions to perform on some zone 'z' when current zone hits the threshol= d: + * Increment counter of zone 'z' + */ +#define BWMON_ZONE_ACTIONS_INCREMENT(z) (0x2 << ((z) * 2)) +/* Clear counter of zone 'z' */ +#define BWMON_ZONE_ACTIONS_CLEAR(z) (0x1 << ((z) * 2)) + +/* Zone 0 threshold hit: Clear zone count */ +#define BWMON_ZONE_ACTIONS_ZONE0 (BWMON_ZONE_ACTIONS_CLEAR(0)) + +/* Zone 1 threshold hit: Increment zone count & clear lower zones */ +#define BWMON_ZONE_ACTIONS_ZONE1 (BWMON_ZONE_ACTIONS_INCREMENT(1) | \ + BWMON_ZONE_ACTIONS_CLEAR(0)) + +/* Zone 2 threshold hit: Increment zone count & clear lower zones */ +#define BWMON_ZONE_ACTIONS_ZONE2 (BWMON_ZONE_ACTIONS_INCREMENT(2) | \ + BWMON_ZONE_ACTIONS_CLEAR(1) | \ + BWMON_ZONE_ACTIONS_CLEAR(0)) + +/* Zone 3 threshold hit: Increment zone count & clear lower zones */ +#define BWMON_ZONE_ACTIONS_ZONE3 (BWMON_ZONE_ACTIONS_INCREMENT(3) | \ + BWMON_ZONE_ACTIONS_CLEAR(2) | \ + BWMON_ZONE_ACTIONS_CLEAR(1) | \ + BWMON_ZONE_ACTIONS_CLEAR(0)) +/* Value for BWMON_ZONE_ACTIONS */ +#define BWMON_ZONE_ACTIONS_DEFAULT (BWMON_ZONE_ACTIONS_ZONE0 | \ + BWMON_ZONE_ACTIONS_ZONE1 << 8 | \ + BWMON_ZONE_ACTIONS_ZONE2 << 16 | \ + BWMON_ZONE_ACTIONS_ZONE3 << 24) + +/* + * There is no clear documentation/explanation of BWMON_THRESHOLD_COUNT + * register. Based on observations, this is number of times one threshold = has to + * be reached, to trigger interrupt in given zone. + * + * 0xff are maximum values meant to ignore the zones 0 and 2. + */ +#define BWMON_THRESHOLD_COUNT 0x2bc +#define BWMON_THRESHOLD_COUNT_ZONE1_SHIFT 8 +#define BWMON_THRESHOLD_COUNT_ZONE2_SHIFT 16 +#define BWMON_THRESHOLD_COUNT_ZONE3_SHIFT 24 +#define BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT 0xff +#define BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT 0xff + +/* BWMONv4 count registers use count unit of 64 kB */ +#define BWMON_COUNT_UNIT_KB 64 +#define BWMON_ZONE_COUNT 0x2d8 +#define BWMON_ZONE_MAX(zone) (0x2e0 + 4 * (zone)) + +struct icc_bwmon_data { + unsigned int sample_ms; + unsigned int default_highbw_kbps; + unsigned int default_medbw_kbps; + unsigned int default_lowbw_kbps; + u8 zone1_thres_count; + u8 zone3_thres_count; +}; + +struct icc_bwmon { + struct device *dev; + void __iomem *base; + int irq; + + unsigned int default_lowbw_kbps; + unsigned int sample_ms; + unsigned int max_bw_kbps; + unsigned int min_bw_kbps; + unsigned int target_kbps; + unsigned int current_kbps; +}; + +static void bwmon_clear_counters(struct icc_bwmon *bwmon) +{ + /* + * Clear counters. The order and barriers are + * important. Quoting downstream Qualcomm msm-4.9 tree: + * + * The counter clear and IRQ clear bits are not in the same 4KB + * region. So, we need to make sure the counter clear is completed + * before we try to clear the IRQ or do any other counter operations. + */ + writel(BWMON_CLEAR_CLEAR, bwmon->base + BWMON_CLEAR); +} + +static void bwmon_clear_irq(struct icc_bwmon *bwmon) +{ + /* + * Clear zone and global interrupts. The order and barriers are + * important. Quoting downstream Qualcomm msm-4.9 tree: + * + * Synchronize the local interrupt clear in mon_irq_clear() + * with the global interrupt clear here. Otherwise, the CPU + * may reorder the two writes and clear the global interrupt + * before the local interrupt, causing the global interrupt + * to be retriggered by the local interrupt still being high. + * + * Similarly, because the global registers are in a different + * region than the local registers, we need to ensure any register + * writes to enable the monitor after this call are ordered with the + * clearing here so that local writes don't happen before the + * interrupt is cleared. + */ + writel(BWMON_IRQ_ENABLE_MASK, bwmon->base + BWMON_IRQ_CLEAR); + writel(BIT(0), bwmon->base + BWMON_GLOBAL_IRQ_CLEAR); +} + +static void bwmon_disable(struct icc_bwmon *bwmon) +{ + /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ + writel(0x0, bwmon->base + BWMON_GLOBAL_IRQ_ENABLE); + writel(0x0, bwmon->base + BWMON_IRQ_ENABLE); + + /* + * Disable bwmon. Must happen before bwmon_clear_irq() to avoid spurious + * IRQ. + */ + writel(0x0, bwmon->base + BWMON_ENABLE); +} + +static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) +{ + /* Enable interrupts */ + writel(BWMON_GLOBAL_IRQ_ENABLE_ENABLE, + bwmon->base + BWMON_GLOBAL_IRQ_ENABLE); + writel(irq_enable, bwmon->base + BWMON_IRQ_ENABLE); + + /* Enable bwmon */ + writel(BWMON_ENABLE_ENABLE, bwmon->base + BWMON_ENABLE); +} + +static unsigned int bwmon_kbps_to_count(unsigned int kbps) +{ + return kbps / BWMON_COUNT_UNIT_KB; +} + +static void bwmon_set_threshold(struct icc_bwmon *bwmon, unsigned int reg, + unsigned int kbps) +{ + unsigned int thres; + + thres =3D mult_frac(bwmon_kbps_to_count(kbps), bwmon->sample_ms, + MSEC_PER_SEC); + writel_relaxed(thres, bwmon->base + reg); +} + +static void bwmon_start(struct icc_bwmon *bwmon, + const struct icc_bwmon_data *data) +{ + unsigned int thres_count; + int window; + + bwmon_clear_counters(bwmon); + + window =3D mult_frac(bwmon->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC); + /* Maximum sampling window: 0xfffff */ + writel_relaxed(window, bwmon->base + BWMON_SAMPLE_WINDOW); + + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_HIGH, + data->default_highbw_kbps); + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_MED, + data->default_medbw_kbps); + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_LOW, + data->default_lowbw_kbps); + + thres_count =3D data->zone3_thres_count << BWMON_THRESHOLD_COUNT_ZONE3_SH= IFT | + BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT << BWMON_THRESHOLD_COUNT_ZONE2= _SHIFT | + data->zone1_thres_count << BWMON_THRESHOLD_COUNT_ZONE1_SHIFT | + BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT; + writel_relaxed(thres_count, bwmon->base + BWMON_THRESHOLD_COUNT); + writel_relaxed(BWMON_ZONE_ACTIONS_DEFAULT, + bwmon->base + BWMON_ZONE_ACTIONS); + /* Write barriers in bwmon_clear_irq() */ + + bwmon_clear_irq(bwmon); + bwmon_enable(bwmon, BWMON_IRQ_ENABLE_MASK); +} + +static irqreturn_t bwmon_intr(int irq, void *dev_id) +{ + struct icc_bwmon *bwmon =3D dev_id; + unsigned int status, max; + int zone; + + status =3D readl(bwmon->base + BWMON_IRQ_STATUS); + status &=3D BWMON_IRQ_ENABLE_MASK; + if (!status) { + /* + * Only zone 1 and zone 3 interrupts are enabled but zone 2 + * threshold could be hit and trigger interrupt even if not + * enabled. + * Such spurious interrupt might come with valuable max count or + * not, so solution would be to always check all + * BWMON_ZONE_MAX() registers to find the highest value. + * Such case is currently ignored. + */ + return IRQ_NONE; + } + + bwmon_disable(bwmon); + + zone =3D get_bitmask_order(status >> BWMON_IRQ_STATUS_ZONE_SHIFT) - 1; + /* + * Zone max bytes count register returns count units within sampling + * window. Downstream kernel for BWMONv4 (called BWMON type 2 in + * downstream) always increments the max bytes count by one. + */ + max =3D readl(bwmon->base + BWMON_ZONE_MAX(zone)) + 1; + max *=3D BWMON_COUNT_UNIT_KB; + bwmon->target_kbps =3D mult_frac(max, MSEC_PER_SEC, bwmon->sample_ms); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t bwmon_intr_thread(int irq, void *dev_id) +{ + struct icc_bwmon *bwmon =3D dev_id; + unsigned int irq_enable =3D 0; + struct dev_pm_opp *opp, *target_opp; + unsigned int bw_kbps, up_kbps, down_kbps; + + bw_kbps =3D bwmon->target_kbps; + + target_opp =3D dev_pm_opp_find_bw_ceil(bwmon->dev, &bw_kbps, 0); + if (IS_ERR(target_opp) && PTR_ERR(target_opp) =3D=3D -ERANGE) + target_opp =3D dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0); + + bwmon->target_kbps =3D bw_kbps; + + bw_kbps--; + opp =3D dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0); + if (IS_ERR(opp) && PTR_ERR(opp) =3D=3D -ERANGE) + down_kbps =3D bwmon->target_kbps; + else + down_kbps =3D bw_kbps; + + up_kbps =3D bwmon->target_kbps + 1; + + if (bwmon->target_kbps >=3D bwmon->max_bw_kbps) + irq_enable =3D BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT); + else if (bwmon->target_kbps <=3D bwmon->min_bw_kbps) + irq_enable =3D BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT); + else + irq_enable =3D BWMON_IRQ_ENABLE_MASK; + + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_HIGH, up_kbps); + bwmon_set_threshold(bwmon, BWMON_THRESHOLD_MED, down_kbps); + /* Write barriers in bwmon_clear_counters() */ + bwmon_clear_counters(bwmon); + bwmon_clear_irq(bwmon); + bwmon_enable(bwmon, irq_enable); + + if (bwmon->target_kbps =3D=3D bwmon->current_kbps) + goto out; + + dev_pm_opp_set_opp(bwmon->dev, target_opp); + bwmon->current_kbps =3D bwmon->target_kbps; + +out: + dev_pm_opp_put(target_opp); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + return IRQ_HANDLED; +} + +static int bwmon_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dev_pm_opp *opp; + struct icc_bwmon *bwmon; + const struct icc_bwmon_data *data; + int ret; + + bwmon =3D devm_kzalloc(dev, sizeof(*bwmon), GFP_KERNEL); + if (!bwmon) + return -ENOMEM; + + data =3D of_device_get_match_data(dev); + + bwmon->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bwmon->base)) { + dev_err(dev, "failed to map bwmon registers\n"); + return PTR_ERR(bwmon->base); + } + + bwmon->irq =3D platform_get_irq(pdev, 0); + if (bwmon->irq < 0) { + dev_err(dev, "failed to acquire bwmon IRQ\n"); + return bwmon->irq; + } + + ret =3D devm_pm_opp_of_add_table(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to add OPP table\n"); + + bwmon->max_bw_kbps =3D UINT_MAX; + opp =3D dev_pm_opp_find_bw_floor(dev, &bwmon->max_bw_kbps, 0); + if (IS_ERR(opp)) + return dev_err_probe(dev, ret, "failed to find max peak bandwidth\n"); + + bwmon->min_bw_kbps =3D 0; + opp =3D dev_pm_opp_find_bw_ceil(dev, &bwmon->min_bw_kbps, 0); + if (IS_ERR(opp)) + return dev_err_probe(dev, ret, "failed to find min peak bandwidth\n"); + + bwmon->sample_ms =3D data->sample_ms; + bwmon->default_lowbw_kbps =3D data->default_lowbw_kbps; + bwmon->dev =3D dev; + + bwmon_disable(bwmon); + ret =3D devm_request_threaded_irq(dev, bwmon->irq, bwmon_intr, + bwmon_intr_thread, + IRQF_ONESHOT, dev_name(dev), bwmon); + if (ret) + return dev_err_probe(dev, ret, "failed to request IRQ\n"); + + platform_set_drvdata(pdev, bwmon); + bwmon_start(bwmon, data); + + return 0; +} + +static int bwmon_remove(struct platform_device *pdev) +{ + struct icc_bwmon *bwmon =3D platform_get_drvdata(pdev); + + bwmon_disable(bwmon); + + return 0; +} + +/* BWMON v4 */ +static const struct icc_bwmon_data sdm845_bwmon_data =3D { + .sample_ms =3D 4, + .default_highbw_kbps =3D 4800 * 1024, /* 4.8 GBps */ + .default_medbw_kbps =3D 512 * 1024, /* 512 MBps */ + .default_lowbw_kbps =3D 0, + .zone1_thres_count =3D 16, + .zone3_thres_count =3D 1, +}; + +static const struct of_device_id bwmon_of_match[] =3D { + { .compatible =3D "qcom,sdm845-cpu-bwmon", .data =3D &sdm845_bwmon_data }, + {} +}; +MODULE_DEVICE_TABLE(of, bwmon_of_match); + +static struct platform_driver bwmon_driver =3D { + .probe =3D bwmon_probe, + .remove =3D bwmon_remove, + .driver =3D { + .name =3D "qcom-bwmon", + .of_match_table =3D bwmon_of_match, + }, +}; +module_platform_driver(bwmon_driver); + +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_DESCRIPTION("QCOM BWMON driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sun Apr 26 10:55:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 326A5C433EF for ; Wed, 29 Jun 2022 07:53:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232633AbiF2Hxg (ORCPT ); Wed, 29 Jun 2022 03:53:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232623AbiF2HxM (ORCPT ); Wed, 29 Jun 2022 03:53:12 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCE503B3FA for ; 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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id t2-20020a056402020200b00437db6acaeesm432173edv.95.2022.06.29.00.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 00:52:58 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/4] arm64: defconfig: enable Qualcomm Bandwidth Monitor Date: Wed, 29 Jun 2022 09:52:49 +0200 Message-Id: <20220629075250.17610-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> References: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the Qualcomm Bandwidth Monitor to allow scaling interconnects depending on bandwidth usage between CPU and memory. This is used already on Qualcomm SDM845 SoC. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6906b83f5e45..6edbcfd3f4ca 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1096,6 +1096,7 @@ CONFIG_QCOM_SOCINFO=3Dm CONFIG_QCOM_STATS=3Dm CONFIG_QCOM_WCNSS_CTRL=3Dm CONFIG_QCOM_APR=3Dm +CONFIG_QCOM_ICC_BWMON=3Dm CONFIG_ARCH_R8A77995=3Dy CONFIG_ARCH_R8A77990=3Dy CONFIG_ARCH_R8A77950=3Dy --=20 2.34.1 From nobody Sun Apr 26 10:55:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E58C6C433EF for ; Wed, 29 Jun 2022 07:53:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232760AbiF2Hxk (ORCPT ); Wed, 29 Jun 2022 03:53:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232675AbiF2HxP (ORCPT ); Wed, 29 Jun 2022 03:53:15 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D9843B554 for ; Wed, 29 Jun 2022 00:53:02 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id eq6so20968845edb.6 for ; Wed, 29 Jun 2022 00:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wfc98UIdtcTx3Uk4wA7IydSC5XqKZoBwf1qoiSGq7iA=; b=I2OK1McGbJoBW21ZZeM4sydqnxk1iFbRCGkI6B363FKEW1FIlXSshq4qaP2D7pvPDw 1G18YVReHPvzbZSLXEW2RH9dg6IdzjUC+1u3f1/hNRJNNlVuThDvrxvjbwFvZXi2sVD5 peCT3dZD6c2lI3aGEc9U8744hIe+u+Vb/U0Q4o7s0CyLRJHQtJmrHf+Av5OaBHIoE/QX VqM6LPRtHlz78oms7iX3isNg0ZgbqizAuUeu6KeEvwOWSuiEeSQErdqtSi1vgplh6Z0s 1D79/zo52w4GN9eMnr/HhGbWv8oFi7VWLDGvXtmLySCgKR2M2RmmJUdYVOgLc6k8prjR QZYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wfc98UIdtcTx3Uk4wA7IydSC5XqKZoBwf1qoiSGq7iA=; b=noQH4+aCDRvnDfdgKJqoIfG9vzP+VtgFYp4Zj0Jq/HnscE+bDmTbtDRCkBc1I3nKq5 8ik27GiuDzEvy1gPs1e7Fa1cnQ8DcVydustRqvybqHBvB7cvHgVwG8yjLxDvaCD5XIbv 0klCSg4vcGxlH92k4bPdU0+KPJuKZZDbnulp3ncCsgIK5T7rVNByU6FvNm6Wzw/Ca3rD pvZuCiePBUHSwCVS0UIAcwXtuvVLNuBW/ThgS1cNbeeUmHWDUdgzo5sAliLfi5QwCW5A JzSU+FVCMzg5EYKNQMMxdhC/UQAg/erdBxd+MrVh13mhDpfJcke/9vHGimRIcyHurbyw eVLw== X-Gm-Message-State: AJIora8vU/dUl9aqciB/lgs3tJeruLdGILtza3sIu5JXATukfqucTlsP ja2qIRE2ul3f3KytIhHE4nA5eA== X-Google-Smtp-Source: AGRyM1um2rliocS+nP8zYQiLFTaGyhO3zUYztQsruEO8RAF5jxnR5TWfwm/XUIood6h0BQlrMa5vhg== X-Received: by 2002:a05:6402:43c7:b0:435:8a92:e8d0 with SMTP id p7-20020a05640243c700b004358a92e8d0mr2517359edc.174.1656489181164; Wed, 29 Jun 2022 00:53:01 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id t2-20020a056402020200b00437db6acaeesm432173edv.95.2022.06.29.00.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 00:53:00 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thara Gopinath Subject: [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON Date: Wed, 29 Jun 2022 09:52:50 +0200 Message-Id: <20220629075250.17610-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> References: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device node for CPU-memory BWMON device (bandwidth monitoring) on SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Co-developed-by: Thara Gopinath Signed-off-by: Thara Gopinath Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 83e8b63f0910..e0f088996390 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2026,6 +2026,44 @@ llcc: system-cache-controller@1100000 { interrupts =3D ; }; =20 + pmu@1436400 { + compatible =3D "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon"; + reg =3D <0 0x01436400 0 0x600>; + interrupts =3D ; + interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LL= CC 3>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* + * The interconnect paths bandwidths taken from + * cpu4_opp_table bandwidth. + * They also match different tables from + * msm-4.9 downstream kernel: + * - the OSM L3 from bandwidth table of + * qcom,cpu4-l3lat-mon (qcom,core-dev-table); + * bus width: 16 bytes; + */ + opp-0 { + opp-peak-kBps =3D <4800000>; + }; + opp-1 { + opp-peak-kBps =3D <9216000>; + }; + opp-2 { + opp-peak-kBps =3D <15052800>; + }; + opp-3 { + opp-peak-kBps =3D <20889600>; + }; + opp-4 { + opp-peak-kBps =3D <25497600>; + }; + }; + }; + pcie0: pci@1c00000 { compatible =3D "qcom,pcie-sdm845"; reg =3D <0 0x01c00000 0 0x2000>, --=20 2.34.1