From nobody Mon Apr 20 05:57:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FB89C43334 for ; Wed, 29 Jun 2022 04:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231433AbiF2EMB (ORCPT ); Wed, 29 Jun 2022 00:12:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229967AbiF2EL4 (ORCPT ); Wed, 29 Jun 2022 00:11:56 -0400 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10CD4326D2 for ; Tue, 28 Jun 2022 21:11:56 -0700 (PDT) Received: by mail-oi1-x22e.google.com with SMTP id u9so19964574oiv.12 for ; Tue, 28 Jun 2022 21:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sFMtqpdghv9Iu/i+C/54b67+Nd1USmA2BqKquNUos/A=; b=zVhR4cZ2qzvF9FIzyUP/GuzHubIJQ7QeyuLeUP1Zf5kKzxXPcWKoi4cIjoKiP+TVYa iGgP0byytoY0nGckQzizJgGVENcSzf5r06pW26FurNp5Jn3FSwFNWQhx20yZycmXgaGk Oj7666qelQ2Jd9lUsRNvIUo6z8laBteO2Y49U9GjQ9MIWf0TNWmYHq/HUcWmqJKq0E6k P4zneA2uh8f2lWhOMGy55JCPMcGjbLHDXyhhY/hGql0UFdDDSJx+w2RF39MhGoS9TeTt WPZ29Jo1c4q6O/cEQ/ky/AWAb8+LVTWKGpSX4hAtZEQuqhNKuDO8JsLE2GM3/RuiMJy2 s7lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sFMtqpdghv9Iu/i+C/54b67+Nd1USmA2BqKquNUos/A=; b=eyC1+ZnyFHlSEJL+3xtTITrdeFPWMQXyeBL+jXbfrz5d+6Ej+NK1QoKsQCQAzQHcyL CInVkkmYVoYTDT9Xcf6k922mMSLgHdFkJ11IuWcLwS+h3tzMg/r4QSWmnlXf7Rw4nbs6 ecUJSuJztk5DABdehxertwWxpnX84CLkbFN5osq6EcmFsvIuiV+d2jZhIoQzNRJAHjRR NjIKQWzFKuUW0HyZW73PGgLtyYNzpnRazC6AK+mdWDtMtQlfPCElNA8VV37YH/1/4kFl mSvVxGZSkPRiXiikf0hpx2xgMl8p7wtdSg73hjdh7Cz1pf4Abejs9t2wJJE3IN/ds6W2 4QWw== X-Gm-Message-State: AJIora88LfA2m3Xf4UaOcDg6FGe4C/RrdHtqPbe8XOBEHlcuemt2R1X8 9SRivmsSQAPJKPpjSaewmB907g== X-Google-Smtp-Source: AGRyM1t3HsfXDwokoCnoAMkM+w1cPhXi4boARhaCeUHkfO60kkWveHFeDkZIumpA6128HSLpKnsr/w== X-Received: by 2002:a05:6808:1797:b0:335:1e4e:41bf with SMTP id bg23-20020a056808179700b003351e4e41bfmr851021oib.224.1656475915455; Tue, 28 Jun 2022 21:11:55 -0700 (PDT) Received: from ripper.. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p12-20020a9d4e0c000000b00616ec82b29bsm1578692otf.35.2022.06.28.21.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 21:11:54 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Jassi Brar , Johan Hovold , Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Johan Hovold Subject: [PATCH v3 1/5] dt-bindings: arm: qcom: Document additional sc8280xp devices Date: Tue, 28 Jun 2022 21:14:34 -0700 Message-Id: <20220629041438.1352536-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220629041438.1352536-1-bjorn.andersson@linaro.org> References: <20220629041438.1352536-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the CRD (Compute Reference Design?) and the Lenovo Thinkpad X13s to the valid device compatibles found on the sc8280xp platform. Signed-off-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski Reviewed-by: Johan Hovold --- Changes since v2: - None Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 5c06d1bfc046..6ec7521be19d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -238,6 +238,8 @@ properties: =20 - items: - enum: + - lenovo,thinkpad-x13s + - qcom,sc8280xp-crd - qcom,sc8280xp-qrd - const: qcom,sc8280xp =20 --=20 2.35.1 From nobody Mon Apr 20 05:57:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF323C433EF for ; Wed, 29 Jun 2022 04:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229729AbiF2EMN (ORCPT ); Wed, 29 Jun 2022 00:12:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231417AbiF2EL7 (ORCPT ); Wed, 29 Jun 2022 00:11:59 -0400 Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A2153668B for ; Tue, 28 Jun 2022 21:11:57 -0700 (PDT) Received: by mail-ot1-x336.google.com with SMTP id m24-20020a0568301e7800b00616b5c114d4so9448011otr.11 for ; Tue, 28 Jun 2022 21:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9XwhN6hWHSS8Xo3qCEB3TdmpDY/iGy7IMz5cHkd8nAs=; b=LuowUxMaf7ZxYLIzl28Xcn061Su9qODhPNu4CAu0xhJH54vrNxhsZOOe26dBmkcckt UzAR1lQR3ObBX1BYpDOp/XngcpdzaC2UnaASLzCfOYSJgGf7UlArWBhIEypsry1j6aWU V8cnWwOaeROIVDUh/PnEJGbd6mlZxEnHjPMCElk4ZvEYn1FyGTG3jxQXk2lnQXovfeAz G+x36R4R6BEs+AnJGzK2V+LkrsWiS0Vnl6LvPWd2psaQOEvdOTczQPoVdnGakbdyHSqm 3PiV07MURgZSbeLQzAYPvAfYiA39yeTYjdlCt3vdWCXK/Qzx1oylZQAzbFCIxpz3dYtz 5XxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9XwhN6hWHSS8Xo3qCEB3TdmpDY/iGy7IMz5cHkd8nAs=; b=lKiC/Z4Zhp1To8MUHxTs27bc1IzHN3ZLiy4v8G+arq8wJntHXzxY6c8Jr426Q2CNCU kONj7ux1p/TbVNd1sQOwgle4z/wJmX3Oa8UYAy3BRP6ayXeoIHveP0AafZVjk1uLHc3o 1oFePReKTnBLd1VQqgbdv59/5YRTGV/Z73E+v8cCx2i6/vjIJD7toPu+qoMSfw2y7t7p QZgpUmH5vczKWxj9jpL4yjYHa9o34/uJCnJK4CyYcRPNQ2nBKfVa721+2qK2irg8p+jv JAwZO6d0LtANG+FNCGmRG9j19roEbzbd4BijViYAOYr6LOl3Ei7qIMC5rlsSs5NQbidm xqvg== X-Gm-Message-State: AJIora/Gt/fag+ud2ItX6h+fcTLSEpu+ITp/71bbf+htJ/5XKS1bk43k kwnoh1rjvn54nLkQj1OLhYjL4Q== X-Google-Smtp-Source: AGRyM1vpOGqtNCrvhjYcOhVDfmJ0I5KWq4+tcQHHhrV/n6DUEwzjx0mwajHGJj55URJjQ+NkFWT92Q== X-Received: by 2002:a9d:471a:0:b0:616:ed33:e41 with SMTP id a26-20020a9d471a000000b00616ed330e41mr677682otf.192.1656475916851; Tue, 28 Jun 2022 21:11:56 -0700 (PDT) Received: from ripper.. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p12-20020a9d4e0c000000b00616ec82b29bsm1578692otf.35.2022.06.28.21.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 21:11:56 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Jassi Brar , Johan Hovold , Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 2/5] dt-bindings: mailbox: qcom-ipcc: Add NSP1 client Date: Tue, 28 Jun 2022 21:14:35 -0700 Message-Id: <20220629041438.1352536-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220629041438.1352536-1-bjorn.andersson@linaro.org> References: <20220629041438.1352536-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a client for the NSP1 found in some recent Qualcomm platforms. Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson --- Changes since v2: - None include/dt-bindings/mailbox/qcom-ipcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/= mailbox/qcom-ipcc.h index 9296d0bb5f34..fbfa3febc66d 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -30,6 +30,7 @@ #define IPCC_CLIENT_PCIE1 14 #define IPCC_CLIENT_PCIE2 15 #define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_NSP1 18 #define IPCC_CLIENT_TME 23 #define IPCC_CLIENT_WPSS 24 =20 --=20 2.35.1 From nobody Mon Apr 20 05:57:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9874DC433EF for ; Wed, 29 Jun 2022 04:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231463AbiF2EMR (ORCPT ); Wed, 29 Jun 2022 00:12:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229967AbiF2EMD (ORCPT ); Wed, 29 Jun 2022 00:12:03 -0400 Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34628366A3 for ; Tue, 28 Jun 2022 21:11:59 -0700 (PDT) Received: by mail-oi1-x230.google.com with SMTP id e131so19969406oif.13 for ; Tue, 28 Jun 2022 21:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B4FQ+NLl/V38ZrufgJj15J7QoYlS7bsUr8cTBYk1thA=; b=RH278QGC/uPo6a5g1QFFXZTgzY6SQbWBl9VtO9V7YL16MFFkdIowMMA1MkDHCT2tBI PXCYmw2nsOZ7Bzhjom8+/sGDtjcJzokS7vi/sTkMJ+8XSQpbi5AaTxPa+qHG2Y8k6vm2 p3nGbvM7Q7oT0UVVDGiMSOJCp2L84mFvpp70UuENpLEyVNmjI2HwbVwPuKzPRVMWLgKn UM1OUcbPSVgru4Yvqouh/KRWDEGE49Ikk+vPLInmdtnDij5dcVcfHn4DBJA21FOtVNnP v51xnTpsccxcKqTL2bO8L5kftKojOtxpKKH//u5mAPGRE73U1TaQDiownRcNh8zhxP2F nVbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B4FQ+NLl/V38ZrufgJj15J7QoYlS7bsUr8cTBYk1thA=; b=J2AAyXOxpgP0dmhA6lNWsBOFuq7kyYag6pl8AtzxzzGZ8/sR3wcGpo3J4yb/QDZgC5 Z0fCxpUxJX1qFghBxPWSY9GAROFb8CZg5nLrPu/+TEiTo0xP3BdY00SZzMKzPJqgIhEt 2+kJGMdS+6FXE7CAcWSQBydScy8et0fEgVv2Bu0X0Kfpk6vEtB1yL92pF0TH3ELWGxwt 0Q0aSUe0ys4VBUyrWDdDKkR7TXr2u9lpokeixs+bJu0GRXymm0/PsBNBxI325jA8iBje ZLA+dXBzGbMVgmJUP66l5nwuORCoo7d6uB4dD7Gufyi0pqjvCa0ANkCS7HLOLc8KZaT8 t3MQ== X-Gm-Message-State: AJIora8f6/i10+bfHJDL3dbbMK+zWkNjOwbEgYNokuwsHkrgjq4ivBLz syCTyIvrgEtv76uBv3Jgd0D9jg== X-Google-Smtp-Source: AGRyM1tTx4dramu98NxVNMJsZiLwKL7hdeAbpdoKQgAamXwJ2ZzuIOgr3XzBVnCVkJVG/Bg4xJwvZg== X-Received: by 2002:a54:460a:0:b0:335:34bb:3c4e with SMTP id p10-20020a54460a000000b0033534bb3c4emr855176oip.147.1656475918219; Tue, 28 Jun 2022 21:11:58 -0700 (PDT) Received: from ripper.. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p12-20020a9d4e0c000000b00616ec82b29bsm1578692otf.35.2022.06.28.21.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 21:11:57 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Jassi Brar , Johan Hovold , Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v3 3/5] arm64: dts: qcom: add SC8280XP platform Date: Tue, 28 Jun 2022 21:14:36 -0700 Message-Id: <20220629041438.1352536-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220629041438.1352536-1-bjorn.andersson@linaro.org> References: <20220629041438.1352536-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce initial support for the Qualcomm SC8280XP platform, aka 8cx Gen 3. This initial contribution supports SMP, CPUfreq, CPU cluster idling, GCC, TLMM, SMMU, RPMh regulators, power-domains and clocks, interconnects, some QUPs, UFS, remoteprocs, USB, watchdog, LLCC and tsens. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Changes since v2: - Fixed include sort order - Dropped a stray newline in &CPU0 - Renamed reserved-memory regions - Dropped clock-frequency of the timers node - Reduced #address-cells and #size-cells to 1 in timer node arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2142 ++++++++++++++++++++++++ 1 file changed, 2142 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi new file mode 100644 index 000000000000..c9d608ac87fa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -0,0 +1,2142 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32764>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + }; + opp-691200000 { + opp-hz =3D /bits/ 64 <691200000>; + }; + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz =3D /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + }; + opp-1996800000 { + opp-hz =3D /bits/ 64 <1996800000>; + }; + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + }; + opp-2227200000 { + opp-hz =3D /bits/ 64 <2227200000>; + }; + opp-2342400000 { + opp-hz =3D /bits/ 64 <2342400000>; + }; + opp-2438400000 { + opp-hz =3D /bits/ 64 <2438400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz =3D /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz =3D /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz =3D /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz =3D /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz =3D /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz =3D /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz =3D /bits/ 64 <2284800000>; + }; + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + }; + opp-2496000000 { + opp-hz =3D /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + }; + opp-2688000000 { + opp-hz =3D /bits/ 64 <2688000000>; + }; + opp-2803200000 { + opp-hz =3D /bits/ 64 <2803200000>; + }; + opp-2899200000 { + opp-hz =3D /bits/ 64 <2899200000>; + }; + opp-2995200000 { + opp-hz =3D /bits/ 64 <2995200000>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_0>; + power-domains =3D <&CPU_PD0>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_100>; + power-domains =3D <&CPU_PD1>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_100: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_200>; + power-domains =3D <&CPU_PD2>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_200: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_300>; + power-domains =3D <&CPU_PD3>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_300: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_400>; + power-domains =3D <&CPU_PD4>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_400: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_500>; + power-domains =3D <&CPU_PD5>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_500: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_600>; + power-domains =3D <&CPU_PD6>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_600: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_700>; + power-domains =3D <&CPU_PD7>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_700: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + + core4 { + cpu =3D <&CPU4>; + }; + + core5 { + cpu =3D <&CPU5>; + }; + + core6 { + cpu =3D <&CPU6>; + }; + + core7 { + cpu =3D <&CPU7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <355>; + exit-latency-us =3D <909>; + min-residency-us =3D <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <241>; + exit-latency-us =3D <1461>; + min-residency-us =3D <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + idle-state-name =3D "cluster-power-collapse"; + arm,psci-suspend-param =3D <0x4100c344>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9987>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sc8280xp", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible =3D "qcom,sc8280xp-aggre1-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible =3D "qcom,sc8280xp-aggre2-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,sc8280xp-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible =3D "qcom,sc8280xp-config-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible =3D "qcom,sc8280xp-dc-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible =3D "qcom,sc8280xp-gem-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_noc: interconnect-lpass-ag-noc { + compatible =3D "qcom,sc8280xp-lpass-ag-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible =3D "qcom,sc8280xp-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible =3D "qcom,sc8280xp-mmss-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible =3D "qcom,sc8280xp-nspa-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible =3D "qcom,sc8280xp-nspb-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible =3D "qcom,sc8280xp-system-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&CLUSTER_SLEEP_0>; + }; + }; + + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + reserved-region@80000000 { + reg =3D <0 0x80000000 0 0x860000>; + no-map; + }; + + cmd_db: cmd-db-region@80860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0 0x80860000 0 0x20000>; + no-map; + }; + + reserved-region@80880000 { + reg =3D <0 0x80880000 0 0x80000>; + no-map; + }; + + smem_mem: smem-region@80900000 { + compatible =3D "qcom,smem"; + reg =3D <0 0x80900000 0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + reserved-region@80b00000 { + reg =3D <0 0x80b00000 0 0x100000>; + no-map; + }; + + reserved-region@83b00000 { + reg =3D <0 0x83b00000 0 0x1700000>; + no-map; + }; + + reserved-region@85b00000 { + reg =3D <0 0x85b00000 0 0xc00000>; + no-map; + }; + + pil_adsp_mem: adsp-region@86c00000 { + reg =3D <0 0x86c00000 0 0x2000000>; + no-map; + }; + + pil_nsp0_mem: cdsp0-region@8a100000 { + reg =3D <0 0x8a100000 0 0x1e00000>; + no-map; + }; + + pil_nsp1_mem: cdsp1-region@8c600000 { + reg =3D <0 0x8c600000 0 0x1e00000>; + no-map; + }; + + reserved-region@aeb00000 { + reg =3D <0 0xaeb00000 0 0x16600000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-nsp0 { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_nsp0_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_nsp0_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-nsp1 { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <617>, <616>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <12>; + + smp2p_nsp1_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_nsp1_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,gcc-sc8280xp"; + reg =3D <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_0_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_1_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + }; + + ipcc: mailbox@408000 { + compatible =3D "qcom,sc8280xp-ipcc", "qcom,ipcc"; + reg =3D <0 0x00408000 0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + qup2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x008c0000 0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0xa3 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + qup2_uart17: serial@884000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00884000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + qup2_i2c5: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + }; + + qup0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x009c0000 0 0x6000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0x563 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + qup0_i2c4: i2c@990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00990000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + }; + + qup1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x00ac0000 0 0x6000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0x83 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0 0x01d84000 0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0xe0 0x0>; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,sc8280xp-qmp-ufs-phy"; + reg =3D <0 0x01d87000 0 0xe10>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clock-names =3D "ref", + "ref_aux"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + status =3D "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg =3D <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + }; + }; + + ufs_card_hc: ufs@1da4000 { + compatible =3D "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0 0x01da4000 0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_card_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_CARD_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc UFS_CARD_GDSC>; + + iommus =3D <&apps_smmu 0x4a0 0x0>; + + clocks =3D <&gcc GCC_UFS_CARD_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_UFS_CARD_AHB_CLK>, + <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status =3D "disabled"; + }; + + ufs_card_phy: phy@1da7000 { + compatible =3D "qcom,sc8280xp-qmp-ufs-phy"; + reg =3D <0 0x01da7000 0 0xe10>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clock-names =3D "ref", + "ref_aux"; + clocks =3D <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; + + resets =3D <&ufs_card_hc 0>; + reset-names =3D "ufsphy"; + + status =3D "disabled"; + + ufs_card_phy_lanes: phy@1da7400 { + reg =3D <0 0x01da7400 0 0x108>, + <0 0x01da7600 0 0x1e0>, + <0 0x01da7c00 0 0x1dc>, + <0 0x01da7800 0 0x108>, + <0 0x01da7a00 0 0x1e0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + usb_0_hsphy: phy@88e5000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e5000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy0: phy@88e7000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e7000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy1: phy@88e8000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e8000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS1_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy2: phy@88e9000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e9000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS2_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy3: phy@88ea000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088ea000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS3_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_qmpphy0: phy-wrapper@88ef000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088ef000 0 0x1c8>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + status =3D "disabled"; + + usb_2_ssphy0: phy@88efe00 { + reg =3D <0 0x088efe00 0 0x160>, + <0 0x088f0000 0 0x1ec>, + <0 0x088ef200 0 0x1f0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb2_phy0_pipe_clk"; + }; + }; + + usb_2_qmpphy1: phy-wrapper@88f1000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088f1000 0 0x1c8>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + status =3D "disabled"; + + usb_2_ssphy1: phy@88f1e00 { + reg =3D <0 0x088f1e00 0 0x160>, + <0 0x088f2000 0 0x1ec>, + <0 0x088f1200 0 0x1f0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb2_phy1_pipe_clk"; + }; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,sc8280xp-adsp-pas"; + reg =3D <0 0x03000000 0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names =3D "lcx", "lmx"; + + memory-region =3D <&pil_adsp_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + }; + }; + + usb_0_qmpphy: phy-wrapper@88ec000 { + compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; + reg =3D <0 0x088ec000 0 0x1e4>, + <0 0x088eb000 0 0x40>, + <0 0x088ed000 0 0x1c8>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_EUD_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + status =3D "disabled"; + + usb_0_ssphy: usb3-phy@88eb400 { + reg =3D <0 0x088eb400 0 0x100>, + <0 0x088eb600 0 0x3ec>, + <0 0x088ec400 0 0x1f0>, + <0 0x088eba00 0 0x100>, + <0 0x088ebc00 0 0x3ec>, + <0 0x088ec700 0 0x64>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb0_phy_pipe_clk_src"; + }; + + usb_0_dpphy: dp-phy@88ed200 { + reg =3D <0 0x088ed200 0 0x200>, + <0 0x088ed400 0 0x200>, + <0 0x088eda00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; + + usb_1_hsphy: phy@8902000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x08902000 0 0x400>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status =3D "disabled"; + }; + + usb_1_qmpphy: phy-wrapper@8904000 { + compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; + reg =3D <0 0x08904000 0 0x1e4>, + <0 0x08903000 0 0x40>, + <0 0x08905000 0 0x1c8>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_SEC_GDSC>; + + status =3D "disabled"; + + usb_1_ssphy: usb3-phy@8903400 { + reg =3D <0 0x08903400 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904400 0 0x1f0>, + <0 0x08903a00 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904200 0 0x18>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb1_phy_pipe_clk_src"; + }; + + usb_1_dpphy: dp-phy@88ed200 { + reg =3D <0 0x08904200 0 0x200>, + <0 0x08904400 0 0x200>, + <0 0x08904a00 0 0x200>, + <0 0x08904600 0 0x200>, + <0 0x08904800 0 0x200>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; + + system-cache-controller@9200000 { + compatible =3D "qcom,sc8280xp-llcc"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; + reg-names =3D "llcc_base", "llcc_broadcast_base"; + interrupts =3D ; + }; + + usb_0: usb@a6f8800 { + compatible =3D "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a6f8800 0 0x400>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names =3D "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + status =3D "disabled"; + + usb_0_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a600000 0 0xcd00>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x820 0x0>; + phys =3D <&usb_0_hsphy>, <&usb_0_ssphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; + + usb_1: usb@a8f8800 { + compatible =3D "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a8f8800 0 0x400>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names =3D "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks =3D <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains =3D <&gcc USB30_SEC_GDSC>; + + resets =3D <&gcc GCC_USB30_SEC_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + status =3D "disabled"; + + usb_1_dwc3: usb@a800000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a800000 0 0xcd00>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x860 0x0>; + phys =3D <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sc8280xp-pdc", "qcom,pdc"; + reg =3D <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges =3D <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 3>, + <69 86 1>, + <70 520 54>, + <124 609 28>, + <159 638 1>, + <160 720 8>, + <168 801 1>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 1>, + <216 646 5>, + <221 390 5>, + <226 700 3>, + <229 240 3>, + <232 269 1>, + <233 377 1>, + <234 372 1>, + <235 138 1>, + <236 857 1>, + <237 860 1>, + <238 137 1>, + <239 668 1>, + <240 366 1>, + <241 949 1>, + <242 815 5>, + <247 769 1>, + <248 768 1>, + <249 663 1>, + <250 799 2>, + <252 798 1>, + <253 765 1>, + <254 763 1>, + <255 454 1>, + <258 139 1>, + <259 786 2>, + <261 370 2>, + <263 158 2>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible =3D "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors =3D <14>; + interrupts-extended =3D <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible =3D "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts-extended =3D <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible =3D "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0 0x0c300000 0 0x400>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + spmi_bus: spmi@c440000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,sc8280xp-tlmm"; + reg =3D <0 0x0f100000 0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 230>; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sc8280xp-smmu-500", "arm,mmu-500"; + reg =3D <0 0x15000000 0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts =3D ; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0 0x20000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic-its@17a40000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0 0x17a40000 0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17c10000 { + compatible =3D "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; + reg =3D <0 0x17c10000 0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x17c23000 0x1000>; + status =3D "disabled"; + }; + + frame@17c25000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x17c25000 0x1000>; + status =3D "disabled"; + }; + + frame@17c27000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x17c26000 0x1000>; + status =3D "disabled"; + }; + + frame@17c29000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x17c29000 0x1000>; + status =3D "disabled"; + }; + + frame@17c2b000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x17c2b000 0x1000>; + status =3D "disabled"; + }; + + frame@17c2d000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x17c2d000 0x1000>; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sc8280xp-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sc8280xp-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible =3D "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + }; + + remoteproc_nsp0: remoteproc@1b300000 { + compatible =3D "qcom,sc8280xp-nsp0-pas"; + reg =3D <0 0x1b300000 0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_NSP>; + power-domain-names =3D "nsp"; + + memory-region =3D <&pil_nsp0_mem>; + + qcom,smem-states =3D <&smp2p_nsp0_out 0>; + qcom,smem-state-names =3D "stop"; + + interconnects =3D <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "nsp0"; + qcom,remote-pid =3D <5>; + + fastrpc { + compatible =3D "qcom,fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x3181 0x0420>; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x3182 0x0420>; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x3183 0x0420>; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x3184 0x0420>; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x3185 0x0420>; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x3186 0x0420>; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu 0x3187 0x0420>; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu 0x3188 0x0420>; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@10 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <10>; + iommus =3D <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@11 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <11>; + iommus =3D <&apps_smmu 0x318c 0x0420>; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu 0x318d 0x0420>; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu 0x318e 0x0420>; + }; + + compute-cb@14 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <14>; + iommus =3D <&apps_smmu 0x318f 0x0420>; + }; + }; + }; + }; + + remoteproc_nsp1: remoteproc@21300000 { + compatible =3D "qcom,sc8280xp-nsp1-pas"; + reg =3D <0 0x21300000 0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_NSP>; + power-domain-names =3D "nsp"; + + memory-region =3D <&pil_nsp1_mem>; + + qcom,smem-states =3D <&smp2p_nsp1_out 0>; + qcom,smem-state-names =3D "stop"; + + interconnects =3D <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0= >; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "nsp1"; + qcom,remote-pid =3D <12>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + mem-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 15>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; +}; --=20 2.35.1 From nobody Mon Apr 20 05:57:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7B92C433EF for ; Wed, 29 Jun 2022 04:12:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231537AbiF2EMV (ORCPT ); Wed, 29 Jun 2022 00:12:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231519AbiF2EME (ORCPT ); Wed, 29 Jun 2022 00:12:04 -0400 Received: from mail-oa1-x35.google.com (mail-oa1-x35.google.com [IPv6:2001:4860:4864:20::35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37DE7369D2 for ; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p12-20020a9d4e0c000000b00616ec82b29bsm1578692otf.35.2022.06.28.21.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 21:11:58 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Jassi Brar , Johan Hovold , Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v3 4/5] arm64: dts: qcom: sc8280xp: Add reference device Date: Tue, 28 Jun 2022 21:14:37 -0700 Message-Id: <20220629041438.1352536-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220629041438.1352536-1-bjorn.andersson@linaro.org> References: <20220629041438.1352536-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add basic support for the SC8280XP reference device, which allows it to boot to a shell (using EFIFB) with functional storage (UFS), USB, keyboard, touchpad, touchscreen, backlight and remoteprocs. The PMICs are, per socinfo, reused from other platforms. But given that the address of the PMICs doesn't match other cases and that it's desirable to label things according to the schematics a new dtsi file is created to represent the reference combination of PMICs. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold --- Changes since v2: - Fixed sort order of &xo_board_clk - Dropped unused includes - Moved regulator suffix to prefix for edp-bl and misc_3p3 - Dropped empty reserved-memory node arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 427 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 109 +++++ 3 files changed, 537 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 2f8aec2cc6db..ceeae094a59f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-villager-r0= .dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts new file mode 100644 index 000000000000..45058ad0a1c8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/ { + model =3D "Qualcomm SC8280XP CRD"; + compatible =3D "qcom,sc8280xp-crd", "qcom,sc8280xp"; + + aliases { + serial0 =3D &qup2_uart17; + }; + + backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pmc8280c_lpg 3 1000000>; + enable-gpios =3D <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply =3D <&vreg_edp_bl>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_bl_en>, <&edp_bl_pwm>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_EDP_BL"; + regulator-min-microvolt =3D <3600000>; + regulator-max-microvolt =3D <3600000>; + + gpio =3D <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_MISC_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + pmc8280-1-rpmh-regulators { + compatible =3D "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-l3-l5-supply =3D <&vreg_s11b>; + + vreg_s11b: smps11 { + regulator-name =3D "vreg_s11b"; + regulator-min-microvolt =3D <1272000>; + regulator-max-microvolt =3D <1272000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l6b: ldo6 { + regulator-name =3D "vreg_l6b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-boot-on; + }; + }; + + pmc8280c-rpmh-regulators { + compatible =3D "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l13c: ldo13 { + regulator-name =3D "vreg_l13c"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + + pmc8280-2-rpmh-regulators { + compatible =3D "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-l4-supply =3D <&vreg_s11b>; + + vreg_l3d: ldo3 { + regulator-name =3D "vreg_l3d"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l4d: ldo4 { + regulator-name =3D "vreg_l4d"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l6d: ldo6 { + regulator-name =3D "vreg_l6d"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7d: ldo7 { + regulator-name =3D "vreg_l7d"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l9d: ldo9 { + regulator-name =3D "vreg_l9d"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; +}; + +&pmc8280c_lpg { + status =3D "okay"; +}; + +&pmk8280_pon_pwrkey { + status =3D "okay"; +}; + +&qup0 { + status =3D "okay"; +}; + +&qup0_i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup0_i2c4_default>, <&ts0_default>; + + status =3D "okay"; + + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + }; +}; + +&qup1 { + status =3D "okay"; +}; + +&qup2 { + status =3D "okay"; +}; + +&qup2_i2c5 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + + status =3D "okay"; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + }; + + keyboard@68 { + compatible =3D "hid-over-i2c"; + reg =3D <0x68>; + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + }; +}; + +&qup2_uart17 { + compatible =3D "qcom,geni-debug-uart"; + + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sc8280xp/qcadsp8280.mbn"; + + status =3D "okay"; +}; + +&remoteproc_nsp0 { + firmware-name =3D "qcom/sc8280xp/qccdsp8280.mbn"; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l7c>; + vcc-max-microamp =3D <800000>; + vccq-supply =3D <&vreg_l3d>; + vccq-max-microamp =3D <900000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l6b>; + vdda-pll-supply =3D <&vreg_l3b>; + + status =3D "okay"; +}; + +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "host"; +}; + +&usb_0_hsphy { + vdda-pll-supply =3D <&vreg_l9d>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l7d>; + + status =3D "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply =3D <&vreg_l9d>; + vdda-pll-supply =3D <&vreg_l4d>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l4b>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l13c>; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l4b>; + vdda-pll-supply =3D <&vreg_l3b>; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; + +/* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ + +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins =3D "gpio8"; + function =3D "normal"; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins =3D "gpio9"; + function =3D "normal"; + }; + + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins =3D "gpio1"; + function =3D "normal"; + }; +}; + +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins =3D "gpio8"; + function =3D "func1"; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + + kybd_default: kybd-default-state { + disable { + pins =3D "gpio102"; + function =3D "gpio"; + output-low; + }; + + int-n { + pins =3D "gpio104"; + function =3D "gpio"; + bias-disable; + }; + + reset { + pins =3D "gpio105"; + function =3D "gpio"; + bias-disable; + }; + }; + + qup0_i2c4_default: qup0-i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + + bias-disable; + drive-strength =3D <16>; + }; + + qup2_i2c5_default: qup2-i2c5-default-state { + pins =3D "gpio81", "gpio82"; + function =3D "qup21"; + + bias-disable; + drive-strength =3D <16>; + }; + + tpad_default: tpad-default-state { + int-n { + pins =3D "gpio182"; + function =3D "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + int-n { + pins =3D "gpio175"; + function =3D "gpio"; + bias-pull-up; + }; + + reset-n { + pins =3D "gpio99"; + function =3D "gpio"; + output-high; + drive-strength =3D <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot= /dts/qcom/sc8280xp-pmics.dtsi new file mode 100644 index 000000000000..ae90b97aecb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include + +&spmi_bus { + pmk8280: pmic@0 { + compatible =3D "qcom,pmk8350", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmk8280_pon: pon@1300 { + compatible =3D "qcom,pm8998-pon"; + reg =3D <0x1300>; + + pmk8280_pon_pwrkey: pwrkey { + compatible =3D "qcom,pmk8350-pwrkey"; + interrupts =3D <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code =3D ; + status =3D "disabled"; + }; + }; + }; + + pmc8280_1: pmic@1 { + compatible =3D "qcom,pm8350", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmc8280_1_gpios: gpio@8800 { + compatible =3D "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmc8280_1_gpios 0 0 10>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmc8280c: pmic@2 { + compatible =3D "qcom,pm8350c", "qcom,spmi-pmic"; + reg =3D <0x2 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmc8280c_gpios: gpio@8800 { + compatible =3D "qcom,pm8350c-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmc8280c_gpios 0 0 9>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pmc8280c_lpg: lpg@e800 { + compatible =3D "qcom,pm8350c-pwm"; + reg =3D <0xe800>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + #pwm-cells =3D <2>; + + status =3D "disabled"; + }; + }; + + pmc8280_2: pmic@3 { + compatible =3D "qcom,pm8350", "qcom,spmi-pmic"; + reg =3D <0x3 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmc8280_2_gpios: gpio@8800 { + compatible =3D "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmc8280_2_gpios 0 0 10>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmr735a: pmic@4 { + compatible =3D "qcom,pmr735a", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmr735a_gpios: gpio@8800 { + compatible =3D "qcom,pmr735a-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmr735a_gpios 0 0 4>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.35.1 From nobody Mon Apr 20 05:57:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29B29C43334 for ; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id p12-20020a9d4e0c000000b00616ec82b29bsm1578692otf.35.2022.06.28.21.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 21:11:59 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Jassi Brar , Johan Hovold , Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v3 5/5] arm64: dts: qcom: add SA8540P and ADP Date: Tue, 28 Jun 2022 21:14:38 -0700 Message-Id: <20220629041438.1352536-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220629041438.1352536-1-bjorn.andersson@linaro.org> References: <20220629041438.1352536-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce the Qualcomm SA8540P automotive platform and the SA8295P ADP development board. The SA8540P and SC8280XP are fairly similar, so the SA8540P is built ontop of the SC8280XP dtsi to reduce duplication. As more advanced features are integrated this might be re-evaluated. This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh regulators, debug UART, PMICs, remoteprocs (NSPs crashes shortly after booting) and USB. The SA8295P ADP contains four PM8450 PMICs, which according to their revid are compatible with PM8150. They are defined within the ADP for now, to avoid creating additional .dtsi files for PM8150 with just addresses changed - and to allow using the labels from the schematics. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold --- Changes since v2: - Sorted "status" property last throughout the patch - Dropped empty reserved-memory node - Dropped multiport vbus-enable pinctrl states for now arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 406 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8540p.dtsi | 133 ++++++++ 3 files changed, 540 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8295p-adp.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8540p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ceeae094a59f..2f416b84b71c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8295p-adp.dts new file mode 100644 index 000000000000..d4baa2460e4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include + +#include "sa8540p.dtsi" + +/ { + model =3D "Qualcomm SA8295P ADP"; + compatible =3D "qcom,sa8295p-adp", "qcom,sa8540p"; + + aliases { + serial0 =3D &qup2_uart17; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&apps_rsc { + pmm8540-a-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1208000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l13a: ldo13 { + regulator-name =3D "vreg_l13a"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + + pmm8540-c-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l3c: ldo3 { + regulator-name =3D "vreg_l3c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1208000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l10c: ldo10 { + regulator-name =3D "vreg_l10c"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l17c: ldo17 { + regulator-name =3D "vreg_l17c"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + + pmm8540-g-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vreg_l3g: ldo3 { + regulator-name =3D "vreg_l3g"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7g: ldo7 { + regulator-name =3D "vreg_l7g"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l8g: ldo8 { + regulator-name =3D "vreg_l8g"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; +}; + +&qup2 { + status =3D "okay"; +}; + +&qup2_uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sa8540p/adsp.mbn"; + status =3D "okay"; +}; + +&remoteproc_nsp0 { + firmware-name =3D "qcom/sa8540p/cdsp.mbn"; + status =3D "okay"; +}; + +&remoteproc_nsp1 { + firmware-name =3D "qcom/sa8540p/cdsp1.mbn"; + status =3D "okay"; +}; + +&spmi_bus { + pm8450a: pmic@0 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450a_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8450c: pmic@4 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450c_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8450e: pmic@8 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x8 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450e_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8450g: pmic@c { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0xc SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450g_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17c>; + vcc-max-microamp =3D <800000>; + vccq-supply =3D <&vreg_l6c>; + vccq-max-microamp =3D <900000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l8g>; + vdda-pll-supply =3D <&vreg_l3g>; + + status =3D "okay"; +}; + +&ufs_card_hc { + reset-gpios =3D <&tlmm 229 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l10c>; + vcc-max-microamp =3D <800000>; + vccq-supply =3D <&vreg_l3c>; + vccq-max-microamp =3D <900000>; + + status =3D "okay"; +}; + +&ufs_card_phy { + vdda-phy-supply =3D <&vreg_l8g>; + vdda-pll-supply =3D <&vreg_l3g>; + + status =3D "okay"; +}; + +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7a>; + vdda33-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply =3D <&vreg_l3a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l1c>; + vdda18-supply =3D <&vreg_l7c>; + vdda33-supply =3D <&vreg_l2c>; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l4c>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&usb_2_hsphy0 { + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_2_hsphy1 { + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_2_hsphy2 { + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_2_hsphy3 { + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_2_qmpphy0 { + vdda-phy-supply =3D <&vreg_l3a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&usb_2_qmpphy1 { + vdda-phy-supply =3D <&vreg_l3a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; + +/* PINCTRL */ +&pm8450c_gpios { + usb2_en_state: usb2-en-state { + pins =3D "gpio9"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; + +&pm8450e_gpios { + usb3_en_state: usb3-en-state { + pins =3D "gpio5"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qc= om/sa8540p.dtsi new file mode 100644 index 000000000000..8ea2886fbab2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include "sc8280xp.dtsi" + +/delete-node/ &cpu0_opp_table; +/delete-node/ &cpu4_opp_table; + +/ { + cpu0_opp_table: cpu0-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + }; + opp-710400000 { + opp-hz =3D /bits/ 64 <710400000>; + }; + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz =3D /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + }; + opp-2131200000 { + opp-hz =3D /bits/ 64 <2131200000>; + }; + opp-2246400000 { + opp-hz =3D /bits/ 64 <2246400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz =3D /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz =3D /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz =3D /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz =3D /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz =3D /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz =3D /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz =3D /bits/ 64 <2284800000>; + }; + opp-2380800000 { + opp-hz =3D /bits/ 64 <2380800000>; + }; + opp-2496000000 { + opp-hz =3D /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + }; + }; +}; + +&rpmhpd { + compatible =3D "qcom,sa8540p-rpmhpd"; +}; --=20 2.35.1