From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA778C43334 for ; Wed, 29 Jun 2022 03:18:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230504AbiF2DSJ (ORCPT ); Tue, 28 Jun 2022 23:18:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229715AbiF2DSE (ORCPT ); Tue, 28 Jun 2022 23:18:04 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBBFA2CE24; Tue, 28 Jun 2022 20:18:00 -0700 (PDT) X-UUID: 59881e7e1c574eb195aebe626c086ffd-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:75eaf488-cd38-4e25-8fad-7a766a7923e2,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:87442a2,CLOUDID:6aabe862-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 59881e7e1c574eb195aebe626c086ffd-20220629 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1622157211; Wed, 29 Jun 2022 11:17:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 29 Jun 2022 11:17:51 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:17:50 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , "Rob Herring" , Bartosz Golaszewski , "Fabien Parent" CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "Matthias Brugger" , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 01/10] net: ethernet: mtk-star-emac: store bit_clk_div in compat structure Date: Wed, 29 Jun 2022 11:17:34 +0800 Message-ID: <20220629031743.22115-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Not all the SoC are using the same clock divider. Move the divider into a compat structure specific to the SoCs. Signed-off-by: Biao Huang Signed-off-by: Fabien Parent --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 95839fd84dab..9c54043f7866 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,10 @@ struct mtk_star_ring { unsigned int tail; }; =20 +struct mtk_star_compat { + unsigned char bit_clk_div; +}; + struct mtk_star_priv { struct net_device *ndev; =20 @@ -256,6 +261,8 @@ struct mtk_star_priv { int duplex; int pause; =20 + const struct mtk_star_compat *compat_data; + /* Protects against concurrent descriptor access. */ spinlock_t lock; =20 @@ -898,7 +905,7 @@ static void mtk_star_init_config(struct mtk_star_priv *= priv) regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val); regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF, MTK_STAR_MSK_MAC_CLK_CONF, - MTK_STAR_BIT_CLK_DIV_10); + priv->compat_data->bit_clk_div); } =20 static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) @@ -1460,6 +1467,7 @@ static int mtk_star_probe(struct platform_device *pde= v) =20 priv =3D netdev_priv(ndev); priv->ndev =3D ndev; + priv->compat_data =3D of_device_get_match_data(&pdev->dev); SET_NETDEV_DEV(ndev, dev); platform_set_drvdata(pdev, ndev); =20 @@ -1556,10 +1564,17 @@ static int mtk_star_probe(struct platform_device *p= dev) } =20 #ifdef CONFIG_OF +static const struct mtk_star_compat mtk_star_mt8516_compat =3D { + .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_10, +}; + static const struct of_device_id mtk_star_of_match[] =3D { - { .compatible =3D "mediatek,mt8516-eth", }, - { .compatible =3D "mediatek,mt8518-eth", }, - { .compatible =3D "mediatek,mt8175-eth", }, + { .compatible =3D "mediatek,mt8516-eth", + .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8518-eth", + .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8175-eth", + .data =3D &mtk_star_mt8516_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C617CC43334 for ; Wed, 29 Jun 2022 03:18:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229717AbiF2DSG (ORCPT ); Tue, 28 Jun 2022 23:18:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbiF2DSA (ORCPT ); Tue, 28 Jun 2022 23:18:00 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48E842CDD1; Tue, 28 Jun 2022 20:17:59 -0700 (PDT) X-UUID: 3f0792f4177542bab283b4b627d0dcee-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:b9f5d488-63a2-4d57-afac-2787478eab27,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham, ACTION:release,TS:100 X-CID-INFO: VERSION:1.1.7,REQID:b9f5d488-63a2-4d57-afac-2787478eab27,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:100 X-CID-META: VersionHash:87442a2,CLOUDID:5ddd1ad6-5d6d-4eaf-a635-828a3ee48b7c,C OID:7ed7beff6384,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 3f0792f4177542bab283b4b627d0dcee-20220629 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 582629879; Wed, 29 Jun 2022 11:17:55 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 29 Jun 2022 11:17:53 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:17:52 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , "Rob Herring" , Bartosz Golaszewski , "Fabien Parent" CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "Matthias Brugger" , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 02/10] net: ethernet: mtk-star-emac: modify IRQ trigger flags Date: Wed, 29 Jun 2022 11:17:35 +0800 Message-ID: <20220629031743.22115-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the flags in request_irq() is IRQF_TRIGGER_NONE, the trigger method is determined by "interrupt" property in dts. So, modify the flag from IRQF_TRIGGER_FALLING to IRQF_TRIGGER_NONE. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Reviewed-by: Bartosz Golaszewski --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 9c54043f7866..f161a55bd09a 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -958,7 +958,7 @@ static int mtk_star_enable(struct net_device *ndev) =20 /* Request the interrupt */ ret =3D request_irq(ndev->irq, mtk_star_handle_irq, - IRQF_TRIGGER_FALLING, ndev->name, ndev); + IRQF_TRIGGER_NONE, ndev->name, ndev); if (ret) goto err_free_skbs; =20 --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CADCC433EF for ; Wed, 29 Jun 2022 03:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229829AbiF2DSM (ORCPT ); Tue, 28 Jun 2022 23:18:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229798AbiF2DSF (ORCPT ); Tue, 28 Jun 2022 23:18:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEF172DAAC; Tue, 28 Jun 2022 20:18:02 -0700 (PDT) X-UUID: 57b3ead8ebb94f76a1454f3bed7e61ff-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:b63aeffa-1364-45f9-ac40-59259d94b967,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.7,REQID:b63aeffa-1364-45f9-ac40-59259d94b967,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:87442a2,CLOUDID:8bdd1ad6-5d6d-4eaf-a635-828a3ee48b7c,C OID:3142f75e81e3,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 57b3ead8ebb94f76a1454f3bed7e61ff-20220629 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 348682674; Wed, 29 Jun 2022 11:17:57 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 29 Jun 2022 11:17:55 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:17:54 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , "Rob Herring" , Bartosz Golaszewski , "Fabien Parent" CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "Matthias Brugger" , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 03/10] net: ethernet: mtk-star-emac: add support for MT8365 SoC Date: Wed, 29 Jun 2022 11:17:36 +0800 Message-ID: <20220629031743.22115-4-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet driver support for MT8365 SoC. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: Fabien Parent --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++--- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index f161a55bd09a..3776af9ac1ff 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -150,6 +150,7 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_STAR_REG_MAC_CLK_CONF 0x00ac #define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0) #define MTK_STAR_BIT_CLK_DIV_10 0x0a +#define MTK_STAR_BIT_CLK_DIV_50 0x32 =20 /* Counter registers. */ #define MTK_STAR_REG_C_RXOKPKT 0x0100 @@ -182,9 +183,11 @@ static const char *const mtk_star_clk_names[] =3D { "c= ore", "reg", "trans" }; #define MTK_STAR_REG_C_RX_TWIST 0x0218 =20 /* Ethernet CFG Control */ -#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4 -#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0) -#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0) +#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4 +#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 +#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 +#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 =20 /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, o= nly @@ -233,6 +236,7 @@ struct mtk_star_ring { }; =20 struct mtk_star_compat { + int (*set_interface_mode)(struct net_device *ndev); unsigned char bit_clk_div; }; =20 @@ -908,13 +912,6 @@ static void mtk_star_init_config(struct mtk_star_priv = *priv) priv->compat_data->bit_clk_div); } =20 -static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) -{ - regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON, - MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII, - MTK_PERICFG_BIT_NIC_CFG_CON_RMII); -} - static int mtk_star_enable(struct net_device *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); @@ -1530,7 +1527,13 @@ static int mtk_star_probe(struct platform_device *pd= ev) return -ENODEV; } =20 - mtk_star_set_mode_rmii(priv); + if (priv->compat_data->set_interface_mode) { + ret =3D priv->compat_data->set_interface_mode(ndev); + if (ret) { + dev_err(dev, "Failed to set phy interface, err =3D %d\n", ret); + return -EINVAL; + } + } =20 ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { @@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *p= dev) } =20 #ifdef CONFIG_OF +static int mt8516_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv =3D netdev_priv(ndev); + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int intf_val; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG0_CON, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); +} + +static int mt8365_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv =3D netdev_priv(ndev); + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int intf_val; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG_CON_V2, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); +} + static const struct mtk_star_compat mtk_star_mt8516_compat =3D { + .set_interface_mode =3D mt8516_set_interface_mode, .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_10, }; =20 +static const struct mtk_star_compat mtk_star_mt8365_compat =3D { + .set_interface_mode =3D mt8365_set_interface_mode, + .bit_clk_div =3D MTK_STAR_BIT_CLK_DIV_50, +}; + static const struct of_device_id mtk_star_of_match[] =3D { { .compatible =3D "mediatek,mt8516-eth", .data =3D &mtk_star_mt8516_compat }, @@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = =3D { .data =3D &mtk_star_mt8516_compat }, { .compatible =3D "mediatek,mt8175-eth", .data =3D &mtk_star_mt8516_compat }, + { .compatible =3D "mediatek,mt8365-eth", + .data =3D &mtk_star_mt8365_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3439C433EF for ; Wed, 29 Jun 2022 03:18:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231156AbiF2DST (ORCPT ); Tue, 28 Jun 2022 23:18:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229997AbiF2DSF (ORCPT ); Tue, 28 Jun 2022 23:18:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93FC3C3; Tue, 28 Jun 2022 20:18:03 -0700 (PDT) X-UUID: c9b8257afc62435ebca2985f45f21993-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:b4442b24-1d25-47c1-b533-8aadb631ff70,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:89dd1ad6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: c9b8257afc62435ebca2985f45f21993-20220629 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 708979057; Wed, 29 Jun 2022 11:17:58 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 29 Jun 2022 11:17:57 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:17:55 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin , Rob Herring Subject: [PATCH net-next v5 04/10] dt-bindings: net: mtk-star-emac: add support for MT8365 Date: Wed, 29 Jun 2022 11:17:37 +0800 Message-ID: <20220629031743.22115-5-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding document for Ethernet on MT8365. Signed-off-by: Biao Huang Reviewed-by: Bartosz Golaszewski Acked-by: Rob Herring --- Documentation/devicetree/bindings/net/mediatek,star-emac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml = b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml index def994c9cbb4..6b0769e831a6 100644 --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt8516-eth - mediatek,mt8518-eth - mediatek,mt8175-eth + - mediatek,mt8365-eth =20 reg: maxItems: 1 --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A7AAC43334 for ; Wed, 29 Jun 2022 03:18:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231200AbiF2DSo (ORCPT ); Tue, 28 Jun 2022 23:18:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230502AbiF2DSI (ORCPT ); Tue, 28 Jun 2022 23:18:08 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73418D8D; Tue, 28 Jun 2022 20:18:06 -0700 (PDT) X-UUID: cdf407a4a73340038c0b5201bfe23b25-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:7d714299-21e0-47dc-a081-c0bc1bbf8366,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:87442a2,CLOUDID:f7dd1ad6-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: cdf407a4a73340038c0b5201bfe23b25-20220629 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2037633284; Wed, 29 Jun 2022 11:18:00 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 29 Jun 2022 11:17:59 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:17:57 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 05/10] net: ethernet: mtk-star-emac: add clock pad selection for RMII Date: Wed, 29 Jun 2022 11:17:38 +0800 Message-ID: <20220629031743.22115-6-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch add a new dts property named "mediatek,rmii-rxc" parsing in driver, which will configure MAC to select which pin the RMII reference clock is connected to, TXC or RXC. TXC pad is the default reference clock pin. If user wants to use RXC pad instead, add "mediatek,rmii-rxc" to corresponding device node. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 3776af9ac1ff..b4d37728be69 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -188,6 +188,8 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) =20 /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, o= nly @@ -264,6 +266,7 @@ struct mtk_star_priv { int speed; int duplex; int pause; + bool rmii_rxc; =20 const struct mtk_star_compat *compat_data; =20 @@ -1527,6 +1530,8 @@ static int mtk_star_probe(struct platform_device *pde= v) return -ENODEV; } =20 + priv->rmii_rxc =3D of_property_read_bool(of_node, "mediatek,rmii-rxc"); + if (priv->compat_data->set_interface_mode) { ret =3D priv->compat_data->set_interface_mode(ndev); if (ret) { @@ -1571,17 +1576,25 @@ static int mt8516_set_interface_mode(struct net_dev= ice *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); struct device *dev =3D mtk_star_get_dev(priv); - unsigned int intf_val; + unsigned int intf_val, ret, rmii_rxc; =20 switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + rmii_rxc =3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; break; default: dev_err(dev, "This interface not supported\n"); return -EINVAL; } =20 + ret =3D regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG1_CON, + MTK_PERICFG_BIT_NIC_CFG_CON_CLK, + rmii_rxc); + if (ret) + return ret; + return regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG0_CON, MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, @@ -1597,6 +1610,7 @@ static int mt8365_set_interface_mode(struct net_devic= e *ndev) switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + intf_val |=3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; break; default: dev_err(dev, "This interface not supported\n"); @@ -1605,7 +1619,8 @@ static int mt8365_set_interface_mode(struct net_devic= e *ndev) =20 return regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON_V2, - MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF | + MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2, intf_val); } =20 --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D63DC433EF for ; Wed, 29 Jun 2022 03:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231444AbiF2DTA (ORCPT ); Tue, 28 Jun 2022 23:19:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231205AbiF2DSX (ORCPT ); Tue, 28 Jun 2022 23:18:23 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADDCEA456; Tue, 28 Jun 2022 20:18:10 -0700 (PDT) X-UUID: d05f7fcb08e64dbbb82463305dd54dc3-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:6f834dc7-0bf1-400c-ab3b-1c5b6e89ea86,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham ,ACTION:release,TS:95 X-CID-INFO: VERSION:1.1.7,REQID:6f834dc7-0bf1-400c-ab3b-1c5b6e89ea86,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:95 X-CID-META: VersionHash:87442a2,CLOUDID:32de1ad6-5d6d-4eaf-a635-828a3ee48b7c,C OID:3142f75e81e3,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: d05f7fcb08e64dbbb82463305dd54dc3-20220629 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1475235419; Wed, 29 Jun 2022 11:18:02 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 29 Jun 2022 11:18:01 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:17:59 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 06/10] net: ethernet: mtk-star-emac: add timing adjustment support Date: Wed, 29 Jun 2022 11:17:39 +0800 Message-ID: <20220629031743.22115-7-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add simple clock inversion for timing adjustment in driver. Add property "mediatek,txc-inverse" or "mediatek,rxc-inverse" to device node when necessary. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index b4d37728be69..05ce62202180 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -130,6 +130,11 @@ static const char *const mtk_star_clk_names[] =3D { "c= ore", "reg", "trans" }; #define MTK_STAR_REG_INT_MASK 0x0054 #define MTK_STAR_BIT_INT_MASK_FNRC BIT(6) =20 +/* Delay-Macro Register */ +#define MTK_STAR_REG_TEST0 0x0058 +#define MTK_STAR_BIT_INV_RX_CLK BIT(30) +#define MTK_STAR_BIT_INV_TX_CLK BIT(31) + /* Misc. Config Register */ #define MTK_STAR_REG_TEST1 0x005c #define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31) @@ -267,6 +272,8 @@ struct mtk_star_priv { int duplex; int pause; bool rmii_rxc; + bool rx_inv; + bool tx_inv; =20 const struct mtk_star_compat *compat_data; =20 @@ -1449,6 +1456,24 @@ static void mtk_star_clk_disable_unprepare(void *dat= a) clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); } =20 +static int mtk_star_set_timing(struct mtk_star_priv *priv) +{ + struct device *dev =3D mtk_star_get_dev(priv); + unsigned int delay_val =3D 0; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); + delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val); +} + static int mtk_star_probe(struct platform_device *pdev) { struct device_node *of_node; @@ -1531,6 +1556,8 @@ static int mtk_star_probe(struct platform_device *pde= v) } =20 priv->rmii_rxc =3D of_property_read_bool(of_node, "mediatek,rmii-rxc"); + priv->rx_inv =3D of_property_read_bool(of_node, "mediatek,rxc-inverse"); + priv->tx_inv =3D of_property_read_bool(of_node, "mediatek,txc-inverse"); =20 if (priv->compat_data->set_interface_mode) { ret =3D priv->compat_data->set_interface_mode(ndev); @@ -1540,6 +1567,12 @@ static int mtk_star_probe(struct platform_device *pd= ev) } } =20 + ret =3D mtk_star_set_timing(priv); + if (ret) { + dev_err(dev, "Failed to set timing, err =3D %d\n", ret); + return -EINVAL; + } + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { dev_err(dev, "unsupported DMA mask\n"); --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F2BBC43334 for ; Wed, 29 Jun 2022 03:18:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231357AbiF2DSu (ORCPT ); Tue, 28 Jun 2022 23:18:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbiF2DSU (ORCPT ); Tue, 28 Jun 2022 23:18:20 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7C7C7653; Tue, 28 Jun 2022 20:18:09 -0700 (PDT) X-UUID: a1b3ac68a07c4ad7a447665cfcffd018-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:972d5f2e-07ca-4766-b78b-31977488b93c,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:4f4a0b86-57f0-47ca-ba27-fe8c57fbf305,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: a1b3ac68a07c4ad7a447665cfcffd018-20220629 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1835165617; Wed, 29 Jun 2022 11:18:04 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 29 Jun 2022 11:18:03 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:18:01 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , "Rob Herring" , Bartosz Golaszewski , "Fabien Parent" CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "Matthias Brugger" , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin , "Rob Herring" Subject: [PATCH net-next v5 07/10] dt-bindings: net: mtk-star-emac: add description for new properties Date: Wed, 29 Jun 2022 11:17:40 +0800 Message-ID: <20220629031743.22115-8-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add description for new properties which will be parsed in driver. Signed-off-by: Biao Huang Acked-by: Rob Herring --- .../bindings/net/mediatek,star-emac.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml = b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml index 6b0769e831a6..64c893c98d80 100644 --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml @@ -48,6 +48,22 @@ properties: Phandle to the device containing the PERICFG register range. This is= used to control the MII mode. =20 + mediatek,rmii-rxc: + type: boolean + description: + If present, indicates that the RMII reference clock, which is from e= xternal + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. + + mediatek,rxc-inverse: + type: boolean + description: + If present, indicates that clock on RXC pad will be inversed. + + mediatek,txc-inverse: + type: boolean + description: + If present, indicates that clock on TXC pad will be inversed. + mdio: $ref: mdio.yaml# unevaluatedProperties: false --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93F5BC43334 for ; Wed, 29 Jun 2022 03:18:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231342AbiF2DSr (ORCPT ); Tue, 28 Jun 2022 23:18:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230417AbiF2DSU (ORCPT ); Tue, 28 Jun 2022 23:18:20 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54CAF64CC; Tue, 28 Jun 2022 20:18:09 -0700 (PDT) X-UUID: 42e57ae5806344f8842774a67a63645b-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:4870107f-3d59-4094-9c42-2e5a6848842b,OB:20,L OB:20,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham ,ACTION:release,TS:95 X-CID-INFO: VERSION:1.1.7,REQID:4870107f-3d59-4094-9c42-2e5a6848842b,OB:20,LOB :20,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:95 X-CID-META: VersionHash:87442a2,CLOUDID:7aace862-0b3f-4b2c-b3a6-ed5c044366a0,C OID:3142f75e81e3,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 42e57ae5806344f8842774a67a63645b-20220629 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 864791453; Wed, 29 Jun 2022 11:18:06 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 29 Jun 2022 11:18:04 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:18:03 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , "Rob Herring" , Bartosz Golaszewski , "Fabien Parent" CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "Matthias Brugger" , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 08/10] net: ethernet: mtk-star-emac: add support for MII interface Date: Wed, 29 Jun 2022 11:17:41 +0800 Message-ID: <20220629031743.22115-9-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for MII interface. If user wants to use MII, assign "MII" to "phy-mode" property in dts. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 05ce62202180..a1165f293494 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -192,6 +192,7 @@ static const char *const mtk_star_clk_names[] =3D { "co= re", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_MII 0 #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 #define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) #define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) @@ -1462,6 +1463,7 @@ static int mtk_star_set_timing(struct mtk_star_priv *= priv) unsigned int delay_val =3D 0; =20 switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_RMII: delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); delay_val |=3D FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); @@ -1543,7 +1545,8 @@ static int mtk_star_probe(struct platform_device *pde= v) ret =3D of_get_phy_mode(of_node, &priv->phy_intf); if (ret) { return ret; - } else if (priv->phy_intf !=3D PHY_INTERFACE_MODE_RMII) { + } else if (priv->phy_intf !=3D PHY_INTERFACE_MODE_RMII && + priv->phy_intf !=3D PHY_INTERFACE_MODE_MII) { dev_err(dev, "unsupported phy mode: %s\n", phy_modes(priv->phy_intf)); return -EINVAL; @@ -1612,6 +1615,10 @@ static int mt8516_set_interface_mode(struct net_devi= ce *ndev) unsigned int intf_val, ret, rmii_rxc; =20 switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_MII; + rmii_rxc =3D 0; + break; case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; rmii_rxc =3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; @@ -1641,6 +1648,9 @@ static int mt8365_set_interface_mode(struct net_devic= e *ndev) unsigned int intf_val; =20 switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: + intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_MII; + break; case PHY_INTERFACE_MODE_RMII: intf_val =3D MTK_PERICFG_BIT_NIC_CFG_CON_RMII; intf_val |=3D priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8C61C433EF for ; Wed, 29 Jun 2022 03:19:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231237AbiF2DTE (ORCPT ); Tue, 28 Jun 2022 23:19:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230489AbiF2DSk (ORCPT ); Tue, 28 Jun 2022 23:18:40 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73E98FD3C; Tue, 28 Jun 2022 20:18:12 -0700 (PDT) X-UUID: 47b5714ed8d743e8a04a6a3d58ccf645-20220629 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:01188897-4b2c-481c-94ca-093fad74f652,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2,CLOUDID:b8ace862-0b3f-4b2c-b3a6-ed5c044366a0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 47b5714ed8d743e8a04a6a3d58ccf645-20220629 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 13461248; Wed, 29 Jun 2022 11:18:08 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 29 Jun 2022 11:18:06 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:18:04 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 09/10] net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs Date: Wed, 29 Jun 2022 11:17:42 +0800 Message-ID: <20220629031743.22115-10-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current driver may lost tx interrupts under bidirectional test with iperf3, which leads to some unexpected issues. This patch let rx/tx interrupt enable/disable separately, and rx/tx are handled in different NAPIs. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 340 ++++++++++-------- 1 file changed, 199 insertions(+), 141 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index a1165f293494..87c6c9bc221d 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -33,6 +33,7 @@ #define MTK_STAR_SKB_ALIGNMENT 16 #define MTK_STAR_HASHTABLE_MC_LIMIT 256 #define MTK_STAR_HASHTABLE_SIZE_MAX 512 +#define MTK_STAR_DESC_NEEDED (MAX_SKB_FRAGS + 4) =20 /* Normally we'd use NET_IP_ALIGN but on arm64 its value is 0 and it doesn= 't * work for this controller. @@ -228,7 +229,8 @@ struct mtk_star_ring_desc_data { struct sk_buff *skb; }; =20 -#define MTK_STAR_RING_NUM_DESCS 128 +#define MTK_STAR_RING_NUM_DESCS 512 +#define MTK_STAR_TX_THRESH (MTK_STAR_RING_NUM_DESCS / 4) #define MTK_STAR_NUM_TX_DESCS MTK_STAR_RING_NUM_DESCS #define MTK_STAR_NUM_RX_DESCS MTK_STAR_RING_NUM_DESCS #define MTK_STAR_NUM_DESCS_TOTAL (MTK_STAR_RING_NUM_DESCS * 2) @@ -263,7 +265,8 @@ struct mtk_star_priv { struct mtk_star_ring rx_ring; =20 struct mii_bus *mii; - struct napi_struct napi; + struct napi_struct tx_napi; + struct napi_struct rx_napi; =20 struct device_node *phy_node; phy_interface_t phy_intf; @@ -379,19 +382,16 @@ mtk_star_ring_push_head_tx(struct mtk_star_ring *ring, mtk_star_ring_push_head(ring, desc_data, flags); } =20 -static unsigned int mtk_star_ring_num_used_descs(struct mtk_star_ring *rin= g) +static unsigned int mtk_star_tx_ring_avail(struct mtk_star_ring *ring) { - return abs(ring->head - ring->tail); -} + u32 avail; =20 -static bool mtk_star_ring_full(struct mtk_star_ring *ring) -{ - return mtk_star_ring_num_used_descs(ring) =3D=3D MTK_STAR_RING_NUM_DESCS; -} + if (ring->tail > ring->head) + avail =3D ring->tail - ring->head - 1; + else + avail =3D MTK_STAR_RING_NUM_DESCS - ring->head + ring->tail - 1; =20 -static bool mtk_star_ring_descs_available(struct mtk_star_ring *ring) -{ - return mtk_star_ring_num_used_descs(ring) > 0; + return avail; } =20 static dma_addr_t mtk_star_dma_map_rx(struct mtk_star_priv *priv, @@ -436,6 +436,36 @@ static void mtk_star_nic_disable_pd(struct mtk_star_pr= iv *priv) MTK_STAR_BIT_MAC_CFG_NIC_PD); } =20 +static void mtk_star_enable_dma_irq(struct mtk_star_priv *priv, + bool rx, bool tx) +{ + u32 value; + + regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); + + if (tx) + value &=3D ~MTK_STAR_BIT_INT_STS_TNTC; + if (rx) + value &=3D ~MTK_STAR_BIT_INT_STS_FNRC; + + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); +} + +static void mtk_star_disable_dma_irq(struct mtk_star_priv *priv, + bool rx, bool tx) +{ + u32 value; + + regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); + + if (tx) + value |=3D MTK_STAR_BIT_INT_STS_TNTC; + if (rx) + value |=3D MTK_STAR_BIT_INT_STS_FNRC; + + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); +} + /* Unmask the three interrupts we care about, mask all others. */ static void mtk_star_intr_enable(struct mtk_star_priv *priv) { @@ -451,20 +481,11 @@ static void mtk_star_intr_disable(struct mtk_star_pri= v *priv) regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~0); } =20 -static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv) -{ - unsigned int val; - - regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); - - return val; -} - static unsigned int mtk_star_intr_ack_all(struct mtk_star_priv *priv) { unsigned int val; =20 - val =3D mtk_star_intr_read(priv); + regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); regmap_write(priv->regs, MTK_STAR_REG_INT_STS, val); =20 return val; @@ -736,25 +757,44 @@ static void mtk_star_free_tx_skbs(struct mtk_star_pri= v *priv) mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_tx); } =20 -/* All processing for TX and RX happens in the napi poll callback. - * - * FIXME: The interrupt handling should be more fine-grained with each - * interrupt enabled/disabled independently when needed. Unfortunatly this - * turned out to impact the driver's stability and until we have something - * working properly, we're disabling all interrupts during TX & RX process= ing - * or when resetting the counter registers. - */ +/** + * mtk_star_handle_irq - Interrupt Handler. + * @irq: interrupt number. + * @data: pointer to a network interface device structure. + * Description : this is the driver interrupt service routine. + * it mainly handles: + * 1. tx complete interrupt for frame transmission. + * 2. rx complete interrupt for frame reception. + * 3. MAC Management Counter interrupt to avoid counter overflow. + **/ static irqreturn_t mtk_star_handle_irq(int irq, void *data) { - struct mtk_star_priv *priv; - struct net_device *ndev; - - ndev =3D data; - priv =3D netdev_priv(ndev); + struct net_device *ndev =3D data; + struct mtk_star_priv *priv =3D netdev_priv(ndev); + unsigned int intr_status =3D mtk_star_intr_ack_all(priv); + bool rx, tx; + + rx =3D (intr_status & MTK_STAR_BIT_INT_STS_FNRC) && + napi_schedule_prep(&priv->rx_napi); + tx =3D (intr_status & MTK_STAR_BIT_INT_STS_TNTC) && + napi_schedule_prep(&priv->tx_napi); + + if (rx || tx) { + spin_lock(&priv->lock); + /* mask Rx and TX Complete interrupt */ + mtk_star_disable_dma_irq(priv, rx, tx); + spin_unlock(&priv->lock); + + if (rx) + __napi_schedule(&priv->rx_napi); + if (tx) + __napi_schedule(&priv->tx_napi); + } =20 - if (netif_running(ndev)) { - mtk_star_intr_disable(priv); - napi_schedule(&priv->napi); + /* interrupt is triggered once any counters reach 0x8000000 */ + if (intr_status & MTK_STAR_REG_INT_STS_MIB_CNT_TH) { + mtk_star_update_stats(priv); + mtk_star_reset_counters(priv); } =20 return IRQ_HANDLED; @@ -970,7 +1010,8 @@ static int mtk_star_enable(struct net_device *ndev) if (ret) goto err_free_skbs; =20 - napi_enable(&priv->napi); + napi_enable(&priv->tx_napi); + napi_enable(&priv->rx_napi); =20 mtk_star_intr_ack_all(priv); mtk_star_intr_enable(priv); @@ -1003,7 +1044,8 @@ static void mtk_star_disable(struct net_device *ndev) struct mtk_star_priv *priv =3D netdev_priv(ndev); =20 netif_stop_queue(ndev); - napi_disable(&priv->napi); + napi_disable(&priv->tx_napi); + napi_disable(&priv->rx_napi); mtk_star_intr_disable(priv); mtk_star_dma_disable(priv); mtk_star_intr_ack_all(priv); @@ -1035,13 +1077,45 @@ static int mtk_star_netdev_ioctl(struct net_device = *ndev, return phy_mii_ioctl(ndev->phydev, req, cmd); } =20 -static int mtk_star_netdev_start_xmit(struct sk_buff *skb, - struct net_device *ndev) +static int __mtk_star_maybe_stop_tx(struct mtk_star_priv *priv, u16 size) +{ + netif_stop_queue(priv->ndev); + + /* Might race with mtk_star_tx_poll, check again */ + smp_mb(); + if (likely(mtk_star_tx_ring_avail(&priv->tx_ring) < size)) + return -EBUSY; + + netif_start_queue(priv->ndev); + + return 0; +} + +static inline int mtk_star_maybe_stop_tx(struct mtk_star_priv *priv, u16 s= ize) +{ + if (likely(mtk_star_tx_ring_avail(&priv->tx_ring) >=3D size)) + return 0; + + return __mtk_star_maybe_stop_tx(priv, size); +} + +static netdev_tx_t mtk_star_netdev_start_xmit(struct sk_buff *skb, + struct net_device *ndev) { struct mtk_star_priv *priv =3D netdev_priv(ndev); struct mtk_star_ring *ring =3D &priv->tx_ring; struct device *dev =3D mtk_star_get_dev(priv); struct mtk_star_ring_desc_data desc_data; + int nfrags =3D skb_shinfo(skb)->nr_frags; + + if (unlikely(mtk_star_tx_ring_avail(ring) < nfrags + 1)) { + if (!netif_queue_stopped(ndev)) { + netif_stop_queue(ndev); + /* This is a hard error, log it. */ + pr_err_ratelimited("Tx ring full when queue awake\n"); + } + return NETDEV_TX_BUSY; + } =20 desc_data.dma_addr =3D mtk_star_dma_map_tx(priv, skb); if (dma_mapping_error(dev, desc_data.dma_addr)) @@ -1049,17 +1123,11 @@ static int mtk_star_netdev_start_xmit(struct sk_buf= f *skb, =20 desc_data.skb =3D skb; desc_data.len =3D skb->len; - - spin_lock_bh(&priv->lock); - mtk_star_ring_push_head_tx(ring, &desc_data); =20 netdev_sent_queue(ndev, skb->len); =20 - if (mtk_star_ring_full(ring)) - netif_stop_queue(ndev); - - spin_unlock_bh(&priv->lock); + mtk_star_maybe_stop_tx(priv, MTK_STAR_DESC_NEEDED); =20 mtk_star_dma_resume_tx(priv); =20 @@ -1091,31 +1159,40 @@ static int mtk_star_tx_complete_one(struct mtk_star= _priv *priv) return ret; } =20 -static void mtk_star_tx_complete_all(struct mtk_star_priv *priv) +static int mtk_star_tx_poll(struct napi_struct *napi, int budget) { + struct mtk_star_priv *priv =3D container_of(napi, struct mtk_star_priv, + tx_napi); + int ret =3D 0, pkts_compl =3D 0, bytes_compl =3D 0, count =3D 0; struct mtk_star_ring *ring =3D &priv->tx_ring; struct net_device *ndev =3D priv->ndev; - int ret, pkts_compl, bytes_compl; - bool wake =3D false; - - spin_lock(&priv->lock); - - for (pkts_compl =3D 0, bytes_compl =3D 0;; - pkts_compl++, bytes_compl +=3D ret, wake =3D true) { - if (!mtk_star_ring_descs_available(ring)) - break; + unsigned int head =3D ring->head; + unsigned int entry =3D ring->tail; =20 + while (entry !=3D head && count < (MTK_STAR_RING_NUM_DESCS - 1)) { ret =3D mtk_star_tx_complete_one(priv); if (ret < 0) break; + + count++; + pkts_compl++; + bytes_compl +=3D ret; + entry =3D ring->tail; } =20 netdev_completed_queue(ndev, pkts_compl, bytes_compl); =20 - if (wake && netif_queue_stopped(ndev)) + if (unlikely(netif_queue_stopped(ndev)) && + (mtk_star_tx_ring_avail(ring) > MTK_STAR_TX_THRESH)) netif_wake_queue(ndev); =20 - spin_unlock(&priv->lock); + if (napi_complete(napi)) { + spin_lock(&priv->lock); + mtk_star_enable_dma_irq(priv, false, true); + spin_unlock(&priv->lock); + } + + return 0; } =20 static void mtk_star_netdev_get_stats64(struct net_device *ndev, @@ -1195,7 +1272,7 @@ static const struct ethtool_ops mtk_star_ethtool_ops = =3D { .set_link_ksettings =3D phy_ethtool_set_link_ksettings, }; =20 -static int mtk_star_receive_packet(struct mtk_star_priv *priv) +static int mtk_star_rx(struct mtk_star_priv *priv, int budget) { struct mtk_star_ring *ring =3D &priv->rx_ring; struct device *dev =3D mtk_star_get_dev(priv); @@ -1203,107 +1280,85 @@ static int mtk_star_receive_packet(struct mtk_star= _priv *priv) struct net_device *ndev =3D priv->ndev; struct sk_buff *curr_skb, *new_skb; dma_addr_t new_dma_addr; - int ret; + int ret, count =3D 0; =20 - spin_lock(&priv->lock); - ret =3D mtk_star_ring_pop_tail(ring, &desc_data); - spin_unlock(&priv->lock); - if (ret) - return -1; + while (count < budget) { + ret =3D mtk_star_ring_pop_tail(ring, &desc_data); + if (ret) + return -1; =20 - curr_skb =3D desc_data.skb; + curr_skb =3D desc_data.skb; =20 - if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || - (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { - /* Error packet -> drop and reuse skb. */ - new_skb =3D curr_skb; - goto push_new_skb; - } + if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || + (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { + /* Error packet -> drop and reuse skb. */ + new_skb =3D curr_skb; + goto push_new_skb; + } =20 - /* Prepare new skb before receiving the current one. Reuse the current - * skb if we fail at any point. - */ - new_skb =3D mtk_star_alloc_skb(ndev); - if (!new_skb) { - ndev->stats.rx_dropped++; - new_skb =3D curr_skb; - goto push_new_skb; - } + /* Prepare new skb before receiving the current one. + * Reuse the current skb if we fail at any point. + */ + new_skb =3D mtk_star_alloc_skb(ndev); + if (!new_skb) { + ndev->stats.rx_dropped++; + new_skb =3D curr_skb; + goto push_new_skb; + } =20 - new_dma_addr =3D mtk_star_dma_map_rx(priv, new_skb); - if (dma_mapping_error(dev, new_dma_addr)) { - ndev->stats.rx_dropped++; - dev_kfree_skb(new_skb); - new_skb =3D curr_skb; - netdev_err(ndev, "DMA mapping error of RX descriptor\n"); - goto push_new_skb; - } + new_dma_addr =3D mtk_star_dma_map_rx(priv, new_skb); + if (dma_mapping_error(dev, new_dma_addr)) { + ndev->stats.rx_dropped++; + dev_kfree_skb(new_skb); + new_skb =3D curr_skb; + netdev_err(ndev, "DMA mapping error of RX descriptor\n"); + goto push_new_skb; + } =20 - /* We can't fail anymore at this point: it's safe to unmap the skb. */ - mtk_star_dma_unmap_rx(priv, &desc_data); + /* We can't fail anymore at this point: + * it's safe to unmap the skb. + */ + mtk_star_dma_unmap_rx(priv, &desc_data); =20 - skb_put(desc_data.skb, desc_data.len); - desc_data.skb->ip_summed =3D CHECKSUM_NONE; - desc_data.skb->protocol =3D eth_type_trans(desc_data.skb, ndev); - desc_data.skb->dev =3D ndev; - netif_receive_skb(desc_data.skb); + skb_put(desc_data.skb, desc_data.len); + desc_data.skb->ip_summed =3D CHECKSUM_NONE; + desc_data.skb->protocol =3D eth_type_trans(desc_data.skb, ndev); + desc_data.skb->dev =3D ndev; + netif_receive_skb(desc_data.skb); =20 - /* update dma_addr for new skb */ - desc_data.dma_addr =3D new_dma_addr; + /* update dma_addr for new skb */ + desc_data.dma_addr =3D new_dma_addr; =20 push_new_skb: - desc_data.len =3D skb_tailroom(new_skb); - desc_data.skb =3D new_skb; =20 - spin_lock(&priv->lock); - mtk_star_ring_push_head_rx(ring, &desc_data); - spin_unlock(&priv->lock); - - return 0; -} - -static int mtk_star_process_rx(struct mtk_star_priv *priv, int budget) -{ - int received, ret; + count++; =20 - for (received =3D 0, ret =3D 0; received < budget && ret =3D=3D 0; receiv= ed++) - ret =3D mtk_star_receive_packet(priv); + desc_data.len =3D skb_tailroom(new_skb); + desc_data.skb =3D new_skb; + mtk_star_ring_push_head_rx(ring, &desc_data); + } =20 mtk_star_dma_resume_rx(priv); =20 - return received; + return count; } =20 -static int mtk_star_poll(struct napi_struct *napi, int budget) +static int mtk_star_rx_poll(struct napi_struct *napi, int budget) { struct mtk_star_priv *priv; - unsigned int status; - int received =3D 0; - - priv =3D container_of(napi, struct mtk_star_priv, napi); - - status =3D mtk_star_intr_read(priv); - mtk_star_intr_ack_all(priv); - - if (status & MTK_STAR_BIT_INT_STS_TNTC) - /* Clean-up all TX descriptors. */ - mtk_star_tx_complete_all(priv); + int work_done =3D 0; =20 - if (status & MTK_STAR_BIT_INT_STS_FNRC) - /* Receive up to $budget packets. */ - received =3D mtk_star_process_rx(priv, budget); + priv =3D container_of(napi, struct mtk_star_priv, rx_napi); =20 - if (unlikely(status & MTK_STAR_REG_INT_STS_MIB_CNT_TH)) { - mtk_star_update_stats(priv); - mtk_star_reset_counters(priv); + work_done =3D mtk_star_rx(priv, budget); + if (work_done < budget) { + napi_complete_done(napi, work_done); + spin_lock(&priv->lock); + mtk_star_enable_dma_irq(priv, true, false); + spin_unlock(&priv->lock); } =20 - if (received < budget) - napi_complete_done(napi, received); - - mtk_star_intr_enable(priv); - - return received; + return work_done; } =20 static void mtk_star_mdio_rwok_clear(struct mtk_star_priv *priv) @@ -1602,7 +1657,10 @@ static int mtk_star_probe(struct platform_device *pd= ev) ndev->netdev_ops =3D &mtk_star_netdev_ops; ndev->ethtool_ops =3D &mtk_star_ethtool_ops; =20 - netif_napi_add(ndev, &priv->napi, mtk_star_poll, NAPI_POLL_WEIGHT); + netif_napi_add(ndev, &priv->rx_napi, mtk_star_rx_poll, + NAPI_POLL_WEIGHT); + netif_tx_napi_add(ndev, &priv->tx_napi, mtk_star_tx_poll, + NAPI_POLL_WEIGHT); =20 return devm_register_netdev(dev, ndev); } --=20 2.25.1 From nobody Sat Sep 21 21:38:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE2B6CCA480 for ; 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Wed, 29 Jun 2022 11:18:09 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 29 Jun 2022 11:18:08 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 29 Jun 2022 11:18:06 +0800 From: Biao Huang To: David Miller , Jakub Kicinski , "Rob Herring" , Bartosz Golaszewski , "Fabien Parent" CC: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "Matthias Brugger" , , , , , , Biao Huang , Yinghua Pan , Macpaul Lin Subject: [PATCH net-next v5 10/10] net: ethernet: mtk-star-emac: enable half duplex hardware support Date: Wed, 29 Jun 2022 11:17:43 +0800 Message-ID: <20220629031743.22115-11-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629031743.22115-1-biao.huang@mediatek.com> References: <20220629031743.22115-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current driver doesn't support half duplex correctly. This patch enable half duplex capability in hardware. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 30 ++++++++----------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 87c6c9bc221d..21c3668194eb 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -883,32 +883,26 @@ static void mtk_star_phy_config(struct mtk_star_priv = *priv) val <<=3D MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD; =20 val |=3D MTK_STAR_BIT_PHY_CTRL1_AN_EN; - val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; - val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; - /* Only full-duplex supported for now. */ - val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; - - regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); - if (priv->pause) { - val =3D MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; - val <<=3D MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; - val |=3D MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; + val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; + val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; + val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; } else { - val =3D 0; + val &=3D ~MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; + val &=3D ~MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; + val &=3D ~MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; } + regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); =20 + val =3D MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; + val <<=3D MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; + val |=3D MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; regmap_update_bits(priv->regs, MTK_STAR_REG_FC_CFG, MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH | MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR, val); =20 - if (priv->pause) { - val =3D MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; - val <<=3D MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; - } else { - val =3D 0; - } - + val =3D MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; + val <<=3D MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; regmap_update_bits(priv->regs, MTK_STAR_REG_EXT_CFG, MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS, val); } --=20 2.25.1