From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24F01C433EF for ; Tue, 28 Jun 2022 12:23:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345621AbiF1MXW (ORCPT ); Tue, 28 Jun 2022 08:23:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345666AbiF1MXP (ORCPT ); Tue, 28 Jun 2022 08:23:15 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6807B12636; Tue, 28 Jun 2022 05:23:14 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0561160FC7; Tue, 28 Jun 2022 12:23:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D657C341CE; Tue, 28 Jun 2022 12:23:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656418993; bh=bw4JxdKBLg5YZjdvIpofcV0Tb/wNIuvBvilj7qW7zR0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NlG8+Oki4S49DTX5lyXPrUoA0zvZXhni38IAMJwdfhYUd4J+oLh2DRXIkSVheOAti yJFyC5rKCtSd6XL0SVdjXDRLEqdXlcGge+Mwh0dDaXyOWSXJOizEiMqmOx8QnQE6SV y9qpA8gxoEag9lZ29lEgdyf+C5RnI3G9pZNKtJsSh6FDL/lMXyVtGa+kQU+5AUzolR rsq5m0DCeBMhlZ2ccc0lZ64mEmmjJu6rgHpZpJoO3cJpKF2kWQozMRZn4cNf+Qnkj0 FuriCOXpjGQDOu4frPjvIGlJTRSrHZYySz4plDp1O67yom+/0ScHw0f1xZIBAnVBlL dyoUGJlFHAAIQ== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Roger Quadros Subject: [PATCH 1/7] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200 Date: Tue, 28 Jun 2022 15:22:49 +0300 Message-Id: <20220628122255.24265-2-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli Signed-off-by: Vignesh Raghavendra Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-j721e-wiz.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 70bac931f99a..8c10ee8e2707 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -325,7 +325,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz) int i; =20 for (i =3D 0; i < num_lanes; i++) { - if (wiz->lane_phy_type[i] =3D=3D PHY_TYPE_QSGMII) { + if (wiz->lane_phy_type[i] =3D=3D PHY_TYPE_SGMII || + wiz->lane_phy_type[i] =3D=3D PHY_TYPE_QSGMII) { ret =3D regmap_field_write(wiz->p_mac_div_sel0[i], 1); if (ret) return ret; @@ -1025,12 +1026,18 @@ static int wiz_phy_reset_assert(struct reset_contro= ller_dev *rcdev, =20 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) { - if (wiz->type !=3D AM64_WIZ_10G) + switch (wiz->type) { + case AM64_WIZ_10G: + if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_PCIE) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + break; + case J721E_WIZ_10G: + if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); + break; + default: return 0; - - if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_PCIE) - return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); - + } return 0; } =20 --=20 2.17.1 From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C1F2CCA479 for ; Tue, 28 Jun 2022 12:23:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345670AbiF1MXX (ORCPT ); Tue, 28 Jun 2022 08:23:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345563AbiF1MXS (ORCPT ); Tue, 28 Jun 2022 08:23:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80E44BE29; Tue, 28 Jun 2022 05:23:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1DEDB61471; Tue, 28 Jun 2022 12:23:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E02C9C341CA; Tue, 28 Jun 2022 12:23:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656418996; bh=624BIf6Kfhc5tEzLjhEHS2z9HYf+RPyNRQJ7oltMkMA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sVyNz+LD5Bzl+G6SrVV0hsBlc31CCNV7+hQ9xo+8NhYcuUaqVIAHHZseLxwNAKzMz 8G2+gcfGqAdvaz6BI4f60EKoSzJ1idQJRyi16zqBlR99e3/39XWBHiPdBoy1mWAHQD T19hdhQnQy/Fa67QiVmbSLlQ4dDhFZbUxJgjScELv1UTUAr+DA4rYLQ94IC/tod/jy bG+DYcrnz4kvcHw5Iy/iLh4ApjmvQE9gbOB+UTE8HtU86/rJkjiZrSttzgH8Sh4PtH BcbcLm94HSn3I6qKf5JQUu2qNiH2VsQegYv1hFmj9V3pD9KPKYoAMhyaRRc9WwDUDG ZGvF7qxteSUcw== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Roger Quadros Subject: [PATCH 2/7] dt-bindings: phy: Add PHY_TYPE_USXGMII definition Date: Tue, 28 Jun 2022 15:22:50 +0300 Message-Id: <20220628122255.24265-3-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Swapnil Jakhade Add definition for USXGMII phy type. Cc: Rob Herring Signed-off-by: Swapnil Jakhade Signed-off-by: Roger Quadros Acked-by: Rob Herring --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index f48c9acf251e..6b901b342348 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -22,5 +22,6 @@ #define PHY_TYPE_QSGMII 9 #define PHY_TYPE_DPHY 10 #define PHY_TYPE_CPHY 11 +#define PHY_TYPE_USXGMII 12 =20 #endif /* _DT_BINDINGS_PHY */ --=20 2.17.1 From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD2ECC433EF for ; Tue, 28 Jun 2022 12:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345589AbiF1MX2 (ORCPT ); Tue, 28 Jun 2022 08:23:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345023AbiF1MXW (ORCPT ); Tue, 28 Jun 2022 08:23:22 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1726DF19; Tue, 28 Jun 2022 05:23:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5D36F61471; Tue, 28 Jun 2022 12:23:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0516CC341CF; Tue, 28 Jun 2022 12:23:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656418999; bh=1V8MXkUgNi2dcarHxNrHOzzjdAUMNaQOkHe4RSHwLdE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Amuzenp5fcgyTfrovE+uSCAOii+Rs7Qv7Lq3/mE/7CYVxIvODoc1UZjkPtSXL85A6 Gy/zJhBflTXxNN7ruQUVRD31IlK5R4Ahi30scRUZmZ/clkjGQqOyGZO8ptFb1Pdat1 G4DovSYjlHjW72EGPn6r8ZuyL7/apGo2edAGvfvFfVgOVuIOCKiYQL6sKiDjFjwh6b eDcu6gV8muOJSutU7wI+szP3gxJfiNBl5c7ynFL3Sh/FS4795lw2j+vKMQpr/WG9n1 twluTyfRRl+yiNbbxnqlJ7iNsl29GXJg8JBJA9I6jOqPyCgSp5IJyMOfAdEmWwUeMk ScWI3Xwj3pZFA== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Roger Quadros Subject: [PATCH 3/7] phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver Date: Tue, 28 Jun 2022 15:22:51 +0300 Message-Id: <20220628122255.24265-4-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tanmay Patil Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by: Tanmay Patil Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-j721e-wiz.c | 51 +++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 8c10ee8e2707..77accea6ec2f 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -129,6 +129,26 @@ static const struct reg_field p0_fullrt_div[WIZ_MAX_LA= NES] =3D { REG_FIELD(WIZ_LANECTL(3), 22, 23), }; =20 +static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] =3D { + REG_FIELD(WIZ_LANECTL(0), 20, 21), + REG_FIELD(WIZ_LANECTL(1), 20, 21), + REG_FIELD(WIZ_LANECTL(2), 20, 21), + REG_FIELD(WIZ_LANECTL(3), 20, 21), +}; + +static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] =3D { + REG_FIELD(WIZ_LANECTL(0), 6, 7), + REG_FIELD(WIZ_LANECTL(1), 6, 7), + REG_FIELD(WIZ_LANECTL(2), 6, 7), + REG_FIELD(WIZ_LANECTL(3), 6, 7), +}; + +static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] =3D { + REG_FIELD(WIZ_LANECTL(0), 18, 19), + REG_FIELD(WIZ_LANECTL(1), 18, 19), + REG_FIELD(WIZ_LANECTL(2), 18, 19), + REG_FIELD(WIZ_LANECTL(3), 18, 19), +}; static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] =3D { REG_FIELD(WIZ_LANEDIV(0), 16, 22), REG_FIELD(WIZ_LANEDIV(1), 16, 22), @@ -280,6 +300,9 @@ struct wiz { struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; + struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; + struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; + struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; @@ -326,7 +349,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz) =20 for (i =3D 0; i < num_lanes; i++) { if (wiz->lane_phy_type[i] =3D=3D PHY_TYPE_SGMII || - wiz->lane_phy_type[i] =3D=3D PHY_TYPE_QSGMII) { + wiz->lane_phy_type[i] =3D=3D PHY_TYPE_QSGMII || + wiz->lane_phy_type[i] =3D=3D PHY_TYPE_USXGMII) { ret =3D regmap_field_write(wiz->p_mac_div_sel0[i], 1); if (ret) return ret; @@ -355,6 +379,13 @@ static int wiz_mode_select(struct wiz *wiz) else continue; =20 + if (wiz->lane_phy_type[i] =3D=3D PHY_TYPE_USXGMII) { + ret =3D regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); + ret =3D regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); + ret =3D regmap_field_write(wiz->p0_refclk_sel[i], 0x3); + mode =3D LANE_MODE_GEN1; + } + ret =3D regmap_field_write(wiz->p_standard_mode[i], mode); if (ret) return ret; @@ -524,6 +555,24 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->p0_fullrt_div[i]); } =20 + wiz->p0_mac_src_sel[i] =3D devm_regmap_field_alloc(dev, regmap, p0_mac_s= rc_sel[i]); + if (IS_ERR(wiz->p0_mac_src_sel[i])) { + dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); + return PTR_ERR(wiz->p0_mac_src_sel[i]); + } + + wiz->p0_rxfclk_sel[i] =3D devm_regmap_field_alloc(dev, regmap, p0_rxfclk= _sel[i]); + if (IS_ERR(wiz->p0_rxfclk_sel[i])) { + dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); + return PTR_ERR(wiz->p0_rxfclk_sel[i]); + } + + wiz->p0_refclk_sel[i] =3D devm_regmap_field_alloc(dev, regmap, p0_refclk= _sel[i]); + if (IS_ERR(wiz->p0_refclk_sel[i])) { + dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); + return PTR_ERR(wiz->p0_refclk_sel[i]); + } + wiz->p_mac_div_sel0[i] =3D devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); if (IS_ERR(wiz->p_mac_div_sel0[i])) { --=20 2.17.1 From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F0A7C433EF for ; Tue, 28 Jun 2022 12:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345602AbiF1MXc (ORCPT ); Tue, 28 Jun 2022 08:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345596AbiF1MXY (ORCPT ); Tue, 28 Jun 2022 08:23:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0EB21208B; Tue, 28 Jun 2022 05:23:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6E61160FFD; Tue, 28 Jun 2022 12:23:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 468ECC341CB; Tue, 28 Jun 2022 12:23:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656419002; bh=qYPfnzTqV+BxctBlh0HulqRk4JegMdUP1qyxoejHvUA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Khf4igej+0j3Ni7xatEFL0AMD2MMQoFYj+Xd85iYQghPGkG99zWk4VCmswSQ32CoL NJTH8ntIj3Qiz8UFwckFrLpmxzLRHzYbwSooyxo/wKtdQ+4e/FziDAgxd/92M8X/bS VQO7rW0+rWDvmbHRMIroszel5s+mRVVRv3bYYoSyFcJp5Ni12zou+vCVTXLpnpkDBc xUHviytXvaCFQVigAwz+aCXVfbmnIas7uXNKnmjIit9Lo1DIr82wDlSbMJJs2MH/PN Rbo1IMJI4y2EOnaW+NuebuJ5SdYe1HJnjHLwAVQfkhK5P0g1MV0HqlcEXkXY1TC7xc pzVS1jb+dtkhQ== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Roger Quadros , Rob Herring Subject: [PATCH 4/7] dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes Date: Tue, 28 Jun 2022 15:22:52 +0300 Message-Id: <20220628122255.24265-5-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div" as deprecated. The clock muxes are provided by the device driver so not required in device tree. Cc: Rob Herring Signed-off-by: Roger Quadros Acked-by: Rob Herring --- Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/= Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index dcd63908aeae..3127bb648427 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -83,6 +83,7 @@ properties: WIZ node should have subnode for refclk_dig to select the reference clock source for the reference clock used in the PHY and PMA digital logic. + deprecated: true properties: clocks: minItems: 2 @@ -111,6 +112,7 @@ patternProperties: description: | WIZ node should have subnodes for each of the PLLs present in the SERDES. + deprecated: true properties: clocks: maxItems: 2 @@ -136,6 +138,7 @@ patternProperties: description: WIZ node should have subnodes for each of the PMA common refclock provided by the SERDES. + deprecated: true properties: clocks: maxItems: 1 --=20 2.17.1 From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E381CCA479 for ; Tue, 28 Jun 2022 12:23:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345601AbiF1MXi (ORCPT ); Tue, 28 Jun 2022 08:23:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345661AbiF1MX3 (ORCPT ); Tue, 28 Jun 2022 08:23:29 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BBE31D312; Tue, 28 Jun 2022 05:23:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 310A2B81E06; Tue, 28 Jun 2022 12:23:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55B11C341CA; Tue, 28 Jun 2022 12:23:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656419005; bh=SmqaQDNLD/5+VbZXpZxV6RGZ6+ob/LvJ25zs+IIEgoA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YVCm1kwexQmPi05+mfii6ESvEleglXwgOHzBVhuvhGo4HP0VCgTMC+pJS//xGUXO9 l4lvreqRYEuyiVXOmdh8nxSwIjl7aNuMTWMG386GCB0uQI6eBZJr+JMsPpyfObx1EI dxxYfMr+HsF6XLgPkOc2vcMvy2/9ceuNDlVGQN+qMQIhhp1rCD3JItN0gomxE43fDs dW0Myl451THIzRUxYeEjhxLqrTPxu/CyI7sFb0GZm9aDEF/PdhEpmur4J0weH/qqHP vnZnKhUP0zsGRAcjJAByrR/0/QNqGVR/4BsAHMUwxt5l6HFOudPo6ucFljBeSFI4a7 7YNYmxpvZah5w== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Roger Quadros , Rob Herring Subject: [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g Date: Tue, 28 Jun 2022 15:22:53 +0300 Message-Id: <20220628122255.24265-6-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ti,j7200-wiz-10g supports an additional reference clock. Add compatible and the additional clock. Cc: Rob Herring Signed-off-by: Roger Quadros Acked-by: Rob Herring --- .../bindings/phy/ti,phy-j721e-wiz.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/= Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 3127bb648427..8305654b66c9 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -16,19 +16,23 @@ properties: - ti,j721e-wiz-16g - ti,j721e-wiz-10g - ti,am64-wiz-10g + - ti,j7200-wiz-10g =20 power-domains: maxItems: 1 =20 clocks: - maxItems: 3 + minItems: 3 + maxItems: 4 description: clock-specifier to represent input to the WIZ =20 clock-names: + minItems: 3 items: - const: fck - const: core_ref_clk - const: ext_ref_clk + - const: core_ref1_clk =20 num-lanes: minimum: 1 @@ -106,6 +110,11 @@ properties: - assigned-clocks - assigned-clock-parents =20 + ti,scm: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to System Control Module for syscon regmap access. + patternProperties: "^pll[0|1]-refclk$": type: object @@ -173,6 +182,16 @@ required: - "#reset-cells" - ranges =20 +allOf: + - if: + properties: + compatible: + contains: + const: ti,j7200-wiz-10g + then: + required: + - ti,scm + additionalProperties: false =20 examples: --=20 2.17.1 From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F359C43334 for ; Tue, 28 Jun 2022 12:23:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345605AbiF1MXj (ORCPT ); Tue, 28 Jun 2022 08:23:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345638AbiF1MXb (ORCPT ); Tue, 28 Jun 2022 08:23:31 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D01FE1D335; Tue, 28 Jun 2022 05:23:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5F4D261474; Tue, 28 Jun 2022 12:23:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 657A5C341CC; Tue, 28 Jun 2022 12:23:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656419008; bh=P7SAAWwCSzVlv2T9lWvUXnEH8devzfc90nldG8hymZU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ggl+R4ju6XZHFHZ0r+RjFHmBt3UGrTgx6aD9lYF3HVGfajARwqUF6blJDFx3twM71 Cg2ohyndHYbRv8ldihz0kEmV7CFiHCBiXW2bBMM4OYY5T8obPbImjHyfHERnSWOJ4H pLQ6hxUPsgCNxiyjf2ux+Zl3ssZY5ydzmOao6cM4dVCeg6F7gIIc5ZE2suFyrDqUe3 Z/L/3doCKxVguNRv7+Jj2hAOX2UkIemNlM6J+8bD5fNSHqq4oolJA99RZjM2ELH0Ps kvyfH5Bb4fWq/PEsZaf2UYEgK59R5ahKnniAZpScBCVOGHp5QtWCNZ2MlkUJ//L+OK j9AMpHceAp0zQ== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Roger Quadros Subject: [PATCH 6/7] phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g Date: Tue, 28 Jun 2022 15:22:54 +0300 Message-Id: <20220628122255.24265-7-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-j721e-wiz.c | 138 ++++++++++++++++++++++++++++++--- 1 file changed, 129 insertions(+), 9 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 77accea6ec2f..cc2ab5152f07 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,10 @@ #include #include =20 +/* SCM offsets */ +#define SERDES_SUP_CTRL 0x4400 + +/* SERDES offsets */ #define WIZ_SERDES_CTRL 0x404 #define WIZ_SERDES_TOP_CTRL 0x408 #define WIZ_SERDES_RST 0x40c @@ -85,6 +90,18 @@ static const struct reg_field pma_cmn_refclk_dig_div =3D REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); static const struct reg_field pma_cmn_refclk1_dig_div =3D REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); + +static const struct reg_field sup_pll0_refclk_mux_sel =3D + REG_FIELD(SERDES_SUP_CTRL, 0, 1); +static const struct reg_field sup_pll1_refclk_mux_sel =3D + REG_FIELD(SERDES_SUP_CTRL, 2, 3); +static const struct reg_field sup_pma_cmn_refclk1_int_mode =3D + REG_FIELD(SERDES_SUP_CTRL, 4, 5); +static const struct reg_field sup_refclk_dig_sel_10g =3D + REG_FIELD(SERDES_SUP_CTRL, 6, 7); +static const struct reg_field sup_legacy_clk_override =3D + REG_FIELD(SERDES_SUP_CTRL, 8, 8); + static const char * const output_clk_names[] =3D { [TI_WIZ_PLL0_REFCLK] =3D "pll0-refclk", [TI_WIZ_PLL1_REFCLK] =3D "pll1-refclk", @@ -248,6 +265,27 @@ static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = =3D { }, }; =20 +static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] =3D { + { + .num_parents =3D 3, + .parents =3D { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table =3D { 2, 3, 0 }, + .node_name =3D "pll0-refclk", + }, + { + .num_parents =3D 3, + .parents =3D { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table =3D { 2, 3, 0 }, + .node_name =3D "pll1-refclk", + }, + { + .num_parents =3D 3, + .parents =3D { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, + .table =3D { 2, 3, 0 }, + .node_name =3D "refclk-dig", + }, +}; + static const struct clk_div_table clk_div_table[] =3D { { .val =3D 0, .div =3D 1, }, { .val =3D 1, .div =3D 2, }, @@ -269,14 +307,18 @@ static const struct wiz_clk_div_sel clk_div_sel[] =3D= { =20 enum wiz_type { J721E_WIZ_16G, - J721E_WIZ_10G, + J721E_WIZ_10G, /* Also for J7200 SR1.0 */ AM64_WIZ_10G, + J7200_WIZ_10G, /* J7200 SR2.0 */ }; =20 struct wiz_data { enum wiz_type type; + const struct reg_field *pll0_refclk_mux_sel; + const struct reg_field *pll1_refclk_mux_sel; const struct reg_field *refclk_dig_sel; const struct reg_field *pma_cmn_refclk1_dig_div; + const struct reg_field *pma_cmn_refclk1_int_mode; const struct wiz_clk_mux_sel *clk_mux_sel; unsigned int clk_div_sel_num; }; @@ -286,6 +328,7 @@ struct wiz_data { =20 struct wiz { struct regmap *regmap; + struct regmap *scm_regmap; enum wiz_type type; const struct wiz_clk_mux_sel *clk_mux_sel; const struct wiz_clk_div_sel *clk_div_sel; @@ -304,12 +347,14 @@ struct wiz { struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; + struct regmap_field *pma_cmn_refclk1_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; struct regmap_field *pma_cmn_refclk1_dig_div; struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; struct regmap_field *typec_ln10_swap; + struct regmap_field *sup_legacy_clk_override; =20 struct device *dev; u32 num_lanes; @@ -448,6 +493,7 @@ static int wiz_init(struct wiz *wiz) static int wiz_regfield_init(struct wiz *wiz) { struct regmap *regmap =3D wiz->regmap; + struct regmap *scm_regmap =3D wiz->regmap; /* updated later to scm_regmap= if applicable */ int num_lanes =3D wiz->num_lanes; struct device *dev =3D wiz->dev; const struct wiz_data *data =3D wiz->data; @@ -497,27 +543,46 @@ static int wiz_regfield_init(struct wiz *wiz) } } =20 + if (wiz->scm_regmap) { + scm_regmap =3D wiz->scm_regmap; + wiz->sup_legacy_clk_override =3D + devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); + if (IS_ERR(wiz->sup_legacy_clk_override)) { + dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); + return PTR_ERR(wiz->sup_legacy_clk_override); + } + } + wiz->mux_sel_field[PLL0_REFCLK] =3D - devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel); + devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); } =20 wiz->mux_sel_field[PLL1_REFCLK] =3D - devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel); + devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); } =20 - wiz->mux_sel_field[REFCLK_DIG] =3D devm_regmap_field_alloc(dev, regmap, + wiz->mux_sel_field[REFCLK_DIG] =3D devm_regmap_field_alloc(dev, scm_regma= p, *data->refclk_dig_sel); if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); } =20 + if (data->pma_cmn_refclk1_int_mode) { + wiz->pma_cmn_refclk1_int_mode =3D + devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mod= e); + if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { + dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); + } + } + for (i =3D 0; i < num_lanes; i++) { wiz->p_enable[i] =3D devm_regmap_field_alloc(dev, regmap, p_enable[i]); @@ -906,9 +971,13 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct = device_node *node) struct device_node *clk_node; int i; =20 - if (wiz->type =3D=3D AM64_WIZ_10G) { + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: of_clk_del_provider(dev->of_node); return; + default: + break; } =20 for (i =3D 0; i < WIZ_MUX_NUM_CLOCKS; i++) { @@ -935,9 +1004,6 @@ static int wiz_clock_register(struct wiz *wiz) int ret; int i; =20 - if (wiz->type !=3D AM64_WIZ_10G) - return 0; - clk_index =3D TI_WIZ_PLL0_REFCLK; for (i =3D 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { ret =3D wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i]= , clk_index); @@ -987,6 +1053,22 @@ static int wiz_clock_init(struct wiz *wiz, struct dev= ice_node *node) else regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); =20 + if (wiz->data->pma_cmn_refclk1_int_mode) { + clk =3D devm_clk_get(dev, "core_ref1_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref1_clk clock not found\n"); + ret =3D PTR_ERR(clk); + return ret; + } + wiz->input_clks[WIZ_CORE_REFCLK1] =3D clk; + + rate =3D clk_get_rate(clk); + if (rate >=3D 100000000) + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); + else + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); + } + clk =3D devm_clk_get(dev, "ext_ref_clk"); if (IS_ERR(clk)) { dev_err(dev, "ext_ref_clk clock not found\n"); @@ -1001,11 +1083,15 @@ static int wiz_clock_init(struct wiz *wiz, struct d= evice_node *node) else regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); =20 - if (wiz->type =3D=3D AM64_WIZ_10G) { + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: ret =3D wiz_clock_register(wiz); if (ret) dev_err(dev, "Failed to register wiz clocks\n"); return ret; + default: + break; } =20 for (i =3D 0; i < WIZ_MUX_NUM_CLOCKS; i++) { @@ -1081,6 +1167,7 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int la= ne) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); break; case J721E_WIZ_10G: + case J7200_WIZ_10G: if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); break; @@ -1139,6 +1226,8 @@ static const struct regmap_config wiz_regmap_config = =3D { =20 static struct wiz_data j721e_16g_data =3D { .type =3D J721E_WIZ_16G, + .pll0_refclk_mux_sel =3D &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel =3D &pll1_refclk_mux_sel, .refclk_dig_sel =3D &refclk_dig_sel_16g, .pma_cmn_refclk1_dig_div =3D &pma_cmn_refclk1_dig_div, .clk_mux_sel =3D clk_mux_sel_16g, @@ -1147,6 +1236,8 @@ static struct wiz_data j721e_16g_data =3D { =20 static struct wiz_data j721e_10g_data =3D { .type =3D J721E_WIZ_10G, + .pll0_refclk_mux_sel =3D &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel =3D &pll1_refclk_mux_sel, .refclk_dig_sel =3D &refclk_dig_sel_10g, .clk_mux_sel =3D clk_mux_sel_10g, .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, @@ -1154,11 +1245,23 @@ static struct wiz_data j721e_10g_data =3D { =20 static struct wiz_data am64_10g_data =3D { .type =3D AM64_WIZ_10G, + .pll0_refclk_mux_sel =3D &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel =3D &pll1_refclk_mux_sel, .refclk_dig_sel =3D &refclk_dig_sel_10g, .clk_mux_sel =3D clk_mux_sel_10g, .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, }; =20 +static struct wiz_data j7200_pg2_10g_data =3D { + .type =3D J7200_WIZ_10G, + .pll0_refclk_mux_sel =3D &sup_pll0_refclk_mux_sel, + .pll1_refclk_mux_sel =3D &sup_pll1_refclk_mux_sel, + .refclk_dig_sel =3D &sup_refclk_dig_sel_10g, + .pma_cmn_refclk1_int_mode =3D &sup_pma_cmn_refclk1_int_mode, + .clk_mux_sel =3D clk_mux_sel_10g_2_refclk, + .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, +}; + static const struct of_device_id wiz_id_table[] =3D { { .compatible =3D "ti,j721e-wiz-16g", .data =3D &j721e_16g_data, @@ -1169,6 +1272,9 @@ static const struct of_device_id wiz_id_table[] =3D { { .compatible =3D "ti,am64-wiz-10g", .data =3D &am64_10g_data, }, + { + .compatible =3D "ti,j7200-wiz-10g", .data =3D &j7200_pg2_10g_data, + }, {} }; MODULE_DEVICE_TABLE(of, wiz_id_table); @@ -1266,6 +1372,16 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } =20 + wiz->scm_regmap =3D syscon_regmap_lookup_by_phandle(node, "ti,scm"); + if (IS_ERR(wiz->scm_regmap)) { + if (wiz->type =3D=3D J7200_WIZ_10G) { + dev_err(dev, "Couldn't get ti,scm regmap\n"); + return -ENODEV; + } + + wiz->scm_regmap =3D NULL; + } + ret =3D of_property_read_u32(node, "num-lanes", &num_lanes); if (ret) { dev_err(dev, "Failed to read num-lanes property\n"); @@ -1327,6 +1443,10 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } =20 + /* Enable supplemental Control override if available */ + if (wiz->scm_regmap) + regmap_field_write(wiz->sup_legacy_clk_override, 1); + phy_reset_dev =3D &wiz->wiz_phy_reset_dev; phy_reset_dev->dev =3D dev; phy_reset_dev->ops =3D &wiz_phy_reset_ops, --=20 2.17.1 From nobody Sun Apr 26 12:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A61CC433EF for ; Tue, 28 Jun 2022 12:23:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345613AbiF1MXl (ORCPT ); Tue, 28 Jun 2022 08:23:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344426AbiF1MXf (ORCPT ); Tue, 28 Jun 2022 08:23:35 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5590213CD8; Tue, 28 Jun 2022 05:23:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EB3F2B81E0A; Tue, 28 Jun 2022 12:23:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4571AC341CF; Tue, 28 Jun 2022 12:23:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656419011; bh=pXV/Nifo7ZhBaapzRCp8sn27XTIo2SKqC2ty0bQ8eTo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sElN7b+rzMLOeuPBwCli5dJvKMF23ZOTVW5+i/RaN9wYbMY4V+9xhy0kA8amUU9uz mbepD3deIyV2kIWIlk/R46OS8ATpD0EmFrI+GFp6Tmw1Dod9HbORyYbwL8yw0p5hZd xLy6AsOZaxXMkxj57NsKdFQiTfRGfB37zehVfszzolfDQXykWdtCd7bc4Bd+kQkdEK u6VTu6xizhyGRFovL2jWpKXagRFYdlUI9/PFwUNnI9sdFtrH1JThx4q/5G6I8Extgv os+T5La1R3pvtIuqsSmhWXT+429rsS4O5telOamfnzM/yR/GC+yGEz7hThG+XO5hrr w6NYzqnKJ4HCA== From: Roger Quadros To: kishon@ti.com, vkoul@kernel.org Cc: vigneshr@ti.com, t-patil@ti.com, sjakhade@cadence.com, s-vadapalli@ti.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Roger Quadros Subject: [PATCH 7/7] phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate Date: Tue, 28 Jun 2022 15:22:55 +0300 Message-Id: <20220628122255.24265-8-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220628122255.24265-1-rogerq@kernel.org> References: <20220628122255.24265-1-rogerq@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index cc2ab5152f07..20af142580ad 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -24,6 +24,11 @@ #include #include =20 +#define REF_CLK_19_2MHZ 19200000 +#define REF_CLK_25MHZ 25000000 +#define REF_CLK_100MHZ 100000000 +#define REF_CLK_156_25MHZ 156250000 + /* SCM offsets */ #define SERDES_SUP_CTRL 0x4400 =20 @@ -1053,6 +1058,25 @@ static int wiz_clock_init(struct wiz *wiz, struct de= vice_node *node) else regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); =20 + switch (wiz->type) { + case AM64_WIZ_10G: + case J7200_WIZ_10G: + switch (rate) { + case REF_CLK_100MHZ: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); + break; + case REF_CLK_156_25MHZ: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); + break; + default: + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); + break; + } + break; + default: + break; + } + if (wiz->data->pma_cmn_refclk1_int_mode) { clk =3D devm_clk_get(dev, "core_ref1_clk"); if (IS_ERR(clk)) { --=20 2.17.1