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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 05:43:52.7703 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e27eb48e-f3e5-4019-6b5e-08da58c92f35 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[20.83.241.18];Helo=[mailrelay000001.14r1f435wfvunndds3vy4cdalc.xx.internal.cloudapp.net] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN1NAM02FT048.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB3846 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds documentation for Triple Modular Redundancy(TMR) Manager IP. The Triple Modular Redundancy(TMR) Manager is responsible for handling the TMR subsystem state, including fault detection and error recovery provides soft error detection, correction and recovery features. Signed-off-by: Appana Durga Kedareswara rao --- .../bindings/misc/xlnx,tmr-manager.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-manager= .yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml b= /Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml new file mode 100644 index 000000000000..f6cb4d235981 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx TMR Microblaze Device Tree Bindings + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Manager is responsible for handling t= he + TMR subsystem state, including fault detection and error recovery. The c= ore + is triplicated in each of the sub-blocks in the TMR subsystem, and provi= des + majority voting of its internal state. + +properties: + compatible: + enum: + - xlnx,tmr-manager-1.0 + + reg: + maxItems: 1 + + xlnx,magic1: + minimum: 0 + maximum: 255 + description: + Magic number 1, When writing to the control register the first write= data + byte (bits 7:0) must match this value in order to have any effect on= the + nominal recovery function. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic1 + +additionalProperties: false + +examples: + - | + tmr-manager@44a10000 { + compatible =3D "xlnx,tmr-manager-1.0"; + reg =3D <0x44a10000 0x10000>; + xlnx,magic1 =3D <0x46>; + }; --=20 2.25.1 From nobody Sun Apr 19 18:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 605CAC433EF for ; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 05:43:58.4075 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1c3a7dc-0a6f-4fa9-8496-08da58c9327e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[20.83.241.18];Helo=[mailrelay000000.14r1f435wfvunndds3vy4cdalc.xx.internal.cloudapp.net] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-DM3NAM02FT029.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR02MB5140 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Triple Modular Redundancy(TMR) Manager is responsible for handling the TMR subsystem state, including fault detection and error recovery provides soft error detection, correction and recovery features. This commit adds support for fault detection feature via sysfs interface. Usage: To know the hardware status: cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/status To know the break handler count(Error count): cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt Signed-off-by: Appana Durga Kedareswara rao --- .../testing/sysfs-driver-xilinx-tmr-manager | 18 ++ MAINTAINERS | 7 + drivers/misc/Kconfig | 10 + drivers/misc/Makefile | 1 + drivers/misc/xilinx_tmr_manager.c | 288 ++++++++++++++++++ 5 files changed, 324 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manag= er create mode 100644 drivers/misc/xilinx_tmr_manager.c diff --git a/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager b/Do= cumentation/ABI/testing/sysfs-driver-xilinx-tmr-manager new file mode 100644 index 000000000000..c2f615126201 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager @@ -0,0 +1,18 @@ +What: /sys/devices/platform/amba_pl//status +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file provides the status of the tmr manager + useful for getting the status of fault. + This file cannot be written. + +What: /sys/devices/platform/amba_pl//errcnt +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file provides the fault detection count. + This file cannot be written. + +What: /sys/devices/platform/amba_pl//dis_block_break +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file enables the break signal. + This file is write only. diff --git a/MAINTAINERS b/MAINTAINERS index 6cc825857722..3d29109788ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12962,6 +12962,13 @@ W: http://www.monstr.eu/fdt/ T: git git://git.monstr.eu/linux-2.6-microblaze.git F: arch/microblaze/ =20 +MICROBLAZE TMR MANAGER +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager +F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml +F: drivers/misc/xilinx_tmr_manager.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 41d2bb0ae23a..555ae2e33b91 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -483,6 +483,16 @@ config OPEN_DICE =20 If unsure, say N. =20 +config TMR_MANAGER + bool "Select TMR Manager" + depends on MICROBLAZE && MB_MANAGER + help + This option enables the driver developed for TMR Manager. The Triple + Modular Redundancy(TMR) manager provides support for fault detection + via sysfs interface. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 70e800e9127f..28b9803f909b 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_XILINX_SDFEC) +=3D xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) +=3D hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) +=3D hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) +=3D open-dice.o +obj-$(CONFIG_TMR_MANAGER) +=3D xilinx_tmr_manager.o diff --git a/drivers/misc/xilinx_tmr_manager.c b/drivers/misc/xilinx_tmr_ma= nager.c new file mode 100644 index 000000000000..5a4562e4a9d4 --- /dev/null +++ b/drivers/misc/xilinx_tmr_manager.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx TMR Subsystem. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Description: + * This driver is developed for TMR Manager,The Triple Modular Redundancy(= TMR) + * Manager is responsible for handling the TMR subsystem state, including + * fault detection and error recovery. The core is triplicated in each of + * the sub-blocks in the TMR subsystem, and provides majority voting of + * its internal state provides soft error detection, correction and + * recovery. Error detection feature is provided through sysfs + * entries which allow the user to observer the TMR microblaze + * status. + */ + +#include +#include +#include + +/* TMR Manager Register offsets */ +#define XTMR_MANAGER_CR_OFFSET 0x0 +#define XTMR_MANAGER_FFR_OFFSET 0x4 +#define XTMR_MANAGER_CMR0_OFFSET 0x8 +#define XTMR_MANAGER_CMR1_OFFSET 0xC +#define XTMR_MANAGER_BDIR_OFFSET 0x10 +#define XTMR_MANAGER_SEMIMR_OFFSET 0x1C + +/* Register Bitmasks/shifts */ +#define XTMR_MANAGER_CR_MAGIC1_MASK GENMASK(7, 0) +#define XTMR_MANAGER_CR_MAGIC2_MASK GENMASK(15, 8) +#define XTMR_MANAGER_CR_RIR_MASK BIT(16) +#define XTMR_MANAGER_FFR_LM12_MASK BIT(0) +#define XTMR_MANAGER_FFR_LM13_MASK BIT(1) +#define XTMR_MANAGER_FFR_LM23_MASK BIT(2) + +#define XTMR_MANAGER_CR_MAGIC2_SHIFT 4 +#define XTMR_MANAGER_CR_RIR_SHIFT 16 +#define XTMR_MANAGER_CR_BB_SHIFT 18 + +#define XTMR_MANAGER_MAGIC1_MAX_VAL 255 + +/** + * struct xtmr_manager_dev - Driver data for TMR Manager + * @regs: device physical base address + * @dev: pointer to device struct + * @cr_val: control register value + * @magic1: Magic 1 hardware configuration value + * @err_cnt: error statistics count + * @phys_baseaddr: Physical base address + */ +struct xtmr_manager_dev { + void __iomem *regs; + struct device *dev; + u32 cr_val; + u32 magic1; + u32 err_cnt; + uintptr_t phys_baseaddr; +}; + +/* IO accessors */ +static inline void xtmr_manager_write(struct xtmr_manager_dev *xtmr_manage= r, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_manager->regs + addr); +} + +static inline u32 xtmr_manager_read(struct xtmr_manager_dev *xtmr_manager, + u32 addr) +{ + return ioread32(xtmr_manager->regs + addr); +} + +/** + * xtmr_manager_unblock_break - unblocks the break signal + * @xtmr_manager: Pointer to xtmr_manager_dev structure + */ +static void xtmr_manager_unblock_break(struct xtmr_manager_dev *xtmr_manag= er) +{ + xtmr_manager->cr_val &=3D ~(1 << XTMR_MANAGER_CR_BB_SHIFT); + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); +} + +/** + * xmb_manager_reset_handler - clears the ffr register contents + * @priv: Private pointer + */ +static void xmb_manager_reset_handler(void *priv) +{ + struct xtmr_manager_dev *xtmr_manager =3D (struct xtmr_manager_dev *)priv; + /* Clear the FFR Register contents as a part of recovery process. */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_FFR_OFFSET, 0); +} + +/** + * xmb_manager_update_errcnt - update the error inject count + * @priv: Private pointer + */ +static void xmb_manager_update_errcnt(void *priv) +{ + struct xtmr_manager_dev *xtmr_manager =3D (struct xtmr_manager_dev *)priv; + + xtmr_manager->err_cnt++; +} + +static ssize_t errcnt_show(struct device *dev, struct device_attribute *at= tr, + char *buf) +{ + struct xtmr_manager_dev *xtmr_manager =3D dev_get_drvdata(dev); + + return sprintf(buf, "%x\n", xtmr_manager->err_cnt); +} +static DEVICE_ATTR_RO(errcnt); + +static ssize_t status_show(struct device *dev, struct device_attribute *at= tr, + char *buf) +{ + struct xtmr_manager_dev *xtmr_manager =3D dev_get_drvdata(dev); + size_t ffr; + int len =3D 0; + + ffr =3D xtmr_manager_read(xtmr_manager, XTMR_MANAGER_FFR_OFFSET); + if ((ffr & XTMR_MANAGER_FFR_LM12_MASK) =3D=3D XTMR_MANAGER_FFR_LM12_MASK)= { + len +=3D sprintf(buf + len, + "Lockstep mismatch between processor 1 and 2\n"); + } + + if ((ffr & XTMR_MANAGER_FFR_LM13_MASK) =3D=3D XTMR_MANAGER_FFR_LM13_MASK)= { + len +=3D sprintf(buf + len, + "Lockstep mismatch between processor 1 and 3\n"); + } + + if ((ffr & XTMR_MANAGER_FFR_LM23_MASK) =3D=3D XTMR_MANAGER_FFR_LM23_MASK)= { + len +=3D sprintf(buf + len, + "Lockstep mismatch between processor 2 and 3\n"); + } + + return len; +} +static DEVICE_ATTR_RO(status); + +static ssize_t dis_block_break_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct xtmr_manager_dev *xtmr_manager =3D dev_get_drvdata(dev); + int ret; + long value; + + ret =3D kstrtoul(buf, 16, &value); + if (ret) + return ret; + + if (value > 1) + return -EINVAL; + + xtmr_manager_unblock_break(xtmr_manager); + return size; +} +static DEVICE_ATTR_WO(dis_block_break); + +static struct attribute *xtmr_manager_attrs[] =3D { + &dev_attr_dis_block_break.attr, + &dev_attr_status.attr, + &dev_attr_errcnt.attr, + NULL, +}; +ATTRIBUTE_GROUPS(xtmr_manager); + +static void xtmr_manager_init(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the SEM interrupt mask register to disable the interrupt */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_SEMIMR_OFFSET, 0); + + /* Allow recovery reset by default */ + xtmr_manager->cr_val =3D (1 << XTMR_MANAGER_CR_RIR_SHIFT) | + xtmr_manager->magic1; + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + /* + * Configure Break Delay Initialization Register to zero so that + * break occurs immediately + */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_BDIR_OFFSET, 0); + + /* + * To come out of break handler need to block the break signal + * in the tmr manager, update the xtmr_manager cr_val for the same + */ + xtmr_manager->cr_val |=3D (1 << XTMR_MANAGER_CR_BB_SHIFT); + + /* + * When the break vector gets asserted because of error injection, + * the break signal must be blocked before exiting from the + * break handler, Below api updates the TMR manager address and + * control register and error counter callback arguments, + * which will be used by the break handler to block the + * break and call the callback function. + */ + xmb_manager_register(xtmr_manager->phys_baseaddr, xtmr_manager->cr_val, + xmb_manager_update_errcnt, + xtmr_manager, xmb_manager_reset_handler); +} + +/** + * xtmr_manager_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation and creates sysfs entries for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_manager_probe(struct platform_device *pdev) +{ + struct xtmr_manager_dev *xtmr_manager; + struct resource *res; + int err; + + xtmr_manager =3D devm_kzalloc(&pdev->dev, sizeof(*xtmr_manager), + GFP_KERNEL); + if (!xtmr_manager) + return -ENOMEM; + + xtmr_manager->dev =3D &pdev->dev; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + xtmr_manager->regs =3D devm_ioremap_resource(xtmr_manager->dev, res); + if (IS_ERR(xtmr_manager->regs)) + return PTR_ERR(xtmr_manager->regs); + + xtmr_manager->phys_baseaddr =3D res->start; + + err =3D of_property_read_u32(pdev->dev.of_node, "xlnx,magic1", + &xtmr_manager->magic1); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic1 property"); + return err; + } else if (xtmr_manager->magic1 > XTMR_MANAGER_MAGIC1_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic1 property value"); + return err; + } + + /* Initialize TMR Manager */ + xtmr_manager_init(xtmr_manager); + + err =3D sysfs_create_groups(&xtmr_manager->dev->kobj, + xtmr_manager_groups); + if (err < 0) { + dev_err(&pdev->dev, "unable to create sysfs entries\n"); + return err; + } + + platform_set_drvdata(pdev, xtmr_manager); + + return 0; +} + +static int xtmr_manager_remove(struct platform_device *pdev) +{ + sysfs_remove_groups(&pdev->dev.kobj, xtmr_manager_groups); + + return 0; +} + +static const struct of_device_id xtmr_manager_of_match[] =3D { + { + .compatible =3D "xlnx,tmr-manager-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_manager_of_match); + +static struct platform_driver xtmr_manager_driver =3D { + .driver =3D { + .name =3D "xilinx-tmr_manager", + .of_match_table =3D xtmr_manager_of_match, + }, + .probe =3D xtmr_manager_probe, + .remove =3D xtmr_manager_remove, +}; +module_platform_driver(xtmr_manager_driver); + +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Manager Driver"); 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 05:44:36.9287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cde90a15-a538-4d67-c321-08da58c94976 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[20.83.241.18];Helo=[mailrelay000001.14r1f435wfvunndds3vy4cdalc.xx.internal.cloudapp.net] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SN1NAM02FT0051.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6721 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds documentation for Triple Modular Redundancy (TMR) Inject IP. Signed-off-by: Appana Durga Kedareswara rao --- .../bindings/misc/xlnx,tmr-inject.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-inject.= yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml b/= Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml new file mode 100644 index 000000000000..4daf9539000b --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx TMR Inject Device Tree Bindings + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Inject core provides functional fault + injection by changing selected MicroBlaze instructions, which provides t= he + possibility to verify that the TMR subsystem error detection and fault + recovery logic is working properly. + +properties: + compatible: + enum: + - xlnx,tmr-inject-1.0 + + reg: + maxItems: 1 + + xlnx,magic: + minimum: 0 + maximum: 255 + description: | + Magic number used when injecting faults. The fault inject write data= least + significant byte (bits 7:0) must match this number to have any effec= t. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic + +additionalProperties: false + +examples: + - | + tmr-inject@44a30000 { + compatible =3D "xlnx,tmr-inject-1.0"; + reg =3D <0x44a10000 0x10000>; + xlnx,magic =3D <0x46>; + }; --=20 2.25.1 From nobody Sun Apr 19 18:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D136C43334 for ; Tue, 28 Jun 2022 05:44:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245138AbiF1Fou (ORCPT ); Tue, 28 Jun 2022 01:44:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245111AbiF1Foo (ORCPT ); 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Mon, 27 Jun 2022 22:43:58 -0700 From: Appana Durga Kedareswara rao To: , , , , , , , , , , CC: , Subject: [PATCH 4/4] drivers: misc: Add Support for TMR Inject IP Date: Tue, 28 Jun 2022 11:13:38 +0530 Message-ID: <20220628054338.1631516-5-appana.durga.rao@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220628054338.1631516-1-appana.durga.rao@xilinx.com> References: <20220628054338.1631516-1-appana.durga.rao@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 059f37f4-887e-4015-6155-08da58c94b42 X-MS-TrafficTypeDiagnostic: DM8PR02MB7989:EE_|SN1NAM02FT0047:EE_|MN2PR02MB6208:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: b39ZkRPtbrf13ULM21Vee2YQoAIriTnvdinDxfLwcdRxt1BcU0ZNfpkGQZaG9NWmoHwQB3kUZWwsjNLUzBX54tejMQ3XvEhJvmlCU5aImAoKfvvVxMSEHNhuD9NGWBOtEgOlO0ACX0NnzuzvHFggLP9TEUgTCHrt7iVCb8PsNT4lwA7HOC95mNANnFIqB4gksyyV2H8L0MNh1FjLWdR3DePrQlMtrifDE0RdBj6tzXhmxNKQRIIvZ1933luoLH2Rx69d1tEj56ZHjRzx17i55ezP4mfGrwlEbm4h0yEf33Ya+/Pxdyzqm7NlXnXZ7uvz33fRQrRIh+MBLcQYmOE/BO2LdPnKoIjQ8Qm1m12mM6ZTHk16TXHgvMitCrMnJH4LcRYFSrV7AQuXa2E1tBPlSEzSJcVbVe+9h9V1A5fvUrUskCQP5O8TrFft5LqxgoNTxmkyG/TABhd3C8MFzBKHlR1YJnuCjW/FsBACz7cTruv0+yxOHEQEvxuTsDKeXLnRVxWWVTyy/2/q0bjV1upIxsji6soPlX3MvJb3UBbmoUbM2QYG58p2DwoEDyvSecJOcSBcPT7bIkysdD7Pa9URTSIvfSBlgDXP0Mej1BtCZKHOYX8iKu2J8f1x8X59Z0BOWOx5QPcPUH04iqWZtrJicYojf17pN1t0bkkCJpB61lWazxQzDlfLA3JLKgzlUviTc5MDjgEVPCLLvHKHdaOXqsBGK/APSFV+olvgGwL0UvHCYCGwRN/7sErmJgKap9zMM8eSoMRBjDGCHv5WEN2VdQv452yX+JjTNeIFiEvBYzswdN+SNZ0e7Ae223l0kB5Eo2Al6uE8cNMyXUey6hILOTdGxBe006EoVK1/U49fTQg= X-Forefront-Antispam-Report-Untrusted: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230016)(4636009)(376002)(396003)(136003)(39860400002)(346002)(40470700004)(46966006)(36840700001)(36860700001)(107886003)(2616005)(54906003)(41300700001)(316002)(83380400001)(110136005)(8936002)(336012)(6666004)(478600001)(186003)(47076005)(5660300002)(1076003)(40480700001)(103116003)(70206006)(40460700003)(8676002)(26005)(426003)(7696005)(4326008)(9786002)(70586007)(7636003)(2906002)(82310400005)(921005)(82740400003)(356005)(36756003)(102446001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 05:44:39.9252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 059f37f4-887e-4015-6155-08da58c94b42 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[20.83.241.18];Helo=[mailrelay000000.14r1f435wfvunndds3vy4cdalc.xx.internal.cloudapp.net] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SN1NAM02FT0047.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6208 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Triple Modular Redundancy(TMR) provides functional fault injection by changing selected MicroBlaze instructions, which provides the possibility to verify that the TMR subsystem error detection and fault recovery logic is working properly. This commit adds support for fault injection, provided sysfs entries which allow the user to inject a fault. Usage: echo 1 > /sys/devices/platform/amba_pl/44a30000.tmr_inject/inject_err Signed-off-by: Appana Durga Kedareswara rao --- .../testing/sysfs-driver-xilinx-tmr-inject | 12 ++ MAINTAINERS | 7 + drivers/misc/Kconfig | 10 + drivers/misc/Makefile | 1 + drivers/misc/xilinx_tmr_inject.c | 201 ++++++++++++++++++ 5 files changed, 231 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject create mode 100644 drivers/misc/xilinx_tmr_inject.c diff --git a/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject b/Doc= umentation/ABI/testing/sysfs-driver-xilinx-tmr-inject new file mode 100644 index 000000000000..373a5964cee9 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject @@ -0,0 +1,12 @@ +What: /sys/devices/platform/amba_pl//inject_err +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file allows to inject fault using tmr inject. + This file is write only. + +What: /sys/devices/platform/amba_pl//inject_cpuid +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file allows to configure the CPU identifier + to enable fault injection. + This file is write only. diff --git a/MAINTAINERS b/MAINTAINERS index 3d29109788ed..1446c5aca9e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12969,6 +12969,13 @@ F: Documentation/ABI/testing/sysfs-driver-xilinx-t= mr-manager F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml F: drivers/misc/xilinx_tmr_manager.c =20 +MICROBLAZE TMR INJECT +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject +F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml +F: drivers/misc/xilinx_tmr_inject.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 555ae2e33b91..0989c36f3051 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -493,6 +493,16 @@ config TMR_MANAGER =20 Say N here unless you know what you are doing. =20 +config TMR_INJECT + bool "Select TMR Inject" + depends on TMR_MANAGER + help + This option enables the driver developed for TMR Inject. + The Triple Modular Redundancy(TMR) Inject provides + fault injection. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 28b9803f909b..e9d0a709e207 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -61,3 +61,4 @@ obj-$(CONFIG_HISI_HIKEY_USB) +=3D hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) +=3D hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) +=3D open-dice.o obj-$(CONFIG_TMR_MANAGER) +=3D xilinx_tmr_manager.o +obj-$(CONFIG_TMR_INJECT) +=3D xilinx_tmr_inject.o diff --git a/drivers/misc/xilinx_tmr_inject.c b/drivers/misc/xilinx_tmr_inj= ect.c new file mode 100644 index 000000000000..e458d6d35ae1 --- /dev/null +++ b/drivers/misc/xilinx_tmr_inject.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Xilinx TMR Inject IP. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Description: + * This driver is developed for TMR Inject IP,The Triple Modular Redundanc= y(TMR) + * Inject provides fault injection. + * Fault injection and detection features are provided through sysfs entri= es + * which allow the user to generate a fault. + */ + +#include +#include +#include + +/* TMR Inject Register offsets */ +#define XTMR_INJECT_CR_OFFSET 0x0 +#define XTMR_INJECT_AIR_OFFSET 0x4 +#define XTMR_INJECT_IIR_OFFSET 0xC +#define XTMR_INJECT_EAIR_OFFSET 0x10 +#define XTMR_INJECT_ERR_OFFSET 0x204 + +/* Register Bitmasks/shifts */ +#define XTMR_INJECT_CR_CPUID_SHIFT 8 +#define XTMR_INJECT_CR_IE_SHIFT 10 +#define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16) + +#define XTMR_INJECT_MAGIC_MAX_VAL 255 + +/** + * struct xtmr_inject_dev - Driver data for TMR Inject + * @regs: device physical base address + * @dev: pointer to device struct + * @cr_val: control register value + * @magic: Magic hardware configuration value + * @err_cnt: error statistics count + */ +struct xtmr_inject_dev { + void __iomem *regs; + struct device *dev; + u32 cr_val; + u32 magic; + u32 err_cnt; +}; + +/* IO accessors */ +static inline void xtmr_inject_write(struct xtmr_inject_dev *xtmr_inject, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_inject->regs + addr); +} + +static inline u32 xtmr_inject_read(struct xtmr_inject_dev *xtmr_inject, + u32 addr) +{ + return ioread32(xtmr_inject->regs + addr); +} + +static ssize_t inject_err_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + int ret; + long value; + + ret =3D kstrtoul(buf, 16, &value); + if (ret) + return ret; + + if (value > 1) + return -EINVAL; + + xmb_inject_err(); + + return size; +} +static DEVICE_ATTR_WO(inject_err); + +static ssize_t inject_cpuid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct xtmr_inject_dev *xtmr_inject =3D dev_get_drvdata(dev); + int ret; + long value; + + ret =3D kstrtoul(buf, 0, &value); + if (ret) + return ret; + + if (value > 3) + return -EINVAL; + + xtmr_inject->cr_val |=3D (value << XTMR_INJECT_CR_CPUID_SHIFT); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, + xtmr_inject->cr_val); + + return size; +} +static DEVICE_ATTR_WO(inject_cpuid); + +static struct attribute *xtmr_inject_attrs[] =3D { + &dev_attr_inject_err.attr, + &dev_attr_inject_cpuid.attr, + NULL, +}; +ATTRIBUTE_GROUPS(xtmr_inject); + +static void xtmr_inject_init(struct xtmr_inject_dev *xtmr_inject) +{ + /* Allow fault injection */ + xtmr_inject->cr_val =3D xtmr_inject->magic | + (1 << XTMR_INJECT_CR_IE_SHIFT) | + (1 << XTMR_INJECT_CR_CPUID_SHIFT); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, + xtmr_inject->cr_val); + /* Initialize the address inject and instruction inject registers */ + xtmr_inject_write(xtmr_inject, XTMR_INJECT_AIR_OFFSET, + XMB_INJECT_ERR_OFFSET); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_IIR_OFFSET, + XMB_INJECT_ERR_OFFSET & XTMR_INJECT_IIR_ADDR_MASK); +} + +/** + * xtmr_inject_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation and creates sysfs entries for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_inject_probe(struct platform_device *pdev) +{ + struct xtmr_inject_dev *xtmr_inject; + int err; + + xtmr_inject =3D devm_kzalloc(&pdev->dev, sizeof(*xtmr_inject), + GFP_KERNEL); + if (!xtmr_inject) + return -ENOMEM; + + xtmr_inject->dev =3D &pdev->dev; + + xtmr_inject->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(xtmr_inject->regs)) + return PTR_ERR(xtmr_inject->regs); + + err =3D of_property_read_u32(pdev->dev.of_node, "xlnx,magic", + &xtmr_inject->magic); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic property"); + return err; + } else if (xtmr_inject->magic > XTMR_INJECT_MAGIC_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic property value"); + return err; + } + + /* Initialize TMR Inject */ + xtmr_inject_init(xtmr_inject); + + err =3D sysfs_create_groups(&xtmr_inject->dev->kobj, xtmr_inject_groups); + if (err < 0) { + dev_err(&pdev->dev, "unable to create sysfs entries\n"); + return err; + } + + platform_set_drvdata(pdev, xtmr_inject); + + return 0; +} + +static int xtmr_inject_remove(struct platform_device *pdev) +{ + sysfs_remove_groups(&pdev->dev.kobj, xtmr_inject_groups); + + return 0; +} + +static const struct of_device_id xtmr_inject_of_match[] =3D { + { + .compatible =3D "xlnx,tmr-inject-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_inject_of_match); + +static struct platform_driver xtmr_inject_driver =3D { + .driver =3D { + .name =3D "xilinx-tmr_inject", + .of_match_table =3D xtmr_inject_of_match, + }, + .probe =3D xtmr_inject_probe, + .remove =3D xtmr_inject_remove, +}; +module_platform_driver(xtmr_inject_driver); +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Inject Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1