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(80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id fi9-20020a170906da0900b00722e5b234basm4821607ejb.179.2022.06.27.02.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 02:09:40 -0700 (PDT) From: Emil Renner Berthing To: Eugeniy Paltsev , dmaengine@vger.kernel.org Cc: Emil Renner Berthing , Vinod Koul , Andy Shevchenko , Pandith N , Michael Zhu , linux-kernel@vger.kernel.org, Samin Guo Subject: [PATCH] dmaengine: dw-axi-dmac: Fix RMW on channel suspend register Date: Mon, 27 Jun 2022 11:09:39 +0200 Message-Id: <20220627090939.1775717-1-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Emil Renner Berthing When the DMA is configured for more than 8 channels the bits controlling suspend moves to another register. However when adding support for this the new register would be completely overwritten in one case and overwritten with values from the old register in another case. Found by comparing the parallel implementation of more than 8 channel support for the StarFive JH7100 SoC by Samin. Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8= ") Co-developed-by: Samin Guo Signed-off-by: Samin Guo Signed-off-by: Emil Renner Berthing --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/d= w-axi-dmac/dw-axi-dmac-platform.c index e9c9bcb1f5c2..c741da02b67e 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1164,8 +1164,9 @@ static int dma_chan_pause(struct dma_chan *dchan) BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); } else { - val =3D BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | - BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; + val =3D axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); + val |=3D BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | + BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); } =20 @@ -1190,12 +1191,13 @@ static inline void axi_chan_resume(struct axi_dma_c= han *chan) { u32 val; =20 - val =3D axi_dma_ioread32(chan->chip, DMAC_CHEN); if (chan->chip->dw->hdata->reg_map_8_channels) { + val =3D axi_dma_ioread32(chan->chip, DMAC_CHEN); val &=3D ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); val |=3D (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); } else { + val =3D axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); val &=3D ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); val |=3D (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); --=20 2.36.1