From nobody Sat Sep 21 23:14:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C05E4C43334 for ; Mon, 27 Jun 2022 02:57:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232362AbiF0C47 (ORCPT ); Sun, 26 Jun 2022 22:56:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232261AbiF0C4j (ORCPT ); Sun, 26 Jun 2022 22:56:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F97038BC; Sun, 26 Jun 2022 19:56:37 -0700 (PDT) X-UUID: 1de1e2985a8046d3a44bc94f6141eee0-20220627 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:eb058da5-ced4-4497-9080-4dc291dd55ba,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:d1df9ed8-850a-491d-a127-60d9309b2b3e,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 1de1e2985a8046d3a44bc94f6141eee0-20220627 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1033088880; Mon, 27 Jun 2022 10:56:34 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 27 Jun 2022 10:56:33 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 27 Jun 2022 10:56:32 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 27 Jun 2022 10:56:31 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tzung-Bi Shih , , , CC: , , , , , , Tomasz Figa , , , kyrie wu , Subject: [V10,5/7] mtk-jpegenc: add jpeg encode worker interface Date: Mon, 27 Jun 2022 10:56:23 +0800 Message-ID: <20220627025625.8956-6-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627025625.8956-1-irui.wang@mediatek.com> References: <20220627025625.8956-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: kyrie wu Add jpeg encoding worker to ensure that two HWs run in parallel in MT8195. Signed-off-by: kyrie wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 208 ++++++++++++++++-- .../platform/mediatek/jpeg/mtk_jpeg_core.h | 30 ++- .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 39 +++- 3 files changed, 240 insertions(+), 37 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 0c5c85a112ca..544673a527a0 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -105,10 +105,18 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] =3D= { #define MTK_JPEG_ENC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_enc_formats) #define MTK_JPEG_DEC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_dec_formats) =20 +enum { + MTK_JPEG_BUF_FLAGS_INIT =3D 0, + MTK_JPEG_BUF_FLAGS_LAST_FRAME =3D 1, +}; + struct mtk_jpeg_src_buf { + u32 frame_num; struct vb2_v4l2_buffer b; struct list_head list; struct mtk_jpeg_dec_param dec_param; + + struct mtk_jpeg_ctx *curr_ctx; }; =20 static int debug; @@ -907,38 +915,134 @@ static int mtk_jpeg_set_dec_dst(struct mtk_jpeg_ctx = *ctx, return 0; } =20 -static void mtk_jpeg_enc_device_run(void *priv) +static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx) { - struct mtk_jpeg_ctx *ctx =3D priv; + struct mtk_jpegenc_comp_dev *comp_jpeg; struct mtk_jpeg_dev *jpeg =3D ctx->jpeg; - struct vb2_v4l2_buffer *src_buf, *dst_buf; + unsigned long flags; + int hw_id =3D -1; + int i; + + spin_lock_irqsave(&jpeg->hw_lock, flags); + for (i =3D 0; i < MTK_JPEGENC_HW_MAX; i++) { + comp_jpeg =3D jpeg->enc_hw_dev[i]; + if (comp_jpeg->hw_state =3D=3D MTK_JPEG_HW_IDLE) { + hw_id =3D i; + comp_jpeg->hw_state =3D MTK_JPEG_HW_BUSY; + break; + } + } + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + + return hw_id; +} + +static int mtk_jpegenc_set_hw_param(struct mtk_jpeg_ctx *ctx, + int hw_id, + struct vb2_v4l2_buffer *src_buf, + struct vb2_v4l2_buffer *dst_buf) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D ctx->jpeg->enc_hw_dev[hw_id]; + + jpeg->hw_param.curr_ctx =3D ctx; + jpeg->hw_param.src_buffer =3D src_buf; + jpeg->hw_param.dst_buffer =3D dst_buf; + + return 0; +} + +static int mtk_jpegenc_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id) +{ + unsigned long flags; + + spin_lock_irqsave(&jpeg->hw_lock, flags); + jpeg->enc_hw_dev[hw_id]->hw_state =3D MTK_JPEG_HW_IDLE; + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + + return 0; +} + +static void mtk_jpegenc_worker(struct work_struct *work) +{ + struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; enum vb2_buffer_state buf_state =3D VB2_BUF_STATE_ERROR; + struct mtk_jpeg_src_buf *jpeg_dst_buf; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + int ret, i, hw_id =3D 0; unsigned long flags; - int ret; =20 + struct mtk_jpeg_ctx *ctx =3D container_of(work, + struct mtk_jpeg_ctx, + jpeg_work); + struct mtk_jpeg_dev *jpeg =3D ctx->jpeg; + + for (i =3D 0; i < MTK_JPEGENC_HW_MAX; i++) + comp_jpeg[i] =3D jpeg->enc_hw_dev[i]; + +retry_select: + hw_id =3D mtk_jpegenc_get_hw(ctx); + if (hw_id < 0) { + ret =3D wait_event_interruptible(jpeg->enc_hw_wq, + atomic_read(&jpeg->enchw_rdy) > 0); + if (ret !=3D 0) { + dev_err(jpeg->dev, "%s : %d, all HW are busy\n", + __func__, __LINE__); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + return; + } + + goto retry_select; + } + + atomic_dec(&jpeg->enchw_rdy); src_buf =3D v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + if (!src_buf) + goto getbuf_fail; + dst_buf =3D v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + if (!dst_buf) + goto getbuf_fail; =20 - ret =3D pm_runtime_resume_and_get(jpeg->dev); - if (ret < 0) + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); + + mtk_jpegenc_set_hw_param(ctx, hw_id, src_buf, dst_buf); + ret =3D pm_runtime_get_sync(comp_jpeg[hw_id]->dev); + if (ret < 0) { + dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", + __func__, __LINE__); goto enc_end; + } =20 - schedule_delayed_work(&jpeg->job_timeout_work, - msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); + ret =3D clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk); + if (ret) { + dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", + __func__, __LINE__); + goto enc_end; + } =20 - spin_lock_irqsave(&jpeg->hw_lock, flags); + schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, + msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); =20 - /* - * Resetting the hardware every frame is to ensure that all the - * registers are cleared. This is a hardware requirement. - */ - mtk_jpeg_enc_reset(jpeg->reg_base); + spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); + jpeg_dst_buf =3D mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf); + jpeg_dst_buf->curr_ctx =3D ctx; + jpeg_dst_buf->frame_num =3D ctx->total_frame_num; + ctx->total_frame_num++; + mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); + mtk_jpeg_set_enc_dst(ctx, + comp_jpeg[hw_id]->reg_base, + &dst_buf->vb2_buf); + mtk_jpeg_set_enc_src(ctx, + comp_jpeg[hw_id]->reg_base, + &src_buf->vb2_buf); + mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base); + mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); =20 - mtk_jpeg_set_enc_src(ctx, jpeg->reg_base, &src_buf->vb2_buf); - mtk_jpeg_set_enc_dst(ctx, jpeg->reg_base, &dst_buf->vb2_buf); - mtk_jpeg_set_enc_params(ctx, jpeg->reg_base); - mtk_jpeg_enc_start(jpeg->reg_base); - spin_unlock_irqrestore(&jpeg->hw_lock, flags); return; =20 enc_end: @@ -946,9 +1050,58 @@ static void mtk_jpeg_enc_device_run(void *priv) v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_buf_done(src_buf, buf_state); v4l2_m2m_buf_done(dst_buf, buf_state); +getbuf_fail: + atomic_inc(&jpeg->enchw_rdy); + mtk_jpegenc_put_hw(jpeg, hw_id); v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); } =20 +static void mtk_jpeg_enc_device_run(void *priv) +{ + struct mtk_jpeg_ctx *ctx =3D priv; + struct mtk_jpeg_dev *jpeg =3D ctx->jpeg; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + enum vb2_buffer_state buf_state =3D VB2_BUF_STATE_ERROR; + unsigned long flags; + int ret; + + if (!jpeg->is_jpgenc_multihw) { + src_buf =3D v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst_buf =3D v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + + ret =3D pm_runtime_resume_and_get(jpeg->dev); + if (ret < 0) + goto enc_end; + + schedule_delayed_work(&jpeg->job_timeout_work, + msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); + + spin_lock_irqsave(&jpeg->hw_lock, flags); + + /* + * Resetting the hardware every frame is to ensure that all the + * registers are cleared. This is a hardware requirement. + */ + mtk_jpeg_enc_reset(jpeg->reg_base); + + mtk_jpeg_set_enc_src(ctx, jpeg->reg_base, &src_buf->vb2_buf); + mtk_jpeg_set_enc_dst(ctx, jpeg->reg_base, &dst_buf->vb2_buf); + mtk_jpeg_set_enc_params(ctx, jpeg->reg_base); + mtk_jpeg_enc_start(jpeg->reg_base); + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + return; + +enc_end: + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + } else { + queue_work(jpeg->workqueue, &ctx->jpeg_work); + } +} + static void mtk_jpeg_dec_device_run(void *priv) { struct mtk_jpeg_ctx *ctx =3D priv; @@ -1211,6 +1364,9 @@ static int mtk_jpeg_open(struct file *file) goto free; } =20 + if (jpeg->is_jpgenc_multihw) + INIT_WORK(&ctx->jpeg_work, mtk_jpegenc_worker); + v4l2_fh_init(&ctx->fh, vfd); file->private_data =3D &ctx->fh; v4l2_fh_add(&ctx->fh); @@ -1355,6 +1511,18 @@ static int mtk_jpeg_probe(struct platform_device *pd= ev) dev_err(&pdev->dev, "Failed to init clk\n"); goto err_clk_init; } + } else { + if (of_property_read_bool(pdev->dev.of_node, + "mediatek,jpegenc-multi-core")) { + init_waitqueue_head(&jpeg->enc_hw_wq); + jpeg->workqueue =3D alloc_ordered_workqueue(MTK_JPEG_NAME, + WQ_MEM_RECLAIM + | WQ_FREEZABLE); + if (!jpeg->workqueue) { + ret =3D -EINVAL; + goto err_alloc_workqueue; + } + } } =20 ret =3D v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev); @@ -1423,6 +1591,8 @@ static int mtk_jpeg_probe(struct platform_device *pde= v) =20 err_clk_init: =20 +err_alloc_workqueue: + err_req_irq: =20 return ret; diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.h index 55719bd1b0fb..2fc20c6e06f4 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -75,6 +75,11 @@ struct mtk_jpeg_variant { u32 cap_q_default_fourcc; }; =20 +enum mtk_jpeg_hw_state { + MTK_JPEG_HW_IDLE =3D 0, + MTK_JPEG_HW_BUSY =3D 1, +}; + struct mtk_jpeg_hw_param { struct vb2_v4l2_buffer *src_buffer; struct vb2_v4l2_buffer *dst_buffer; @@ -97,12 +102,17 @@ struct mtk_jpegenc_clk { =20 /** * struct mtk_jpegenc_comp_dev - JPEG COREX abstraction - * @dev: JPEG device - * @plat_dev: platform device data - * @reg_base: JPEG registers mapping - * @master_dev: mtk_jpeg_dev device - * @pm: mtk_jpegenc_pm - * @jpegenc_irq: jpeg encode irq num + * @dev: JPEG device + * @plat_dev: platform device data + * @reg_base: JPEG registers mapping + * @master_dev: mtk_jpeg_dev device + * @venc_clk: mtk_jpegenc_clk + * @jpegenc_irq: jpeg encode irq num + * @job_timeout_work: handle jpeg encode work + * @hw_param: record hw param + * @hw_rdy: record hw ready + * @hw_state: record hw state + * @hw_lock: spinlock protecting the hw device resource */ struct mtk_jpegenc_comp_dev { struct device *dev; @@ -114,6 +124,9 @@ struct mtk_jpegenc_comp_dev { int hw_id; struct delayed_work job_timeout_work; struct mtk_jpeg_hw_param hw_param; + enum mtk_jpeg_hw_state hw_state; + //spinlock protecting the hw device resource + spinlock_t hw_lock; }; =20 /** @@ -146,6 +159,8 @@ struct mtk_jpeg_dev { void __iomem *reg_encbase[MTK_JPEGENC_HW_MAX]; struct mtk_jpegenc_comp_dev *enc_hw_dev[MTK_JPEGENC_HW_MAX]; bool is_jpgenc_multihw; + wait_queue_head_t enc_hw_wq; + atomic_t enchw_rdy; }; =20 /** @@ -204,6 +219,9 @@ struct mtk_jpeg_ctx { u8 enc_quality; u8 restart_interval; struct v4l2_ctrl_handler ctrl_hdl; + + struct work_struct jpeg_work; + u32 total_frame_num; }; =20 #endif /* _MTK_JPEG_CORE_H */ diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index bea62013ce7d..8e1840137c34 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -192,6 +192,7 @@ static void mtk_jpegenc_timeout_work(struct work_struct= *work) container_of(dly_work, struct mtk_jpegenc_comp_dev, job_timeout_work); + struct mtk_jpeg_dev *master_jpeg =3D cjpeg->master_dev; enum vb2_buffer_state buf_state =3D VB2_BUF_STATE_ERROR; struct vb2_v4l2_buffer *src_buf, *dst_buf; =20 @@ -202,6 +203,9 @@ static void mtk_jpegenc_timeout_work(struct work_struct= *work) mtk_jpeg_enc_reset(cjpeg->reg_base); clk_disable_unprepare(cjpeg->venc_clk.clks->clk); pm_runtime_put(cjpeg->dev); + cjpeg->hw_state =3D MTK_JPEG_HW_IDLE; + atomic_inc(&master_jpeg->enchw_rdy); + wake_up(&master_jpeg->enc_hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); } =20 @@ -218,30 +222,37 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq= , void *priv) =20 cancel_delayed_work(&jpeg->job_timeout_work); =20 + ctx =3D jpeg->hw_param.curr_ctx; + src_buf =3D jpeg->hw_param.src_buffer; + dst_buf =3D jpeg->hw_param.dst_buffer; + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); + irq_status =3D readl(jpeg->reg_base + JPEG_ENC_INT_STS) & JPEG_ENC_INT_STATUS_MASK_ALLIRQ; if (irq_status) writel(0, jpeg->reg_base + JPEG_ENC_INT_STS); - if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) - return IRQ_NONE; - - ctx =3D v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev); - if (!ctx) { - v4l2_err(&master_jpeg->v4l2_dev, "Context is NULL\n"); - return IRQ_HANDLED; + if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) { + dev_err(jpeg->dev, " Not JPEG_ENC_INT_STATUS_DONE\n"); + goto irq_handled; } =20 - src_buf =3D v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - dst_buf =3D v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); - result_size =3D mtk_jpeg_enc_get_file_size(jpeg->reg_base); vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); + +irq_handled: buf_state =3D VB2_BUF_STATE_DONE; v4l2_m2m_buf_done(src_buf, buf_state); v4l2_m2m_buf_done(dst_buf, buf_state); - v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx); pm_runtime_put(ctx->jpeg->dev); + clk_disable_unprepare(jpeg->venc_clk.clks->clk); + if (!list_empty(&ctx->fh.m2m_ctx->out_q_ctx.rdy_queue) || + !list_empty(&ctx->fh.m2m_ctx->cap_q_ctx.rdy_queue)) { + queue_work(master_jpeg->workqueue, &ctx->jpeg_work); + } + + jpeg->hw_state =3D MTK_JPEG_HW_IDLE; + wake_up(&master_jpeg->enc_hw_wq); + atomic_inc(&master_jpeg->enchw_rdy); =20 return IRQ_HANDLED; } @@ -294,6 +305,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device= *pdev) dev->plat_dev =3D pdev; dev->dev =3D &pdev->dev; =20 + atomic_set(&master_dev->enchw_rdy, MTK_JPEGENC_HW_MAX); + spin_lock_init(&dev->hw_lock); + dev->hw_state =3D MTK_JPEG_HW_IDLE; + INIT_DELAYED_WORK(&dev->job_timeout_work, mtk_jpegenc_timeout_work); =20 --=20 2.18.0