From nobody Sat Sep 21 23:15:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74416CCA47C for ; Mon, 27 Jun 2022 02:56:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231616AbiF0C4s (ORCPT ); Sun, 26 Jun 2022 22:56:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232245AbiF0C4g (ORCPT ); Sun, 26 Jun 2022 22:56:36 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 475E7558C; Sun, 26 Jun 2022 19:56:34 -0700 (PDT) X-UUID: 3f87205d4d194623bbf47fed095c97a4-20220627 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:3f8ea534-76b3-4408-a62a-f2cb5523edb7,OB:0,LO B:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham, ACTION:release,TS:95 X-CID-INFO: VERSION:1.1.6,REQID:3f8ea534-76b3-4408-a62a-f2cb5523edb7,OB:0,LOB: 10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:95 X-CID-META: VersionHash:b14ad71,CLOUDID:ee10192e-1756-4fa3-be7f-474a6e4be921,C OID:e04d07d52a31,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 3f87205d4d194623bbf47fed095c97a4-20220627 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 109386181; Mon, 27 Jun 2022 10:56:31 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 27 Jun 2022 10:56:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 27 Jun 2022 10:56:30 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 27 Jun 2022 10:56:29 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tzung-Bi Shih , , , CC: , , , , , , Tomasz Figa , , , kyrie wu , Subject: [V10,3/7] mtk-jpegenc: manage jpegenc multi-hardware Date: Mon, 27 Jun 2022 10:56:21 +0800 Message-ID: <20220627025625.8956-4-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627025625.8956-1-irui.wang@mediatek.com> References: <20220627025625.8956-1-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: kyrie wu manage each hardware information, including irq/clk/power. the hardware includes HW0 and HW1. Signed-off-by: kyrie wu --- drivers/media/platform/mediatek/jpeg/Makefile | 11 +- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 77 ++++++--- .../platform/mediatek/jpeg/mtk_jpeg_core.h | 38 +++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 160 ++++++++++++++++++ 4 files changed, 261 insertions(+), 25 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/Makefile b/drivers/media/= platform/mediatek/jpeg/Makefile index 76c33aad0f3f..69703db4b0a5 100644 --- a/drivers/media/platform/mediatek/jpeg/Makefile +++ b/drivers/media/platform/mediatek/jpeg/Makefile @@ -1,6 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -mtk_jpeg-objs :=3D mtk_jpeg_core.o \ +obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) +=3D mtk_jpeg.o \ + mtk-jpeg-enc-hw.o + +mtk_jpeg-y :=3D mtk_jpeg_core.o \ mtk_jpeg_dec_hw.o \ - mtk_jpeg_dec_parse.o \ - mtk_jpeg_enc_hw.o -obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) +=3D mtk_jpeg.o + mtk_jpeg_dec_parse.o + +mtk-jpeg-enc-hw-y :=3D mtk_jpeg_enc_hw.o diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 724fb7aeb0ee..0c5c85a112ca 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -680,7 +680,7 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb) { struct mtk_jpeg_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); struct mtk_jpeg_q_data *q_data =3D NULL; - struct v4l2_plane_pix_format plane_fmt; + struct v4l2_plane_pix_format plane_fmt =3D {}; int i; =20 q_data =3D mtk_jpeg_get_q_data(ctx, vb->vb2_queue->type); @@ -1312,31 +1312,49 @@ static int mtk_jpeg_probe(struct platform_device *p= dev) spin_lock_init(&jpeg->hw_lock); jpeg->dev =3D &pdev->dev; jpeg->variant =3D of_device_get_match_data(jpeg->dev); - INIT_DELAYED_WORK(&jpeg->job_timeout_work, mtk_jpeg_job_timeout_work); =20 - jpeg->reg_base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(jpeg->reg_base)) { - ret =3D PTR_ERR(jpeg->reg_base); - return ret; + if (of_property_read_bool(pdev->dev.of_node, + "mediatek,jpegenc-multi-core")) { + jpeg->is_jpgenc_multihw =3D true; + ret =3D devm_of_platform_populate(&pdev->dev); + if (ret) { + v4l2_err(&jpeg->v4l2_dev, "Master of platform populate failed."); + return -EINVAL; + } } =20 - jpeg_irq =3D platform_get_irq(pdev, 0); - if (jpeg_irq < 0) - return jpeg_irq; + if (!jpeg->is_jpgenc_multihw) { + INIT_DELAYED_WORK(&jpeg->job_timeout_work, + mtk_jpeg_job_timeout_work); =20 - ret =3D devm_request_irq(&pdev->dev, jpeg_irq, - jpeg->variant->irq_handler, 0, pdev->name, jpeg); - if (ret) { - dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n", - jpeg_irq, ret); - goto err_req_irq; - } + jpeg->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(jpeg->reg_base)) { + ret =3D PTR_ERR(jpeg->reg_base); + return ret; + } =20 - ret =3D devm_clk_bulk_get(jpeg->dev, jpeg->variant->num_clks, - jpeg->variant->clks); - if (ret) { - dev_err(&pdev->dev, "Failed to init clk, err %d\n", ret); - goto err_clk_init; + jpeg_irq =3D platform_get_irq(pdev, 0); + if (jpeg_irq < 0) + return jpeg_irq; + + ret =3D devm_request_irq(&pdev->dev, + jpeg_irq, + jpeg->variant->irq_handler, + 0, + pdev->name, jpeg); + if (ret) { + dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n", + jpeg_irq, ret); + goto err_req_irq; + } + + ret =3D devm_clk_bulk_get(jpeg->dev, + jpeg->variant->num_clks, + jpeg->variant->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + goto err_clk_init; + } } =20 ret =3D v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev); @@ -1497,6 +1515,18 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdat= a =3D { .cap_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, }; =20 +static const struct mtk_jpeg_variant mtk8195_jpegenc_drvdata =3D { + .formats =3D mtk_jpeg_enc_formats, + .num_formats =3D MTK_JPEG_ENC_NUM_FORMATS, + .qops =3D &mtk_jpeg_enc_qops, + .m2m_ops =3D &mtk_jpeg_enc_m2m_ops, + .dev_name =3D "mtk-jpeg-enc", + .ioctl_ops =3D &mtk_jpeg_enc_ioctl_ops, + .out_q_default_fourcc =3D V4L2_PIX_FMT_YUYV, + .cap_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, +}; + +#if defined(CONFIG_OF) static const struct of_device_id mtk_jpeg_match[] =3D { { .compatible =3D "mediatek,mt8173-jpgdec", @@ -1510,10 +1540,15 @@ static const struct of_device_id mtk_jpeg_match[] = =3D { .compatible =3D "mediatek,mtk-jpgenc", .data =3D &mtk_jpeg_drvdata, }, + { + .compatible =3D "mediatek,mt8195-jpgenc", + .data =3D &mtk8195_jpegenc_drvdata, + }, {}, }; =20 MODULE_DEVICE_TABLE(of, mtk_jpeg_match); +#endif =20 static struct platform_driver mtk_jpeg_driver =3D { .probe =3D mtk_jpeg_probe, diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.h index 3e4811a41ba2..b743d081d1f5 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -9,6 +9,7 @@ #ifndef _MTK_JPEG_CORE_H #define _MTK_JPEG_CORE_H =20 +#include #include #include #include @@ -74,6 +75,39 @@ struct mtk_jpeg_variant { u32 cap_q_default_fourcc; }; =20 +enum mtk_jpegenc_hw_id { + MTK_JPEGENC_HW0, + MTK_JPEGENC_HW1, + MTK_JPEGENC_HW_MAX, +}; + +/** + * struct mtk_vcodec_clk - Structure used to store vcodec clock information + */ +struct mtk_jpegenc_clk { + struct clk_bulk_data *clks; + int clk_num; +}; + +/** + * struct mtk_jpegenc_comp_dev - JPEG COREX abstraction + * @dev: JPEG device + * @plat_dev: platform device data + * @reg_base: JPEG registers mapping + * @master_dev: mtk_jpeg_dev device + * @pm: mtk_jpegenc_pm + * @jpegenc_irq: jpeg encode irq num + */ +struct mtk_jpegenc_comp_dev { + struct device *dev; + struct platform_device *plat_dev; + void __iomem *reg_base; + struct mtk_jpeg_dev *master_dev; + struct mtk_jpegenc_clk venc_clk; + int jpegenc_irq; + int hw_id; +}; + /** * struct mtk_jpeg_dev - JPEG IP abstraction * @lock: the mutex protecting this structure @@ -100,6 +134,10 @@ struct mtk_jpeg_dev { void __iomem *reg_base; struct delayed_work job_timeout_work; const struct mtk_jpeg_variant *variant; + + void __iomem *reg_encbase[MTK_JPEGENC_HW_MAX]; + struct mtk_jpegenc_comp_dev *enc_hw_dev[MTK_JPEGENC_HW_MAX]; + bool is_jpgenc_multihw; }; =20 /** diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index a2b6e1f85c2d..3d985be960cc 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -5,11 +5,27 @@ * */ =20 +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include =20 +#include "mtk_jpeg_core.h" #include "mtk_jpeg_enc_hw.h" =20 static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] =3D { @@ -30,6 +46,16 @@ static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_qualit= y[] =3D { {.quality_param =3D 97, .hardware_value =3D JPEG_ENC_QUALITY_Q97}, }; =20 +#if defined(CONFIG_OF) +static const struct of_device_id mtk_jpegenc_drv_ids[] =3D { + { + .compatible =3D "mediatek,mt8195-jpgenc-hw", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids); +#endif + void mtk_jpeg_enc_reset(void __iomem *base) { writel(0, base + JPEG_ENC_RSTB); @@ -159,3 +185,137 @@ void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx= , void __iomem *base) } EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_params); =20 +static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) +{ + struct vb2_v4l2_buffer *src_buf, *dst_buf; + enum vb2_buffer_state buf_state; + struct mtk_jpeg_ctx *ctx; + u32 result_size; + u32 irq_status; + + struct mtk_jpegenc_comp_dev *jpeg =3D priv; + struct mtk_jpeg_dev *master_jpeg =3D jpeg->master_dev; + + irq_status =3D readl(jpeg->reg_base + JPEG_ENC_INT_STS) & + JPEG_ENC_INT_STATUS_MASK_ALLIRQ; + if (irq_status) + writel(0, jpeg->reg_base + JPEG_ENC_INT_STS); + if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) + return IRQ_NONE; + + ctx =3D v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev); + if (!ctx) { + v4l2_err(&master_jpeg->v4l2_dev, "Context is NULL\n"); + return IRQ_HANDLED; + } + + src_buf =3D v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + dst_buf =3D v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); + + result_size =3D mtk_jpeg_enc_get_file_size(jpeg->reg_base); + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); + buf_state =3D VB2_BUF_STATE_DONE; + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); + v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx); + pm_runtime_put(ctx->jpeg->dev); + + return IRQ_HANDLED; +} + +static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev) +{ + struct platform_device *pdev =3D dev->plat_dev; + int ret; + + dev->jpegenc_irq =3D platform_get_irq(pdev, 0); + if (dev->jpegenc_irq < 0) { + dev_err(&pdev->dev, "Failed to get irq resource"); + return dev->jpegenc_irq; + } + + ret =3D devm_request_irq(&pdev->dev, + dev->jpegenc_irq, + mtk_jpegenc_hw_irq_handler, + 0, + pdev->name, dev); + if (ret) { + dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)", + dev->jpegenc_irq, ret); + return -ENOENT; + } + + return 0; +} + +static int mtk_jpegenc_hw_probe(struct platform_device *pdev) +{ + struct mtk_jpegenc_clk *jpegenc_clk; + struct mtk_jpeg_dev *master_dev; + struct mtk_jpegenc_comp_dev *dev; + int ret; + + struct device *decs =3D &pdev->dev; + + if (!decs->parent) + return -EPROBE_DEFER; + + master_dev =3D dev_get_drvdata(decs->parent); + if (!master_dev) + return -EPROBE_DEFER; + + dev =3D devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->plat_dev =3D pdev; + dev->dev =3D &pdev->dev; + + jpegenc_clk =3D &dev->venc_clk; + + jpegenc_clk->clk_num =3D devm_clk_bulk_get_all(&pdev->dev, + &jpegenc_clk->clks); + if (jpegenc_clk->clk_num < 0) + return dev_err_probe(&pdev->dev, jpegenc_clk->clk_num, + "Failed to get jpegenc clock count\n"); + + dev->reg_base =3D + devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dev->reg_base)) + return PTR_ERR(dev->reg_base); + + ret =3D mtk_jpegenc_hw_init_irq(dev); + if (ret) + return ret; + + of_property_read_u32(decs->of_node, "hw_id", + &dev->hw_id); + + if (dev->hw_id >=3D 0 || dev->hw_id < MTK_JPEGENC_HW_MAX) { + master_dev->enc_hw_dev[dev->hw_id] =3D dev; + master_dev->reg_encbase[dev->hw_id] =3D dev->reg_base; + dev->master_dev =3D master_dev; + } else { + return dev_err_probe(&pdev->dev, dev->hw_id, + "Invalid hw id\n"); + } + + platform_set_drvdata(pdev, dev); + pm_runtime_enable(&pdev->dev); + + return 0; +} + +struct platform_driver mtk_jpegenc_hw_driver =3D { + .probe =3D mtk_jpegenc_hw_probe, + .driver =3D { + .name =3D "mtk-jpegenc-hw", + .of_match_table =3D of_match_ptr(mtk_jpegenc_drv_ids), + }, +}; + +module_platform_driver(mtk_jpegenc_hw_driver); + +MODULE_DESCRIPTION("MediaTek JPEG encode HW driver"); +MODULE_LICENSE("GPL"); --=20 2.18.0