From nobody Sat Sep 21 23:12:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6551C43334 for ; Fri, 24 Jun 2022 13:37:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232155AbiFXNhV (ORCPT ); Fri, 24 Jun 2022 09:37:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232052AbiFXNhT (ORCPT ); Fri, 24 Jun 2022 09:37:19 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6249F403F6; Fri, 24 Jun 2022 06:37:17 -0700 (PDT) X-UUID: c6c3e81cb5784dd6998d94fe5877c204-20220624 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:64b501b8-03a5-4636-88bc-dad08a044a7c,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:61447ed8-850a-491d-a127-60d9309b2b3e,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: c6c3e81cb5784dd6998d94fe5877c204-20220624 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1802192298; Fri, 24 Jun 2022 21:37:11 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 24 Jun 2022 21:37:09 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 24 Jun 2022 21:37:08 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: Sean Wang , Zhiyong Tao , =?UTF-8?q?N=EDcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , , , , , , , Guodong Liu Subject: [PATCH v2 1/5] pinctrl: mediatek: add generic driving setup property on mt8192 Date: Fri, 24 Jun 2022 21:36:56 +0800 Message-ID: <20220624133700.15487-2-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220624133700.15487-1-guodong.liu@mediatek.com> References: <20220624133700.15487-1-guodong.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1. The dt-binding expects that drive-strength arguments be passed in mA, but the driver was expecting raw values. And that this commit changes the driver so that it is aligned with the binding. 2. This commit provides generic driving setup, which support 2/4/6/8/10/12/14/16mA driving, original driver just set raw data setup setting when use drive-strength property. Signed-off-by: Guodong Liu Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/me= diatek/pinctrl-mt8192.c index acccde9262ba..2421a12fc573 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1372,8 +1372,8 @@ static const struct mtk_pin_soc mt8192_data =3D { .gpio_m =3D 0, .bias_set_combo =3D mtk_pinconf_bias_set_combo, .bias_get_combo =3D mtk_pinconf_bias_get_combo, - .drive_set =3D mtk_pinconf_drive_set_raw, - .drive_get =3D mtk_pinconf_drive_get_raw, + .drive_set =3D mtk_pinconf_drive_set_rev1, + .drive_get =3D mtk_pinconf_drive_get_rev1, .adv_pull_get =3D mtk_pinconf_adv_pull_get, .adv_pull_set =3D mtk_pinconf_adv_pull_set, .adv_drive_get =3D mtk_pinconf_adv_drive_get, --=20 2.25.5 From nobody Sat Sep 21 23:12:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C751CC433EF for ; Fri, 24 Jun 2022 13:37:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232181AbiFXNhY (ORCPT ); Fri, 24 Jun 2022 09:37:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229450AbiFXNhT (ORCPT ); Fri, 24 Jun 2022 09:37:19 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E41E403F9; Fri, 24 Jun 2022 06:37:18 -0700 (PDT) X-UUID: 504d5c95862a46ab9921bb61bf92dafb-20220624 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:3748d154-966a-4337-b329-a32ae962ab03,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham ,ACTION:release,TS:75 X-CID-INFO: VERSION:1.1.6,REQID:3748d154-966a-4337-b329-a32ae962ab03,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:75 X-CID-META: VersionHash:b14ad71,CLOUDID:ed72f82d-1756-4fa3-be7f-474a6e4be921,C OID:268ef7771c0c,Recheck:0,SF:28|17|19|48,TC:nil,Content:1,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 504d5c95862a46ab9921bb61bf92dafb-20220624 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 912113576; Fri, 24 Jun 2022 21:37:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 24 Jun 2022 21:37:13 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 24 Jun 2022 21:37:12 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: Sean Wang , Zhiyong Tao , =?UTF-8?q?N=EDcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , , , , , , , Guodong Liu Subject: [PATCH v2 2/5] pinctrl: mediatek: add drive for I2C related pins on mt8192 Date: Fri, 24 Jun 2022 21:36:57 +0800 Message-ID: <20220624133700.15487-3-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220624133700.15487-1-guodong.liu@mediatek.com> References: <20220624133700.15487-1-guodong.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch provides the advanced drive raw data setting version for I2C used pins on mt8192. Signed-off-by: Guodong Liu Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 96 ++++++----------------- 1 file changed, 26 insertions(+), 70 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/me= diatek/pinctrl-mt8192.c index 2421a12fc573..efabeb422aea 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1259,74 +1259,32 @@ static const struct mtk_pin_field_calc mt8192_pin_r= 1_range[] =3D { PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1), }; =20 -static const struct mtk_pin_field_calc mt8192_pin_e1e0en_range[] =3D { - PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 1), - PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 1), - PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 1), - PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 1), - PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 1), - PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 1), - PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 1), - PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 1), - PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 1), - PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 1), - PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 1), - PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 1), - PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 1), - PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 1), -}; +static const struct mtk_pin_field_calc mt8192_pin_drv_adv_range[] =3D { + PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 0, 5), + PIN_FIELD_BASE(90, 90, 2, 0x0040, 0x10, 5, 5), =20 -static const struct mtk_pin_field_calc mt8192_pin_e0_range[] =3D { - PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 1, 1), - PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 19, 1), - PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 16, 1), - PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 4, 1), - PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 13, 1), - PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 1, 1), - PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 10, 1), - PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 28, 1), - PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 7, 1), - PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 25, 1), - PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 4, 1), - PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 22, 1), - PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 1, 1), - PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 4, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 4, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 10, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 1, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 4, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 1, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 7, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 3), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 3), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 3), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 3), }; =20 -static const struct mtk_pin_field_calc mt8192_pin_e1_range[] =3D { - PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 2, 1), - PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 20, 1), - PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 17, 1), - PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 5, 1), - PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 14, 1), - PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1), - PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 11, 1), - PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 29, 1), - PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 8, 1), - PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 26, 1), - PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 5, 1), - PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 23, 1), - PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 2, 1), - PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 5, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 5, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 11, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 2, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 5, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 2, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 8, 1), -}; =20 =20 static const char * const mt8192_pinctrl_register_base_names[] =3D { @@ -1355,9 +1313,7 @@ static const struct mtk_pin_reg_calc mt8192_reg_cals[= PINCTRL_PIN_REG_MAX] =3D { [PINCTRL_PIN_REG_PUPD] =3D MTK_RANGE(mt8192_pin_pupd_range), [PINCTRL_PIN_REG_R0] =3D MTK_RANGE(mt8192_pin_r0_range), [PINCTRL_PIN_REG_R1] =3D MTK_RANGE(mt8192_pin_r1_range), - [PINCTRL_PIN_REG_DRV_EN] =3D MTK_RANGE(mt8192_pin_e1e0en_range), - [PINCTRL_PIN_REG_DRV_E0] =3D MTK_RANGE(mt8192_pin_e0_range), - [PINCTRL_PIN_REG_DRV_E1] =3D MTK_RANGE(mt8192_pin_e1_range), + [PINCTRL_PIN_REG_DRV_ADV] =3D MTK_RANGE(mt8192_pin_drv_adv_range), }; =20 static const struct mtk_pin_soc mt8192_data =3D { @@ -1376,8 +1332,8 @@ static const struct mtk_pin_soc mt8192_data =3D { .drive_get =3D mtk_pinconf_drive_get_rev1, .adv_pull_get =3D mtk_pinconf_adv_pull_get, .adv_pull_set =3D mtk_pinconf_adv_pull_set, - .adv_drive_get =3D mtk_pinconf_adv_drive_get, - .adv_drive_set =3D mtk_pinconf_adv_drive_set, + .adv_drive_get =3D mtk_pinconf_adv_drive_get_raw, + .adv_drive_set =3D mtk_pinconf_adv_drive_set_raw, }; =20 static const struct of_device_id mt8192_pinctrl_of_match[] =3D { --=20 2.25.5 From nobody Sat Sep 21 23:12:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0CF3CCA480 for ; Fri, 24 Jun 2022 13:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232200AbiFXNh1 (ORCPT ); Fri, 24 Jun 2022 09:37:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232178AbiFXNhY (ORCPT ); Fri, 24 Jun 2022 09:37:24 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB8C440E67; Fri, 24 Jun 2022 06:37:22 -0700 (PDT) X-UUID: 37c0f22834864e579f7ad7224ed81807-20220624 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:ace8b1b8-68ce-40fa-870b-7ab0aa77beec,OB:0,LO B:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.6,REQID:ace8b1b8-68ce-40fa-870b-7ab0aa77beec,OB:0,LOB: 20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:b14ad71,CLOUDID:0373f82d-1756-4fa3-be7f-474a6e4be921,C OID:7978bb9d6098,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 37c0f22834864e579f7ad7224ed81807-20220624 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2057986667; Fri, 24 Jun 2022 21:37:17 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 24 Jun 2022 21:37:15 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 24 Jun 2022 21:37:15 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: Sean Wang , Zhiyong Tao , =?UTF-8?q?N=EDcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , , , , , , , Guodong Liu Subject: [PATCH v2 3/5] pinctrl: mediatek: add rsel setting on mt8192 Date: Fri, 24 Jun 2022 21:36:58 +0800 Message-ID: <20220624133700.15487-4-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220624133700.15487-1-guodong.liu@mediatek.com> References: <20220624133700.15487-1-guodong.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1. I2C pins's resistance value can be controlled by rsel register. This patch provides rsel (resistance selection) setting on mt8192. 2. Also add the missing pull type array for mt8192 to document the pull type of each pin and prevent invalid pull type settings. Signed-off-by: Guodong Liu Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 136 ++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/me= diatek/pinctrl-mt8192.c index efabeb422aea..ffb0b04f0e3c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1285,7 +1285,141 @@ static const struct mtk_pin_field_calc mt8192_pin_d= rv_adv_range[] =3D { PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 3), }; =20 +static const struct mtk_pin_field_calc mt8192_pin_rsel_range[] =3D { + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 2), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 2), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 2), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 2), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 2), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 2), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 2), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 2), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 2), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 2), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 2), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 2), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 2), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 2), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 2), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 2), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 2), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 2), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 2), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 2), +}; =20 +static const unsigned int mt8192_pull_type[] =3D { + MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/ + MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/ + MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/ + MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/ + MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/ + MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/ + MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/ + MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/ + MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/ + MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/ + MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/ + MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/ + MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ + MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ + MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ + MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/ + MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/ + MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/ + MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/ + MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/ + MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PU_PD_TYPE,/*67*/ + MTK_PULL_PU_PD_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100* MTK_PULL_PU_PD_TYPE,/*101*/ + MTK_PULL_PU_PD_TYPE,/*102* MTK_PULL_PU_PD_TYPE,/*103*/ + MTK_PULL_PU_PD_TYPE,/*104* MTK_PULL_PU_PD_TYPE,/*105*/ + MTK_PULL_PU_PD_TYPE,/*106* MTK_PULL_PU_PD_TYPE,/*107*/ + MTK_PULL_PU_PD_TYPE,/*108* MTK_PULL_PU_PD_TYPE,/*109*/ + MTK_PULL_PU_PD_TYPE,/*110* MTK_PULL_PU_PD_TYPE,/*111*/ + MTK_PULL_PU_PD_TYPE,/*112* MTK_PULL_PU_PD_TYPE,/*113*/ + MTK_PULL_PU_PD_TYPE,/*114* MTK_PULL_PU_PD_TYPE,/*115*/ + MTK_PULL_PU_PD_TYPE,/*116* MTK_PULL_PU_PD_TYPE,/*117*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*118*/ MTK_PULL_PU_PD_RSEL_TYPE,/*119*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*120*/ MTK_PULL_PU_PD_RSEL_TYPE,/*121*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*122*/ MTK_PULL_PU_PD_RSEL_TYPE,/*123*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*124*/ MTK_PULL_PU_PD_RSEL_TYPE,/*125*/ + MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_TYPE,/*127*/ + MTK_PULL_PU_PD_TYPE,/*128*/ MTK_PULL_PU_PD_TYPE,/*129*/ + MTK_PULL_PU_PD_TYPE,/*130*/ MTK_PULL_PU_PD_TYPE,/*131*/ + MTK_PULL_PU_PD_TYPE,/*132*/ MTK_PULL_PU_PD_TYPE,/*133*/ + MTK_PULL_PU_PD_TYPE,/*134*/ MTK_PULL_PU_PD_TYPE,/*135*/ + MTK_PULL_PU_PD_TYPE,/*136*/ MTK_PULL_PU_PD_TYPE,/*137*/ + MTK_PULL_PU_PD_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_TYPE,/*143*/ + MTK_PULL_PU_PD_TYPE,/*144*/ MTK_PULL_PU_PD_TYPE,/*145*/ + MTK_PULL_PU_PD_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/ + MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/ + MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/ + MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/ + MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/ + MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/ + MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*160*/ MTK_PULL_PU_PD_RSEL_TYPE,/*161*/ + MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/ + MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/ + MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/ + MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/ + MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/ + MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/ + MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/ + MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/ + MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/ + MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/ + MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PUPD_R1R0_TYPE,/*183*/ + MTK_PULL_PUPD_R1R0_TYPE,/*184*/ MTK_PULL_PUPD_R1R0_TYPE,/*185*/ + MTK_PULL_PUPD_R1R0_TYPE,/*186*/ MTK_PULL_PUPD_R1R0_TYPE,/*187*/ + MTK_PULL_PUPD_R1R0_TYPE,/*188*/ MTK_PULL_PUPD_R1R0_TYPE,/*189*/ + MTK_PULL_PUPD_R1R0_TYPE,/*190*/ MTK_PULL_PUPD_R1R0_TYPE,/*191*/ + MTK_PULL_PUPD_R1R0_TYPE,/*192*/ MTK_PULL_PUPD_R1R0_TYPE,/*193*/ + MTK_PULL_PUPD_R1R0_TYPE,/*194*/ MTK_PULL_PU_PD_TYPE,/*195*/ + MTK_PULL_PU_PD_TYPE,/*196*/ MTK_PULL_PU_PD_TYPE,/*197*/ + MTK_PULL_PU_PD_TYPE,/*198*/ MTK_PULL_PU_PD_TYPE,/*199*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*200*/ MTK_PULL_PU_PD_RSEL_TYPE,/*201*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*202*/ MTK_PULL_PU_PD_RSEL_TYPE,/*203*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*204*/ MTK_PULL_PU_PD_RSEL_TYPE,/*205*/ + MTK_PULL_PU_PD_TYPE,/*206*/ MTK_PULL_PU_PD_TYPE,/*207*/ + MTK_PULL_PU_PD_TYPE,/*208*/ MTK_PULL_PU_PD_TYPE,/*209*/ + MTK_PULL_PU_PD_TYPE,/*210*/ MTK_PULL_PU_PD_TYPE,/*211*/ + MTK_PULL_PU_PD_TYPE,/*212*/ MTK_PULL_PU_PD_TYPE,/*213*/ + MTK_PULL_PU_PD_TYPE,/*214*/ MTK_PULL_PU_PD_TYPE,/*215*/ + MTK_PULL_PU_PD_TYPE,/*216*/ MTK_PULL_PU_PD_TYPE,/*217*/ + MTK_PULL_PU_PD_TYPE,/*218*/ MTK_PULL_PU_PD_TYPE,/*219*/ +}; =20 static const char * const mt8192_pinctrl_register_base_names[] =3D { "iocfg0", "iocfg_rm", "iocfg_bm", "iocfg_bl", "iocfg_br", @@ -1314,6 +1448,7 @@ static const struct mtk_pin_reg_calc mt8192_reg_cals[= PINCTRL_PIN_REG_MAX] =3D { [PINCTRL_PIN_REG_R0] =3D MTK_RANGE(mt8192_pin_r0_range), [PINCTRL_PIN_REG_R1] =3D MTK_RANGE(mt8192_pin_r1_range), [PINCTRL_PIN_REG_DRV_ADV] =3D MTK_RANGE(mt8192_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] =3D MTK_RANGE(mt8192_pin_rsel_range), }; =20 static const struct mtk_pin_soc mt8192_data =3D { @@ -1323,6 +1458,7 @@ static const struct mtk_pin_soc mt8192_data =3D { .ngrps =3D ARRAY_SIZE(mtk_pins_mt8192), .base_names =3D mt8192_pinctrl_register_base_names, .nbase_names =3D ARRAY_SIZE(mt8192_pinctrl_register_base_names), + .pull_type =3D mt8192_pull_type, .eint_hw =3D &mt8192_eint_hw, .nfuncs =3D 8, .gpio_m =3D 0, --=20 2.25.5 From nobody Sat Sep 21 23:12:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 271EEC433EF for ; Fri, 24 Jun 2022 13:37:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232229AbiFXNhg (ORCPT ); Fri, 24 Jun 2022 09:37:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232160AbiFXNh0 (ORCPT ); Fri, 24 Jun 2022 09:37:26 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 299B640E67; Fri, 24 Jun 2022 06:37:25 -0700 (PDT) X-UUID: 2dcfa4be3a324a67bf30dac2097589df-20220624 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:5c2e0c24-e745-45ab-865f-be3130705009,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:b14ad71,CLOUDID:b4447ed8-850a-491d-a127-60d9309b2b3e,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 2dcfa4be3a324a67bf30dac2097589df-20220624 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1088283788; Fri, 24 Jun 2022 21:37:20 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 24 Jun 2022 21:37:18 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 24 Jun 2022 21:37:17 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: Sean Wang , Zhiyong Tao , =?UTF-8?q?N=EDcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , , , , , , , Guodong Liu Subject: [PATCH v2 4/5] pinctrl: mediatek: dropping original advanced drive configuration function Date: Fri, 24 Jun 2022 21:36:59 +0800 Message-ID: <20220624133700.15487-5-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220624133700.15487-1-guodong.liu@mediatek.com> References: <20220624133700.15487-1-guodong.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Function bias_combo getter/setters already handle all cases advanced drive configuration, include drive for I2C related pins. Signed-off-by: Guodong Liu Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/me= diatek/pinctrl-mt8192.c index ffb0b04f0e3c..2fe51fb6b266 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1466,8 +1466,6 @@ static const struct mtk_pin_soc mt8192_data =3D { .bias_get_combo =3D mtk_pinconf_bias_get_combo, .drive_set =3D mtk_pinconf_drive_set_rev1, .drive_get =3D mtk_pinconf_drive_get_rev1, - .adv_pull_get =3D mtk_pinconf_adv_pull_get, - .adv_pull_set =3D mtk_pinconf_adv_pull_set, .adv_drive_get =3D mtk_pinconf_adv_drive_get_raw, .adv_drive_set =3D mtk_pinconf_adv_drive_set_raw, }; --=20 2.25.5 From nobody Sat Sep 21 23:12:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74B48C433EF for ; Fri, 24 Jun 2022 13:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232237AbiFXNhk (ORCPT ); Fri, 24 Jun 2022 09:37:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232210AbiFXNha (ORCPT ); Fri, 24 Jun 2022 09:37:30 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27EC343492; Fri, 24 Jun 2022 06:37:28 -0700 (PDT) X-UUID: 019c11712cf4428cb453bb914a167bd9-20220624 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:e7639bda-7295-4f12-a4bf-28cd6bf0a628,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.6,REQID:e7639bda-7295-4f12-a4bf-28cd6bf0a628,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:b14ad71,CLOUDID:4273f82d-1756-4fa3-be7f-474a6e4be921,C OID:2f488628baa7,Recheck:0,SF:28|17|19|48,TC:nil,Content:1,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 019c11712cf4428cb453bb914a167bd9-20220624 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 883618693; Fri, 24 Jun 2022 21:37:22 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 24 Jun 2022 21:37:21 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 24 Jun 2022 21:37:20 +0800 From: Guodong Liu To: Linus Walleij , Rob Herring , Matthias Brugger , Sean Wang CC: Sean Wang , Zhiyong Tao , =?UTF-8?q?N=EDcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , , , , , , , Guodong Liu Subject: [PATCH v2 5/5] pinctrl: mediatek: fix the pinconf definition of some GPIO pins Date: Fri, 24 Jun 2022 21:37:00 +0800 Message-ID: <20220624133700.15487-6-guodong.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220624133700.15487-1-guodong.liu@mediatek.com> References: <20220624133700.15487-1-guodong.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove pin definitions that do not support the R0 & R1 pinconfig property. Signed-off-by: Guodong Liu Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado --- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 60 ----------------------- 1 file changed, 60 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/me= diatek/pinctrl-mt8192.c index 2fe51fb6b266..a66394c6f443 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1107,24 +1107,10 @@ static const struct mtk_pin_field_calc mt8192_pin_p= upd_range[] =3D { PIN_FIELD_BASE(54, 54, 1, 0x0060, 0x10, 2, 1), PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 4, 1), PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 3, 1), - PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 31, 1), - PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 31, 1), PIN_FIELD_BASE(152, 152, 7, 0x0090, 0x10, 3, 1), PIN_FIELD_BASE(153, 153, 7, 0x0090, 0x10, 2, 1), PIN_FIELD_BASE(154, 154, 7, 0x0090, 0x10, 0, 1), PIN_FIELD_BASE(155, 155, 7, 0x0090, 0x10, 1, 1), - PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 31, 1), - PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 31, 1), PIN_FIELD_BASE(183, 183, 9, 0x0030, 0x10, 1, 1), PIN_FIELD_BASE(184, 184, 9, 0x0030, 0x10, 2, 1), PIN_FIELD_BASE(185, 185, 9, 0x0030, 0x10, 4, 1), @@ -1137,12 +1123,6 @@ static const struct mtk_pin_field_calc mt8192_pin_pu= pd_range[] =3D { PIN_FIELD_BASE(192, 192, 9, 0x0030, 0x10, 0, 1), PIN_FIELD_BASE(193, 193, 9, 0x0030, 0x10, 5, 1), PIN_FIELD_BASE(194, 194, 9, 0x0030, 0x10, 11, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 31, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 31, 1), }; =20 static const struct mtk_pin_field_calc mt8192_pin_r0_range[] =3D { @@ -1164,24 +1144,10 @@ static const struct mtk_pin_field_calc mt8192_pin_r= 0_range[] =3D { PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 2, 1), PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 4, 1), PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 3, 1), - PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 1), - PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 1), - PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 1), - PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 1), - PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 1), - PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 1), - PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 1), - PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 1), - PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 1), - PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 1), - PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 1), - PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 1), PIN_FIELD_BASE(152, 152, 7, 0x00c0, 0x10, 3, 1), PIN_FIELD_BASE(153, 153, 7, 0x00c0, 0x10, 2, 1), PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 0, 1), PIN_FIELD_BASE(155, 155, 7, 0x00c0, 0x10, 1, 1), - PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 1), - PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 1), PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 1, 1), PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 2, 1), PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 4, 1), @@ -1194,12 +1160,6 @@ static const struct mtk_pin_field_calc mt8192_pin_r0= _range[] =3D { PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 0, 1), PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 5, 1), PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 11, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 1), }; =20 static const struct mtk_pin_field_calc mt8192_pin_r1_range[] =3D { @@ -1221,24 +1181,10 @@ static const struct mtk_pin_field_calc mt8192_pin_r= 1_range[] =3D { PIN_FIELD_BASE(54, 54, 1, 0x0090, 0x10, 2, 1), PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 4, 1), PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 3, 1), - PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 1, 1), - PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 13, 1), - PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 11, 1), - PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 23, 1), - PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 9, 1), - PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 21, 1), - PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 7, 1), - PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 19, 1), - PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 5, 1), - PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 17, 1), - PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 3, 1), - PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 15, 1), PIN_FIELD_BASE(152, 152, 7, 0x00d0, 0x10, 3, 1), PIN_FIELD_BASE(153, 153, 7, 0x00d0, 0x10, 2, 1), PIN_FIELD_BASE(154, 154, 7, 0x00d0, 0x10, 0, 1), PIN_FIELD_BASE(155, 155, 7, 0x00d0, 0x10, 1, 1), - PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 1, 1), - PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 3, 1), PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 1, 1), PIN_FIELD_BASE(184, 184, 9, 0x0050, 0x10, 2, 1), PIN_FIELD_BASE(185, 185, 9, 0x0050, 0x10, 4, 1), @@ -1251,12 +1197,6 @@ static const struct mtk_pin_field_calc mt8192_pin_r1= _range[] =3D { PIN_FIELD_BASE(192, 192, 9, 0x0050, 0x10, 0, 1), PIN_FIELD_BASE(193, 193, 9, 0x0050, 0x10, 5, 1), PIN_FIELD_BASE(194, 194, 9, 0x0050, 0x10, 11, 1), - PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 3, 1), - PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 7, 1), - PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 1, 1), - PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 3, 1), - PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 1, 1), - PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1), }; =20 static const struct mtk_pin_field_calc mt8192_pin_drv_adv_range[] =3D { --=20 2.25.5