From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91B58C433EF for ; Thu, 23 Jun 2022 21:13:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229936AbiFWVNe (ORCPT ); Thu, 23 Jun 2022 17:13:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229850AbiFWVNa (ORCPT ); Thu, 23 Jun 2022 17:13:30 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28BB8506E0 for ; Thu, 23 Jun 2022 14:13:29 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id n1so477390wrg.12 for ; Thu, 23 Jun 2022 14:13:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oky3YgKKfNXCQVslFZi4xoyuek1RvMVadIY0VBZTguA=; b=Gi4aZN2sLBYp2ljUDPgzuGmqSQQkoBx224Y9NdkkPudfprFuvJKpVNzxTerjz+W79c uJemVZrRHa337z29pIJwA4xKfXYxK/FLUqZgHJDI8UJbCs8rTNxdrYm8kG5EPlDUjqSa 43uaEfEpNdjOi0mZBsh8k2Rh6jNuIburDRnqUiLSV/PzvSeIzYQHbMFFQV5n80bGfP1I ErLxO1Z4qXB5v6Pb91rXN5PavcL6BZT14uO0WgOTcxfgoE05tfD3TaeDcGNsNw16gm5g /Svj0Js2kguzTPIXpp/nuLnvSqZ7CJmSwBdKQyjEj46vSmwSZIpA96aJvuWvabOIML5W XnPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oky3YgKKfNXCQVslFZi4xoyuek1RvMVadIY0VBZTguA=; b=VEr61VA5g41B+/muu6oQRsC8PcihU4if6NpQr4r8B4g1neHdWN2VAFNFUWut0LKiqT aFlHY8W8unxqQQ43A5wFmnI2JmFbGSXaYiqbJny2PTJNs+kyOokFIqfx7IOgp10O+Fxw aGR6YWOSk0CsGC2pZICxjrl9BTFUFqDBKe2d4AkUTlHz82fybHrkx4aaWLUBX7LCAQ19 Qdt4HjemMaARNs8xMnQqHn7/acJUubUGZ2ilWxg1qpt0q6O8eu6hnnMH/SB8ZB/4jDWb KBF01gsyJmTR0fLJcxVI0n0lrPWEWyhKID68BEwSFtePDvrtWz3fErIe5UpbVmIwp413 irGw== X-Gm-Message-State: AJIora/o6Bub77cj55IY9wwbBTXVMYPNPI+nztz7BkVAPzn0hv9KRJ8z JrDTWQhKWits0Elalbs7JRMh8xBkj2I= X-Google-Smtp-Source: AGRyM1u74I3yclz1slGC+ZAtAzuCAsg8Kp437l9Kw7u2Pwp5GeLMxdxqWb94DNFdZ+yBfuNRbG5x9Q== X-Received: by 2002:a05:6000:192:b0:21a:3c91:df05 with SMTP id p18-20020a056000019200b0021a3c91df05mr10206433wrx.655.1656018807701; Thu, 23 Jun 2022 14:13:27 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id v15-20020a5d43cf000000b0021badf3cb26sm498689wrr.63.2022.06.23.14.13.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:27 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/12] regmap-irq: Convert bool bitfields to unsigned int Date: Thu, 23 Jun 2022 22:14:09 +0100 Message-Id: <20220623211420.918875-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use 'unsigned int' for bitfields for consistency with most other kernel code. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 2 +- include/linux/regmap.h | 26 +++++++++++++------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index a6db605707b0..a58b29e9c7c7 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -43,7 +43,7 @@ struct regmap_irq_chip_data { unsigned int irq_reg_stride; unsigned int type_reg_stride; =20 - bool clear_status:1; + unsigned int clear_status:1; }; =20 static int sub_irq_reg(struct regmap_irq_chip_data *data, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 8952fa3d0d59..7c5e4a20e9cf 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1518,19 +1518,19 @@ struct regmap_irq_chip { unsigned int type_base; unsigned int *virt_reg_base; unsigned int irq_reg_stride; - bool mask_writeonly:1; - bool init_ack_masked:1; - bool mask_invert:1; - bool use_ack:1; - bool ack_invert:1; - bool clear_ack:1; - bool wake_invert:1; - bool runtime_pm:1; - bool type_invert:1; - bool type_in_mask:1; - bool clear_on_unmask:1; - bool not_fixed_stride:1; - bool status_invert:1; + unsigned int mask_writeonly:1; + unsigned int init_ack_masked:1; + unsigned int mask_invert:1; + unsigned int use_ack:1; + unsigned int ack_invert:1; + unsigned int clear_ack:1; + unsigned int wake_invert:1; + unsigned int runtime_pm:1; + unsigned int type_invert:1; + unsigned int type_in_mask:1; + unsigned int clear_on_unmask:1; + unsigned int not_fixed_stride:1; + unsigned int status_invert:1; =20 int num_regs; =20 --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24251C433EF for ; Thu, 23 Jun 2022 21:13:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229901AbiFWVNh (ORCPT ); Thu, 23 Jun 2022 17:13:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbiFWVNb (ORCPT ); Thu, 23 Jun 2022 17:13:31 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B255F506DB for ; Thu, 23 Jun 2022 14:13:30 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id s1so493155wra.9 for ; Thu, 23 Jun 2022 14:13:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1j/DIF/Fnv8RPcb6VzAvPxanMn+C+wmq9yB73HToH5Q=; b=MRkzlNJ6E7f7MsWd8tjufz+IN8bN9Gu64Hs8WWp8eQvKuAZzORqec28MAjjHoGWV8d ystjzntlOsSgckx/re43dmwR1khxqCIlOD2P01rOamRvzYHU+X40XcpGGoq3XCzrse91 hwRQDelZWmsI7AEusxCUNl3WK8ke7MnXkfeRGF9SzBZEwKaa8LJdEic/MvUjOonYVfsx ojA2b1/2AUTFEnWn0H8Zi9VX4WnX3TbcO3lkcPvgBLNQxqKzqHuuE0rQMckKBY0LicPm vBurKPahZijnxOP5KruOrpwc5Xy/Ut+EZO2hMf7OHCywbHlrCPjTGyHyIcMl4/s0KagL 1e8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1j/DIF/Fnv8RPcb6VzAvPxanMn+C+wmq9yB73HToH5Q=; b=acqyjp7d8QO7ENX7fH//2wz7Y1SUlaD7YiFXrM5vgsZNFXelNL/UkAqIY79uPu/s6Y 856DSAoZWk/RcGe9//PjKbd0mx/86P9yGCC8CaGNYjKsTRTSgevF+fAVo1hY4AQQdwcI 9oihq7dvplhIa9F6sxWjbuw+EZMcW2Cbb7L8ZQ0EMaooLO9roJIb2YwBYrM/SqL//8n0 xt95y4j7dQgVF1GA5gwoZnUzqx5t0zPvqzAZd4mGpPii1CeVZ5rDSjeG0p0s8IeTPiwA PjNY6iiSrCDfZ0pgE6QrCrJyCFviSyZ91eqLUHhALK3D3hZWNtAEEKZjLMxGKdRa9mCu 2D9g== X-Gm-Message-State: AJIora+hYyRSNQ7IpOJ5vsOBytXUDgXGyfiiGNFXl12PT5xXyU1T97su BZahsZ5uCt4IyATxBDSMjL8= X-Google-Smtp-Source: AGRyM1uzR/LHMsuFGT4K5Q38BYjn0O+T5c3D1I/X4JlnrKKqsw5B6YopRiqGEK7YhtwkaXbCHU9hRQ== X-Received: by 2002:a5d:4352:0:b0:213:4910:6616 with SMTP id u18-20020a5d4352000000b0021349106616mr10053266wrr.226.1656018809319; Thu, 23 Jun 2022 14:13:29 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id e20-20020a5d5954000000b0020fcaba73bcsm388885wri.104.2022.06.23.14.13.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:28 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/12] regmap-irq: Remove unused type_reg_stride field Date: Thu, 23 Jun 2022 22:14:10 +0100 Message-Id: <20220623211420.918875-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It appears that no chip ever required a nonzero type_reg_stride and commit 1066cfbdfa3f ("regmap-irq: Extend sub-irq to support non-fixed reg strides") broke support. Just remove the field. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 6 ------ include/linux/regmap.h | 3 --- 2 files changed, 9 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index a58b29e9c7c7..475a959e2b8b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -41,7 +41,6 @@ struct regmap_irq_chip_data { unsigned int **virt_buf; =20 unsigned int irq_reg_stride; - unsigned int type_reg_stride; =20 unsigned int clear_status:1; }; @@ -743,11 +742,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *f= wnode, else d->irq_reg_stride =3D 1; =20 - if (chip->type_reg_stride) - d->type_reg_stride =3D chip->type_reg_stride; - else - d->type_reg_stride =3D 1; - if (!map->use_single_read && map->reg_stride =3D=3D 1 && d->irq_reg_stride =3D=3D 1) { d->status_reg_buf =3D kmalloc_array(chip->num_regs, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 7c5e4a20e9cf..f75911239977 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1487,8 +1487,6 @@ struct regmap_irq_sub_irq_map { * @num_type_reg: Number of type registers. * @num_virt_regs: Number of non-standard irq configuration registers. * If zero unsupported. - * @type_reg_stride: Stride to use for chips where type registers are not - * contiguous. * @handle_pre_irq: Driver specific callback to handle interrupt from dev= ice * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from dev= ice @@ -1539,7 +1537,6 @@ struct regmap_irq_chip { =20 int num_type_reg; int num_virt_regs; - unsigned int type_reg_stride; =20 int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFFAEC43334 for ; Thu, 23 Jun 2022 21:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229887AbiFWVNl (ORCPT ); Thu, 23 Jun 2022 17:13:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229929AbiFWVNc (ORCPT ); Thu, 23 Jun 2022 17:13:32 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5731F506E0 for ; Thu, 23 Jun 2022 14:13:31 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id r20so547593wra.1 for ; Thu, 23 Jun 2022 14:13:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7iiZ1g2foyg+pIBZL+lLC+0n9kDHXAVzLQyCSVfDJ08=; b=g4Grn3YmGC1+IcwN8QObevjbd44d+989zZV+3JaTY0xt8f1ITTyHLY15SH3o3Pclfo jYDv4Vr7GOSZ05ufB0Br/B8EHSblAJr/fkGVc72codtkMdE1zq9PJbCd6sodW2TQSLum osZmiOCWEG6jhR3R0gbVnM4Izz2BwSG0aFlC+jqlPGEbGTFX/8j6HmecQ5jEumqbInp8 sKZV22XFx1wYMMOAZMGgs+U351HVh/hct3l5X6lwd8hD8vS2MF+O2WY+nfspmYPLTxy7 TD5hml3FtevOv1YsGFALikrAqkz1NrpKtR1VCfoejqakoB6HkBwfMAlJVNRI/aA36gXf 9kLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7iiZ1g2foyg+pIBZL+lLC+0n9kDHXAVzLQyCSVfDJ08=; b=R+wTkg3D3gz5jPhO5voJBfuDgKwps2faq89fn1nhTN4EFO0J7QMlO0rIiGf3ggIGNW IWOOgBXn/t9LdFlHtzz9bdXmALs+qb3dcjvPqxhIUglgvCyaiUg30lrzgNk7msSQNgwJ Qps8TvThstsnloAhNdMtpYxjKoSKW7NLTQDrn8TzTqixi4u9wFIl30wuBPFH7nGwY67O +H26egCI2w5/H9Z3zXQ2aUZ+GvAMoyb3/H2C/rf3OYW/8N05b26RS2jyjgxsdWUnQKPP jpU2KBY6NmUJn+yFrI9bSqhkgnJCc1DuvRSwg06niGw4KMtQ/29syvBPTLR1S8Nb6c/l aQ/Q== X-Gm-Message-State: AJIora/gOOMo0Drcs1Mg0HFxc3gxOHDTF1upXvgPEQx3M1kLxCOKimSR Ljn7bJLWctvzCR9v5N3yCeY= X-Google-Smtp-Source: AGRyM1vHoi5qUwVQ7GRAfiQIs4odq2EG3Vef2E3QjtfiIxAnIND7243E1l5CFaj1TE5wf764TtYLEA== X-Received: by 2002:adf:fa52:0:b0:21b:910d:cddd with SMTP id y18-20020adffa52000000b0021b910dcdddmr10192030wrr.291.1656018810933; Thu, 23 Jun 2022 14:13:30 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id ay26-20020a5d6f1a000000b0021baf5e590dsm412186wrb.71.2022.06.23.14.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:30 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/12] regmap-irq: Cleanup sizeof(...) use in memory allocation Date: Thu, 23 Jun 2022 22:14:11 +0100 Message-Id: <20220623211420.918875-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of mentioning unsigned int directly, use a sizeof(...) involving the buffer we're allocating to ensure the types don't get out of sync. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index 475a959e2b8b..dca27b4e29d3 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -670,30 +670,30 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *= fwnode, =20 if (chip->num_main_regs) { d->main_status_buf =3D kcalloc(chip->num_main_regs, - sizeof(unsigned int), + sizeof(*d->main_status_buf), GFP_KERNEL); =20 if (!d->main_status_buf) goto err_alloc; } =20 - d->status_buf =3D kcalloc(chip->num_regs, sizeof(unsigned int), + d->status_buf =3D kcalloc(chip->num_regs, sizeof(*d->status_buf), GFP_KERNEL); if (!d->status_buf) goto err_alloc; =20 - d->mask_buf =3D kcalloc(chip->num_regs, sizeof(unsigned int), + d->mask_buf =3D kcalloc(chip->num_regs, sizeof(*d->mask_buf), GFP_KERNEL); if (!d->mask_buf) goto err_alloc; =20 - d->mask_buf_def =3D kcalloc(chip->num_regs, sizeof(unsigned int), + d->mask_buf_def =3D kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), GFP_KERNEL); if (!d->mask_buf_def) goto err_alloc; =20 if (chip->wake_base) { - d->wake_buf =3D kcalloc(chip->num_regs, sizeof(unsigned int), + d->wake_buf =3D kcalloc(chip->num_regs, sizeof(*d->wake_buf), GFP_KERNEL); if (!d->wake_buf) goto err_alloc; @@ -702,11 +702,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *= fwnode, num_type_reg =3D chip->type_in_mask ? chip->num_regs : chip->num_type_reg; if (num_type_reg) { d->type_buf_def =3D kcalloc(num_type_reg, - sizeof(unsigned int), GFP_KERNEL); + sizeof(*d->type_buf_def), GFP_KERNEL); if (!d->type_buf_def) goto err_alloc; =20 - d->type_buf =3D kcalloc(num_type_reg, sizeof(unsigned int), + d->type_buf =3D kcalloc(num_type_reg, sizeof(*d->type_buf), GFP_KERNEL); if (!d->type_buf) goto err_alloc; @@ -723,7 +723,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, =20 for (i =3D 0; i < chip->num_virt_regs; i++) { d->virt_buf[i] =3D kcalloc(chip->num_regs, - sizeof(unsigned int), + sizeof(**d->virt_buf), GFP_KERNEL); if (!d->virt_buf[i]) goto err_alloc; --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D275C43334 for ; Thu, 23 Jun 2022 21:13:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229750AbiFWVNp (ORCPT ); Thu, 23 Jun 2022 17:13:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229950AbiFWVNf (ORCPT ); Thu, 23 Jun 2022 17:13:35 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07E7250B03 for ; Thu, 23 Jun 2022 14:13:34 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id m32-20020a05600c3b2000b0039756bb41f2so414652wms.3 for ; Thu, 23 Jun 2022 14:13:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VqID5x/tjmobIccvt6tf2g3gXW+2/FDTRjd9KrrHqF4=; b=WNeouhwZYUPPBBHO7307nHyxJ9XH1mT1cVB692WnpZFRrcCViR+9OjwGR1fSISBDcQ +fjtJBH9ryQ+z2qB4OcWcqQIYjitMM8UJxXY+nrOdy6WJn2926X1UDKizIRC+95k/Biy Y1VXgNSdvLxJB0uBNTQxKs40JCLW0s7hD5I+pzd1trSYYUEOR7X+iTX6/bxESJnn9tGh n/FwgloopEhy+vs3HaF35yipXR5BG6lCgJI60DNHb/hKcu3/jPxSmBpIx6QF8jK1W90f +O3Ush+nI0EG+72TNMo7H9Y/fI0SPCSkgW0kZLDK7pian6wFJTAkaQAKB/k0gl1Hiix6 lL8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VqID5x/tjmobIccvt6tf2g3gXW+2/FDTRjd9KrrHqF4=; b=fELqrhtrXMCqiclXJzuXuEAjWALoOV+jU3VsBHPAV8PSStDzeRRgO7kZ9mEk9Fp8Kp YxjItsYexLwvuJIyKTWsKkEtXaP6WiY6/fy8WHTd3wR5ffaV2Z6kSnaRBTNEbzmZ04I2 fp5TWH1JElE8NZxYxaqH0azTjYLEOaR1e2nM+eWEbMDPepbXTJfcMmi9qmUXlTjL4hnz +0w1ofevhSOODaJ2XMitnxyypm5QdZZH+JLqoGUTzPeHKac6qZIOjAwDidF8Bp8gxxWr YFfn5f7JxREn3wZVlvOrZggoc9RuntF+NjXBhzvlW087ZKuNU2iemu7UWuCO3HPLxI67 RP9Q== X-Gm-Message-State: AJIora+cFj1nQDTMwYIFVNejWw042C0OCWJVziavkysgU1yWaFyV8j2+ SULu2qgDdBKS/QoUn7EvSjk= X-Google-Smtp-Source: AGRyM1u0qTmDVNQgQjlHVSFDyEpSORhptzldhUSlvugxOT3R2t6PvpxsdIF5N2CbS35e9NDQJEYHGw== X-Received: by 2002:a05:600c:19c9:b0:39c:72fc:9530 with SMTP id u9-20020a05600c19c900b0039c72fc9530mr6292709wmq.88.1656018812622; Thu, 23 Jun 2022 14:13:32 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id j3-20020adfe503000000b0021b8a0d680esm400194wrm.86.2022.06.23.14.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:32 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/12] regmap-irq: Remove an unnecessary restriction on type_in_mask Date: Thu, 23 Jun 2022 22:14:12 +0100 Message-Id: <20220623211420.918875-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Check types_supported instead of checking type_rising/falling_val when using type_in_mask interrupts. This makes the intent clearer and allows a type_in_mask irq to support level or edge triggers, rather than only edge triggers. Update the documentation and comments to reflect the new behavior. This shouldn't affect existing drivers, because if they didn't set types_supported properly the type buffer wouldn't be updated. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 19 ++++++++----------- include/linux/regmap.h | 8 +++++--- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index dca27b4e29d3..fd7c4315d16b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -252,22 +252,19 @@ static void regmap_irq_enable(struct irq_data *data) struct regmap *map =3D d->map; const struct regmap_irq *irq_data =3D irq_to_regmap_irq(d, data->hwirq); unsigned int reg =3D irq_data->reg_offset / map->reg_stride; - unsigned int mask, type; - - type =3D irq_data->type.type_falling_val | irq_data->type.type_rising_val; + unsigned int mask; =20 /* * The type_in_mask flag means that the underlying hardware uses - * separate mask bits for rising and falling edge interrupts, but - * we want to make them into a single virtual interrupt with - * configurable edge. + * separate mask bits for each interrupt trigger type, but we want + * to have a single logical interrupt with a configurable type. * - * If the interrupt we're enabling defines the falling or rising - * masks then instead of using the regular mask bits for this - * interrupt, use the value previously written to the type buffer - * at the corresponding offset in regmap_irq_set_type(). + * If the interrupt we're enabling defines any supported types + * then instead of using the regular mask bits for this interrupt, + * use the value previously written to the type buffer at the + * corresponding offset in regmap_irq_set_type(). */ - if (d->chip->type_in_mask && type) + if (d->chip->type_in_mask && irq_data->type.types_supported) mask =3D d->type_buf[reg] & irq_data->mask; else mask =3D irq_data->mask; diff --git a/include/linux/regmap.h b/include/linux/regmap.h index f75911239977..106ca1172d3d 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1468,9 +1468,11 @@ struct regmap_irq_sub_irq_map { * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. * @wake_invert: Inverted wake register: cleared bits are wake enabled. * @type_invert: Invert the type flags. - * @type_in_mask: Use the mask registers for controlling irq type. For - * interrupts defining type_rising/falling_mask use mask_ba= se - * for edge configuration and never update bits in type_bas= e. + * @type_in_mask: Use the mask registers for controlling irq type. Use thi= s if + * the hardware provides separate bits for rising/falling edge + * or low/high level interrupts and they should be combined into + * a single logical interrupt. Use &struct regmap_irq_type data + * to define the mask bit for each irq type. * @clear_on_unmask: For chips with interrupts cleared on read: read the s= tatus * registers before unmasking interrupts to clear any bi= ts * set when they were masked. --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19A5FC433EF for ; Thu, 23 Jun 2022 21:13:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230120AbiFWVNr (ORCPT ); Thu, 23 Jun 2022 17:13:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbiFWVNi (ORCPT ); Thu, 23 Jun 2022 17:13:38 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E31E5130D for ; Thu, 23 Jun 2022 14:13:35 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id i67-20020a1c3b46000000b003a03567d5e9so593489wma.1 for ; Thu, 23 Jun 2022 14:13:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+qGHCihlNL7T5T1G7aMDu8MmDKY14zb9oDODHpK/qzo=; b=S1xehfFKO5ilpkywkeqlpTy+vnCc2lcbAhOiTJQSxZ3d/gTT/HgbPo2UWfbSSoVwTS DneIJA/68lETzir+R8relctPzs/1FJY//sJ84eG1WUkngGwjE5TUzt0qHAkcmismR+ZR 91Ckvg8o4L2dVdrp+0IwKVuhSIAPcFT+PZUs1HYm3qHK0QF91ZRXMtJRod94Kz+HuHRY vRnBZGPXsVpX2L/sRWxb5oEhuueZ3keqOhrqj91YuFwvj3S7X22zBSkvVirK91TaAvfv Rk5lJGRiYNandi43Grk/gRA7cUaT7SUaMFsvZ51nQm3xhHlCrMYHXRG3fIaUaFo69/jZ uDIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+qGHCihlNL7T5T1G7aMDu8MmDKY14zb9oDODHpK/qzo=; b=anqCRdnL4u1v79YD3AGneAEfwotiljfUTvqj6vBOKwXvk9eOlzGYpqQt4p/xBOnKFl Gerl5fi/KNCYESUkfQHnB/Oy0pHhRu8HspUyxAA4lpr8RxD4mpI56dOUIYU0WZZ9zWRm BkQROt3JmL0P0A9Q++7n762twJh0pNyiqIm1Sf+CpLLyz6yzQ8hVVEz9ISRca6XagBA9 6tXFXHmnVwrM14fXj1ge5ty1DgiVk4vqOtgjJRH7Grr5YJqFXzBKDHdP7g1X1TFF7PiE 7PP22/j1GpGxE3kGkJD81N80hzBhC3wW/tMG6ZRFE37wo4ULtzQgmvcfizNrtsX1G+Wy 61RA== X-Gm-Message-State: AJIora9Qemmpf9onDkA+70lTAc+c//X8ShDW85cUO9sy33gUftONQUKV kPLpWppadRZr848lGswwP+0= X-Google-Smtp-Source: AGRyM1s96y5jbOAruKIBOzv3fj3rhEH6KOs8iL9c93S8NUrIz/RFOi+AdNow2XwwmJ4ztQ3QS/BTSw== X-Received: by 2002:a05:600c:35d2:b0:39c:8490:abbf with SMTP id r18-20020a05600c35d200b0039c8490abbfmr6439848wmq.86.1656018814254; Thu, 23 Jun 2022 14:13:34 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id 10-20020a05600c26ca00b003973b9d0447sm5070837wmv.36.2022.06.23.14.13.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:33 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/12] regmap-irq: Remove inappropriate uses of regmap_irq_update_bits() Date: Thu, 23 Jun 2022 22:14:13 +0100 Message-Id: <20220623211420.918875-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" regmap_irq_update_bits() is misnamed and should only be used for updating mask registers, since it checks the mask_writeonly flag. However, it was also used for updating wake and type registers. It's safe to replace these uses with regmap_update_bits() because there are no users of the mask_writeonly flag. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index fd7c4315d16b..cb20ce6f91e7 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -158,11 +158,11 @@ static void regmap_irq_sync_unlock(struct irq_data *d= ata) reg =3D sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->wake_buf[i]); else - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret !=3D 0) @@ -205,10 +205,10 @@ static void regmap_irq_sync_unlock(struct irq_data *d= ata) continue; reg =3D sub_irq_reg(d, d->chip->type_base, i); if (d->chip->type_invert) - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->type_buf_def[i], ~d->type_buf[i]); else - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->type_buf_def[i], d->type_buf[i]); if (ret !=3D 0) dev_err(d->map->dev, "Failed to sync type in %x\n", @@ -825,11 +825,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *= fwnode, reg =3D sub_irq_reg(d, d->chip->wake_base, i); =20 if (chip->wake_invert) - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], 0); else - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret !=3D 0) { --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B039BC433EF for ; Thu, 23 Jun 2022 21:13:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230167AbiFWVNx (ORCPT ); Thu, 23 Jun 2022 17:13:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230019AbiFWVNi (ORCPT ); Thu, 23 Jun 2022 17:13:38 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34FD651311 for ; Thu, 23 Jun 2022 14:13:36 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id m32-20020a05600c3b2000b0039756bb41f2so414652wms.3 for ; Thu, 23 Jun 2022 14:13:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEQIwlQTc4kPghW2wNEhgQMVH2n26SLzg8zoPvmRxGU=; b=D1K7AwVK5TzTFfifp7CxhpuosId2pz3TPE1ZZ5GjzjzlaYwwMu6UaDllJsKTSokYNE IdbUYwhhq29gNPT6scTGB1QQaSQxFN2z+qgT/M+InuNGKNB7sKg8u45zxgFCxs0B4gS/ OVixmcVH7c3lS18imyMnV/bTRjEpkBhSJ7PLjpT14WSqto+CUht00ql7xs1LVeMdXpTp dTparxaP5J0EjxhxFR8MBkhIKfbu+Uw6t2hZzdbCqMlODOaLukFBY49FWEJPAOZyj2TZ Xu4W0Y3p4c+cyPKzlwLkHwQnO9KJR7Wxwk/9XlTWbmrKHg57R1y5fQ6eqA02m3rG6pop Ru/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEQIwlQTc4kPghW2wNEhgQMVH2n26SLzg8zoPvmRxGU=; b=W26WtVt2FuaIccWKm+ragnPcJyb89vT6/E3eue884WBWgK+BqIJD+OE6JQyUQEBey2 uSFpZbj1Iv+g9UktEx4keXMnJWhH156dQI7DX/UxUHFTgrVC4gxEiJbzl/UnJ2Vl9kat xq4rs3ejfFCZle1TUgGpDRKiuktvmCi2cUcmY2098F6Bt3D68kR8UaCryXW9g8orHGoD mt1qbf0Z3Iv9LwgyHAzH0sg6B/38cXmA2zAKbAtGP8cVBwSppB2qfrPCk5qLE+ncAK3+ dBBLR0IOj37rQb4rE2zyxKJlkfk0FUMlTfwvPnQSj1OOB6tAWlvbXDmuwoX/FAeTnR6A 5sYA== X-Gm-Message-State: AJIora9CoQnttpLudADwV9Kzi0dBsP26hGBJICCXRbsULlsYqPrb6Ebz rQy8N0PqPDS8bRLzBlXp9nI= X-Google-Smtp-Source: AGRyM1sKGmoNY+PQxGWT9xM1gV+pQC1cyP1FizJFGFljm7mH2aH9KPanBjdo9sFor6Huy2jdSvUn9A== X-Received: by 2002:a05:600c:1c24:b0:39c:6530:2a60 with SMTP id j36-20020a05600c1c2400b0039c65302a60mr6311706wms.78.1656018815833; Thu, 23 Jun 2022 14:13:35 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id a3-20020a056000100300b0021b943a50b3sm399654wrx.85.2022.06.23.14.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:35 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/12] regmap-irq: Remove mask_writeonly and regmap_irq_update_bits() Date: Thu, 23 Jun 2022 22:14:14 +0100 Message-Id: <20220623211420.918875-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit a71411dbf6c8 ("regmap: irq: add chip option mask_writeonly") introduced the mask_writeonly option, but it isn't used now and it appears it's never been used by any in-tree drivers. The motivation for the option is mentioned in the commit message, Some irq controllers have writeonly/multipurpose register layouts. In those cases we read invalid data back. [...] The option causes mask register updates to use regmap_write_bits() instead of regmap_update_bits(). However, regmap_write_bits() doesn't solve the reading invalid data problem. It's still a read-modify-write op like regmap_update_bits(). The difference is that 'update bits' will only write the new value if it is different from the current value, while 'write bits' will write the new value unconditionally, even if it's the same as the current value. This seems like a bit of a specialized use case and probably isn't that useful for regmap-irq, so let's just remove the option and go back to using an 'update bits' op for the mask registers. We can always add the option back if some driver ends up needing it in the future. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 24 +++++++----------------- include/linux/regmap.h | 2 -- 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index cb20ce6f91e7..7e93dd8af56b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -80,16 +80,6 @@ static void regmap_irq_lock(struct irq_data *data) mutex_lock(&d->lock); } =20 -static int regmap_irq_update_bits(struct regmap_irq_chip_data *d, - unsigned int reg, unsigned int mask, - unsigned int val) -{ - if (d->chip->mask_writeonly) - return regmap_write_bits(d->map, reg, mask, val); - else - return regmap_update_bits(d->map, reg, mask, val); -} - static void regmap_irq_sync_unlock(struct irq_data *data) { struct regmap_irq_chip_data *d =3D irq_data_get_irq_chip_data(data); @@ -130,11 +120,11 @@ static void regmap_irq_sync_unlock(struct irq_data *d= ata) =20 reg =3D sub_irq_reg(d, d->chip->mask_base, i); if (d->chip->mask_invert) { - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); } else if (d->chip->unmask_base) { /* set mask with mask_base register */ - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret < 0) dev_err(d->map->dev, @@ -143,12 +133,12 @@ static void regmap_irq_sync_unlock(struct irq_data *d= ata) unmask_offset =3D d->chip->unmask_base - d->chip->mask_base; /* clear mask with unmask_base register */ - ret =3D regmap_irq_update_bits(d, + ret =3D regmap_update_bits(d->map, reg + unmask_offset, d->mask_buf_def[i], d->mask_buf[i]); } else { - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->mask_buf[i]); } if (ret !=3D 0) @@ -763,17 +753,17 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *= fwnode, reg =3D sub_irq_reg(d, d->chip->mask_base, i); =20 if (chip->mask_invert) - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { unmask_offset =3D d->chip->unmask_base - d->chip->mask_base; - ret =3D regmap_irq_update_bits(d, + ret =3D regmap_update_bits(d->map, reg + unmask_offset, d->mask_buf[i], d->mask_buf[i]); } else - ret =3D regmap_irq_update_bits(d, reg, + ret =3D regmap_update_bits(d->map, reg, d->mask_buf[i], d->mask_buf[i]); if (ret !=3D 0) { dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 106ca1172d3d..d21eb8ad2675 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1452,7 +1452,6 @@ struct regmap_irq_sub_irq_map { * * @status_base: Base status register address. * @mask_base: Base mask register address. - * @mask_writeonly: Base mask register is write only. * @unmask_base: Base unmask register address. for chips who have * separate mask and unmask registers * @ack_base: Base ack address. If zero then the chip is clear on read. @@ -1518,7 +1517,6 @@ struct regmap_irq_chip { unsigned int type_base; unsigned int *virt_reg_base; unsigned int irq_reg_stride; - unsigned int mask_writeonly:1; unsigned int init_ack_masked:1; unsigned int mask_invert:1; unsigned int use_ack:1; --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A38FDC433EF for ; Thu, 23 Jun 2022 21:14:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230177AbiFWVN7 (ORCPT ); Thu, 23 Jun 2022 17:13:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbiFWVNk (ORCPT ); Thu, 23 Jun 2022 17:13:40 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FF2B5133C for ; Thu, 23 Jun 2022 14:13:39 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id l126-20020a1c2584000000b0039c1a10507fso427106wml.1 for ; Thu, 23 Jun 2022 14:13:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yGdqQ4oAuggJEmpNM1D1Sw+hLvuTVREq9oE+Alw71tA=; b=UakyC0v/Hrh2824Aqybuwxif2gEioO2b7Sf1r9Na9QA+QN7/5sfsN3t2M3YT46lZrH cC3mdOfG4n8TjHp596Czsytxl3HwwaZAySClyl+6ZD4Z0gaXNAhN56arW1GjqN94fKt5 jpydmLF80JbtuA1Q9q6T6iNEQwq5YUaOLERY7r9FgjY0g1L6eprVBnBb0b0W/q/gnlkC k+bmfLbl8mPt7dkgmvuTJk9HOurCkED0c2j0DGrFnV4CduAo3xwvPK+3pDWK8dg0kQWR xTjGoq1nhxwOK5wXV5vPegb+G3RK95a0lDL9pHD1q4ogc0N2KOkcjkY1PS1u+bGerkKo 0XfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yGdqQ4oAuggJEmpNM1D1Sw+hLvuTVREq9oE+Alw71tA=; b=fqJuuTPozUPM6HaJd4OHXpenTuSqiqNhJGdRyyf+XW9F0OqYOgZkqGwOD5Lx60nLHv dAJzFcF8O3wQ3+Mw7rbTpTPgyMzmUuhMYF39opOcT6ljmf2IxBJGC/DKap17ucH5VIZW aTIuJIxrbt+jmOicBeiXmHYdwAt5ibmDmfTil5VqndgdZ2qglbMeRubehzCZYreamKAq Zkq6DTyBeS/7xLXH3x/X1D2Dacv3bmHqFcwaOi2OhLV2c9+Znye7ttCZ08nVmeRovUWb XXzj1igrahu5Fj1kDfNujLoyleWQaiSqEgYYpU+6jFriMCiGOJpnOq/r3fScrA+Ja+8l JZVA== X-Gm-Message-State: AJIora9bfIBqAjFj7SjYuaIFv2lJrHwqwHHmueWEfS/cMoBSimUXnVmh DUEpvDB/aDw9I4jSlFE2Ffg= X-Google-Smtp-Source: AGRyM1tIhQE9Sjr3YNubI5e68iAaqJex/k2T0jRFnMVJDWS166kL60cHijoh/PbTHpTAMCe0R4Q2nw== X-Received: by 2002:a05:600c:247:b0:39c:8088:68fe with SMTP id 7-20020a05600c024700b0039c808868femr6343596wmj.162.1656018817496; Thu, 23 Jun 2022 14:13:37 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id 10-20020a05600c26ca00b003973b9d0447sm5070980wmv.36.2022.06.23.14.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:37 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/12] regmap-irq: Refactor checks for status bulk read support Date: Thu, 23 Jun 2022 22:14:15 +0100 Message-Id: <20220623211420.918875-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are several conditions that must be satisfied to support bulk read of status registers. Move the check into a function to avoid duplicating it in two places. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index 7e93dd8af56b..5f9a5856c45e 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -73,6 +73,14 @@ struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_c= hip_data *data, return &data->chip->irqs[irq]; } =20 +static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *d= ata) +{ + struct regmap *map =3D data->map; + + return data->irq_reg_stride =3D=3D 1 && map->reg_stride =3D=3D 1 && + !map->use_single_read; +} + static void regmap_irq_lock(struct irq_data *data) { struct regmap_irq_chip_data *d =3D irq_data_get_irq_chip_data(data); @@ -467,8 +475,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } =20 } - } else if (!map->use_single_read && map->reg_stride =3D=3D 1 && - data->irq_reg_stride =3D=3D 1) { + } else if (regmap_irq_can_bulk_read_status(data)) { =20 u8 *buf8 =3D data->status_reg_buf; u16 *buf16 =3D data->status_reg_buf; @@ -729,8 +736,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, else d->irq_reg_stride =3D 1; =20 - if (!map->use_single_read && map->reg_stride =3D=3D 1 && - d->irq_reg_stride =3D=3D 1) { + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf =3D kmalloc_array(chip->num_regs, map->format.val_bytes, GFP_KERNEL); --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED387C433EF for ; Thu, 23 Jun 2022 21:14:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230144AbiFWVOC (ORCPT ); Thu, 23 Jun 2022 17:14:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230026AbiFWVNl (ORCPT ); Thu, 23 Jun 2022 17:13:41 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B71E051310 for ; Thu, 23 Jun 2022 14:13:40 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id m1so542041wrb.2 for ; Thu, 23 Jun 2022 14:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pFicCXDe5rb79PhZKoaZ8t2q32vOWXf1ocVF975OVTs=; b=bz3W2eW4ow4FraSLDvoD8TxAt3V1s+cOxxbEl5XanYbi0yPQ95jBgJMyPcIOPVYfWT L1UI8wcyeVIjrUw9XTsZDxgeQsn1/6WEO69ajLqP801NJfSj3ufjeC7xRmblVL2sggdF AJluDa/3NjkEr0g6tJDIUUS1EROB1tp9JH4wj3A2pC1g+AcxV2t1/XcuCphMCx0isFUe QHgzhpNh/8rYSH/o/wL19oO0Kg8hZpG5zAoEFdDOOqVcbS20iBMYa8qIGa9DtDbDrwxd 3PIc89K+NVTuUkj5911jxKv0EULDlAKjluQjhxiIoJJeaHvUhzDQWSa/m17coDEruUAa T2pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pFicCXDe5rb79PhZKoaZ8t2q32vOWXf1ocVF975OVTs=; b=7lMxr14PAu9pV8CUeFlZ6bTApeyTnnD4LCj9CWZTPQAio7zmBuqCW6FIBW9QYUyqsQ Ex49miZaBvguVgjJHOrPthfZAhMUmBJFvwYbGQz4nQWyWhWrzPeKPzh57+CGenFeJSdX 5gaD2u+UUQtkxKpIgjyc2G3RTlaGyHfwsOb55x8rqRrymzbds0ix2N1y5CK+y2/92sve LrSOYgM2L3sTkby5fKRzcWnciTrld2Wfug10Vw+pQbd1FFvXeW0X3xOx7S+lt5dSvz7E d2uuqAKxSg4dC9sYsQ4A+7bZpS/KKO53pWFS9cBpNNibS741hfPi/yRNvb6xtcNpVnZa ghlg== X-Gm-Message-State: AJIora963XyMvDqOmULAHF1eBDzJeIBBUDIKPAbmBESfUcPiLjCIxwpj v6gaJ22H0Q6HmhWI/4GmpHk= X-Google-Smtp-Source: AGRyM1voHJkzFyYajsOuikNeOsCZERztTnrtJAFi5sQVnWu2o8J/amkEKkzuO6mDeF3aNMhZJdr3pg== X-Received: by 2002:a5d:452d:0:b0:21b:81f6:d91 with SMTP id j13-20020a5d452d000000b0021b81f60d91mr9855146wra.521.1656018819218; Thu, 23 Jun 2022 14:13:39 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id j14-20020adfa54e000000b0021b93b29cacsm468757wrb.99.2022.06.23.14.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:38 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/12] regmap-irq: Introduce config registers for irq types Date: Thu, 23 Jun 2022 22:14:16 +0100 Message-Id: <20220623211420.918875-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Config registers provide a more uniform approach to handling irq type registers. They are essentially an extension of the virtual registers used by the qcom-pm8008 driver. Config registers can be represented as a 2D array: config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 There are 'num_config_bases' base registers, each of which is used to address 'num_config_regs' registers. The addresses are calculated in the same way as for other bases. It is assumed that an irq's type is controlled by one column of registers; that column is identified by the irq's 'type_reg_offset'. The set_type_config() callback is responsible for updating the config register contents. It receives an array of buffers (each represents a row of registers) and the index of the column to update, along with the 'struct regmap_irq' description and requested irq type. Buffered values are written to registers in regmap_irq_sync_unlock(). Note that the entire register contents are overwritten, which is a minor change in behavior from type registers via 'type_base'. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 115 +++++++++++++++++++++++++++++-- include/linux/regmap.h | 12 ++++ 2 files changed, 122 insertions(+), 5 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index 5f9a5856c45e..e3dbf55a561f 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -39,6 +39,7 @@ struct regmap_irq_chip_data { unsigned int *type_buf; unsigned int *type_buf_def; unsigned int **virt_buf; + unsigned int **config_buf; =20 unsigned int irq_reg_stride; =20 @@ -228,6 +229,17 @@ static void regmap_irq_sync_unlock(struct irq_data *da= ta) } } =20 + for (i =3D 0; i < d->chip->num_config_bases; i++) { + for (j =3D 0; j < d->chip->num_config_regs; j++) { + reg =3D sub_irq_reg(d, d->chip->config_base[i], j); + ret =3D regmap_write(map, reg, d->config_buf[i][j]); + if (ret) + dev_err(d->map->dev, + "Failed to write config %x: %d\n", + reg, ret); + } + } + if (d->chip->runtime_pm) pm_runtime_put(map->dev); =20 @@ -287,7 +299,7 @@ static int regmap_irq_set_type(struct irq_data *data, u= nsigned int type) struct regmap_irq_chip_data *d =3D irq_data_get_irq_chip_data(data); struct regmap *map =3D d->map; const struct regmap_irq *irq_data =3D irq_to_regmap_irq(d, data->hwirq); - int reg; + int reg, ret; const struct regmap_irq_type *t =3D &irq_data->type; =20 if ((t->types_supported & type) !=3D type) @@ -327,9 +339,19 @@ static int regmap_irq_set_type(struct irq_data *data, = unsigned int type) return -EINVAL; } =20 - if (d->chip->set_type_virt) - return d->chip->set_type_virt(d->virt_buf, type, data->hwirq, - reg); + if (d->chip->set_type_virt) { + ret =3D d->chip->set_type_virt(d->virt_buf, type, data->hwirq, + reg); + if (ret) + return ret; + } + + if (d->chip->set_type_config) { + ret =3D d->chip->set_type_config(d->config_buf, type, + irq_data, reg); + if (ret) + return ret; + } =20 return 0; } @@ -599,6 +621,61 @@ static const struct irq_domain_ops regmap_domain_ops = =3D { .xlate =3D irq_domain_xlate_onetwocell, }; =20 +/** + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration cal= lback. + * @buf: Buffer containing configuration register values, this is a 2D arr= ay of + * `num_config_bases` rows, each of `num_config_regs` elements. + * @type: The requested IRQ type. + * @irq_data: The IRQ being configured. + * @idx: Index of the irq's config registers within each array `buf[i]` + * + * This is a &struct regmap_irq_chip->set_type_config callback suitable for + * chips with one config register. Register values are updated according to + * the &struct regmap_irq_type data associated with an IRQ. + */ +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int typ= e, + const struct regmap_irq *irq_data, int idx) +{ + const struct regmap_irq_type *t =3D &irq_data->type; + + if (t->type_reg_mask) + buf[0][idx] &=3D ~t->type_reg_mask; + else + buf[0][idx] &=3D ~(t->type_falling_val | + t->type_rising_val | + t->type_level_low_val | + t->type_level_high_val); + + switch (type) { + case IRQ_TYPE_EDGE_FALLING: + buf[0][idx] |=3D t->type_falling_val; + break; + + case IRQ_TYPE_EDGE_RISING: + buf[0][idx] |=3D t->type_rising_val; + break; + + case IRQ_TYPE_EDGE_BOTH: + buf[0][idx] |=3D (t->type_falling_val | + t->type_rising_val); + break; + + case IRQ_TYPE_LEVEL_HIGH: + buf[0][idx] |=3D t->type_level_high_val; + break; + + case IRQ_TYPE_LEVEL_LOW: + buf[0][idx] |=3D t->type_level_low_val; + break; + + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple); + /** * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handl= ing * @@ -724,6 +801,24 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *f= wnode, } } =20 + if (chip->num_config_bases && chip->num_config_regs) { + /* + * Create config_buf[num_config_bases][num_config_regs] + */ + d->config_buf =3D kcalloc(chip->num_config_bases, + sizeof(*d->config_buf), GFP_KERNEL); + if (!d->config_buf) + goto err_alloc; + + for (i =3D 0; i < chip->num_config_regs; i++) { + d->config_buf[i] =3D kcalloc(chip->num_config_regs, + sizeof(**d->config_buf), + GFP_KERNEL); + if (!d->config_buf[i]) + goto err_alloc; + } + } + d->irq_chip =3D regmap_irq_chip; d->irq_chip.name =3D chip->name; d->irq =3D irq; @@ -894,6 +989,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *f= wnode, kfree(d->virt_buf[i]); kfree(d->virt_buf); } + if (d->config_buf) { + for (i =3D 0; i < chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); return ret; } @@ -934,7 +1034,7 @@ EXPORT_SYMBOL_GPL(regmap_add_irq_chip); void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) { unsigned int virq; - int hwirq; + int i, hwirq; =20 if (!d) return; @@ -964,6 +1064,11 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_c= hip_data *d) kfree(d->mask_buf); kfree(d->status_reg_buf); kfree(d->status_buf); + if (d->config_buf) { + for (i =3D 0; i < d->chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); } EXPORT_SYMBOL_GPL(regmap_del_irq_chip); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index d21eb8ad2675..432449f318cb 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1459,6 +1459,7 @@ struct regmap_irq_sub_irq_map { * @wake_base: Base address for wake enables. If zero unsupported. * @type_base: Base address for irq type. If zero unsupported. * @virt_reg_base: Base addresses for extra config regs. + * @config_base: Base address for IRQ type config regs. If null unsupporte= d. * @irq_reg_stride: Stride to use for chips where registers are not conti= guous. * @init_ack_masked: Ack all masked interrupts once during initalization. * @mask_invert: Inverted mask register: cleared bits are masked out. @@ -1488,12 +1489,15 @@ struct regmap_irq_sub_irq_map { * @num_type_reg: Number of type registers. * @num_virt_regs: Number of non-standard irq configuration registers. * If zero unsupported. + * @num_config_bases: Number of config base registers. + * @num_config_regs: Number of config registers for each config base regis= ter. * @handle_pre_irq: Driver specific callback to handle interrupt from dev= ice * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from dev= ice * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_typ= e() * and configure virt regs. + * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter= when * driver specific pre/post interrupt handler is called. * @@ -1516,6 +1520,7 @@ struct regmap_irq_chip { unsigned int wake_base; unsigned int type_base; unsigned int *virt_reg_base; + const unsigned int *config_base; unsigned int irq_reg_stride; unsigned int init_ack_masked:1; unsigned int mask_invert:1; @@ -1537,16 +1542,23 @@ struct regmap_irq_chip { =20 int num_type_reg; int num_virt_regs; + int num_config_bases; + int num_config_regs; =20 int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); int (*set_type_virt)(unsigned int **buf, unsigned int type, unsigned long hwirq, int reg); + int (*set_type_config)(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); void *irq_drv_data; }; =20 struct regmap_irq_chip_data; =20 +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int typ= e, + const struct regmap_irq *irq_data, int idx); + int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, int irq_base, const struct regmap_irq_chip *chip, struct regmap_irq_chip_data **data); --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58EDAC433EF for ; Thu, 23 Jun 2022 21:14:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230111AbiFWVOG (ORCPT ); Thu, 23 Jun 2022 17:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230071AbiFWVNm (ORCPT ); Thu, 23 Jun 2022 17:13:42 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FEDB5131D for ; Thu, 23 Jun 2022 14:13:41 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id i67-20020a1c3b46000000b003a03567d5e9so593489wma.1 for ; Thu, 23 Jun 2022 14:13:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nXcllgLFQkv+OtgQlnqQLrSG+8U6QBobVbJQIfbLeDc=; b=Koz/reU77bu0VvbgzNl5NYw466Hvlq+xJzo7e9i6p+Ltpv9ptGfhVMICdtRtcXzIfP 2ivQSbaBGxkP1GpTxevwBJHstbh84GFj0ov2HyPTH07JcwEm5qSdfs2hYnjNJ2+m/i8j yr0U6VoocnfO91cJhusyD5j75Pb+6FDiT/WCOXFoW63pig6Hjb44QrVnQaOeZxd24Tnc AMzeXLumoOPR5UO0v5SnlUZ+yTZRZWwKU2CIcq9tnRzZr7Os0LVgEd9xSwux8v9DsI0S VIxwm5H996Rtaza0+spjVvpEhIZGu9aCl9d7ZJH1N1LTxTSmoFMeSuAimEXFgTv28L0M hqBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nXcllgLFQkv+OtgQlnqQLrSG+8U6QBobVbJQIfbLeDc=; b=Gj6KiPEoKGIXjR8nJh27sW7UG4v7LSbmTKTzBy1/hhuIcaN3fcphQ7eDI3eOKZYgVf r1TP2cYcFSM+eI68IN5zA9SrHvmWWGnHcpZUxrlXO3lHyFmCxofifTz5bEtb6zqjJerH O0IcaOetwZAbinBkofA4IhWki2CN4sW3D325mh9qvZ/KWOw3Z7yQt/tIbQgvn5hpreNG 2nFAFQDVkz9/9teKwFwmniSJzZGgQ4z0aFmvfR0S0E31riKglZDRyIA+nwfwvWypelmE kn+UZQiQ9W2R9JXyJhV6xFEDy2AMCQXHmPcp/YTM86EsO0lVItpR+uAGvdKByiEUjh7h fBtA== X-Gm-Message-State: AJIora/AetGYtwyfN5baRpqko1jJAxR86yszg3Sk1ozlBwMytputoHr4 M4jlZvJ6o4o6s785x00ySaw= X-Google-Smtp-Source: AGRyM1v/B9pfRAAPsksMMQl0bhgtMcCRDcWfQiF0kCvTypfnviL3jOLOIPlrV/Qx5mbGGedlWM7+cg== X-Received: by 2002:a1c:f310:0:b0:39c:605f:1dba with SMTP id q16-20020a1cf310000000b0039c605f1dbamr6293798wmq.43.1656018820755; Thu, 23 Jun 2022 14:13:40 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id m17-20020a05600c3b1100b0039c5497deccsm6117087wms.1.2022.06.23.14.13.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:40 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/12] regmap-irq: Deprecate type registers and virtual registers Date: Thu, 23 Jun 2022 22:14:17 +0100 Message-Id: <20220623211420.918875-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Config registers can be used to replace both type and virtual registers, so mark both features are deprecated and issue a warning if they're used. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 6 ++++++ include/linux/regmap.h | 18 ++++++++++++------ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index e3dbf55a561f..8cbc62c3d638 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -726,6 +726,12 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *f= wnode, return -EINVAL; } =20 + if (chip->num_type_reg) + dev_warn(map->dev, "type registers are deprecated; use config registers = instead"); + + if (chip->num_virt_regs || chip->virt_reg_base || chip->set_type_virt) + dev_warn(map->dev, "virtual registers are deprecated; use config registe= rs instead"); + if (irq_base) { irq_base =3D irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); if (irq_base < 0) { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 432449f318cb..2b5b07f85cc0 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1457,8 +1457,10 @@ struct regmap_irq_sub_irq_map { * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. - * @type_base: Base address for irq type. If zero unsupported. - * @virt_reg_base: Base addresses for extra config regs. + * @type_base: Base address for irq type. If zero unsupported. Depreca= ted, + * use @config_base instead. + * @virt_reg_base: Base addresses for extra config regs. Deprecated, use + * @config_base instead. * @config_base: Base address for IRQ type config regs. If null unsupporte= d. * @irq_reg_stride: Stride to use for chips where registers are not conti= guous. * @init_ack_masked: Ack all masked interrupts once during initalization. @@ -1467,7 +1469,8 @@ struct regmap_irq_sub_irq_map { * @ack_invert: Inverted ack register: cleared bits for ack. * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. * @wake_invert: Inverted wake register: cleared bits are wake enabled. - * @type_invert: Invert the type flags. + * @type_invert: Invert the type flags. Deprecated, use config registers + * instead. * @type_in_mask: Use the mask registers for controlling irq type. Use thi= s if * the hardware provides separate bits for rising/falling edge * or low/high level interrupts and they should be combined into @@ -1486,9 +1489,11 @@ struct regmap_irq_sub_irq_map { * @irqs: Descriptors for individual IRQs. Interrupt numbers are * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. - * @num_type_reg: Number of type registers. + * @num_type_reg: Number of type registers. Deprecated, use config regi= sters + * instead. * @num_virt_regs: Number of non-standard irq configuration registers. - * If zero unsupported. + * If zero unsupported. Deprecated, use config registers + * instead. * @num_config_bases: Number of config base registers. * @num_config_regs: Number of config registers for each config base regis= ter. * @handle_pre_irq: Driver specific callback to handle interrupt from dev= ice @@ -1496,7 +1501,8 @@ struct regmap_irq_sub_irq_map { * @handle_post_irq: Driver specific callback to handle interrupt from dev= ice * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_typ= e() - * and configure virt regs. + * and configure virt regs. Deprecated, use @set_type_config + * callback and config registers instead. * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter= when * driver specific pre/post interrupt handler is called. --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DFB7C433EF for ; Thu, 23 Jun 2022 21:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbiFWVOI (ORCPT ); Thu, 23 Jun 2022 17:14:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230086AbiFWVNr (ORCPT ); Thu, 23 Jun 2022 17:13:47 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0491851310 for ; Thu, 23 Jun 2022 14:13:44 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id p6-20020a05600c1d8600b003a035657950so410542wms.4 for ; Thu, 23 Jun 2022 14:13:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bSfmZia4N88+QuTxam9V/x71AfxUr34uHrXfe8m2m+s=; b=CJKxIDKcSn9k4/Oba6B7a3sSuUvr8v3/17i15mO921Fg+Ib0mQd1DnUaRARHHQlb+N TvKbO4kgpprV9fqFcBdriPBe65vB3PWaS5ZwxtCNbP+eoeWlKwZx5b52RifJEjEyoS/Z c8aKO1oqoAL6audyCk1Vqxk3iEZvclXXyZl9vWwpHRokYhh9e0ChMfYonMCpvs02H/ky vKOOUIqBPSRRrlBDUbe5JJC5l0kFGFg/2QTIXSzeXR0xhbASEE5xlKoY/Leo3Xor48Kr F3F3UneROvGrqzEbDEjcbqqzXf24Bnr3jSloC5SNm3w+zL+pERUJs9NFrVMjuSeNRr1b nSog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bSfmZia4N88+QuTxam9V/x71AfxUr34uHrXfe8m2m+s=; b=Kq1uYHSuTOy+puU1hpN0WCWv/GzCFtw2ghwllkpPg4+UrkyyBc6aDdxdVVmc24m2tf t5Crm+aR5I6GFvabDf3uiALQgUlSV9nEm9RUVDgD51wMl3ffAZvzRRLg3ByVm3wOF5DW m9DPUGUoavwfiqYniYt46JXQdEEAk693c/mGA3Eko/Yt9fCvSfKZ6dncHtJsQ3z9xgwP 58i7+xt+Zzj+PZoHQAriN/VhCVgbXScR57BX+jnMNxihUdCwKtCi9uUMotp8QE5Ixk2s +9OQ4X4Qjr4TUJUBk3qVGF0xfivFWV2GMws8Wf0e23w1yz2p4L5zIxWrmW71zO15fIhP a+MQ== X-Gm-Message-State: AJIora9aX6vHX6A6ASkGXEJrfRnH/nmmpIeUl4RinCSl06WRgKQKv1ER 3/NjRjH7PnXpznh0e1DCGlw= X-Google-Smtp-Source: AGRyM1tRW4NrB3WocxJX0YlwG4yc9l7mZO1xHjrPfMacDIz6u91cTbjM3SZCBhpkc2BE2J/GVBIdlw== X-Received: by 2002:a05:600c:4fd4:b0:3a0:334e:241e with SMTP id o20-20020a05600c4fd400b003a0334e241emr4332887wmq.73.1656018822404; Thu, 23 Jun 2022 14:13:42 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id j3-20020adfe503000000b0021b8a0d680esm400456wrm.86.2022.06.23.14.13.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:42 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/12] regmap-irq: Fix inverted handling of unmask registers Date: Thu, 23 Jun 2022 22:14:18 +0100 Message-Id: <20220623211420.918875-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To me "unmask" suggests that we write 1s to the register when an interrupt is enabled. This also makes sense because it's the opposite of what the "mask" register does (write 1s to disable an interrupt). But regmap-irq does the opposite: for a disabled interrupt, it writes 1s to "unmask" and 0s to "mask". This is surprising and deviates from the usual way mask registers are handled. Additionally, mask_invert didn't interact with unmask registers properly -- it caused them to be ignored entirely. Fix this by making mask and unmask registers orthogonal, using the following behavior: * Mask registers are written with 1s for disabled interrupts. * Unmask registers are written with 1s for enabled interrupts. This behavior supports both normal or inverted mask registers and separate set/clear registers via different combinations of mask_base/unmask_base. The old unmask register behavior is deprecated. Drivers need to opt-in to the new behavior by setting mask_unmask_non_inverted. Warnings are issued if the driver relies on deprecated behavior. Chips that only set one of mask_base/unmask_base don't have to use the mask_unmask_non_inverted flag because that use case was previously not supported. The mask_invert flag is also deprecated in favor of describing inverted mask registers as unmask registers. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 114 +++++++++++++++++++------------ include/linux/regmap.h | 18 ++++- 2 files changed, 84 insertions(+), 48 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index 8cbc62c3d638..2c724ae185c4 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -30,6 +30,9 @@ struct regmap_irq_chip_data { int irq; int wake_count; =20 + unsigned int mask_base; + unsigned int unmask_base; + void *status_reg_buf; unsigned int *main_status_buf; unsigned int *status_buf; @@ -95,7 +98,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map =3D d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; =20 if (d->chip->runtime_pm) { @@ -124,35 +126,23 @@ static void regmap_irq_sync_unlock(struct irq_data *d= ata) * suppress pointless writes. */ for (i =3D 0; i < d->chip->num_regs; i++) { - if (!d->chip->mask_base) - continue; - - reg =3D sub_irq_reg(d, d->chip->mask_base, i); - if (d->chip->mask_invert) { + if (d->mask_base) { + reg =3D sub_irq_reg(d, d->mask_base, i); ret =3D regmap_update_bits(d->map, reg, - d->mask_buf_def[i], ~d->mask_buf[i]); - } else if (d->chip->unmask_base) { - /* set mask with mask_base register */ + d->mask_buf_def[i], d->mask_buf[i]); + if (ret) + dev_err(d->map->dev, "Failed to sync masks in %x\n", + reg); + } + + if (d->unmask_base) { + reg =3D sub_irq_reg(d, d->unmask_base, i); ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); - if (ret < 0) - dev_err(d->map->dev, - "Failed to sync unmasks in %x\n", + if (ret) + dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); - unmask_offset =3D d->chip->unmask_base - - d->chip->mask_base; - /* clear mask with unmask_base register */ - ret =3D regmap_update_bits(d->map, - reg + unmask_offset, - d->mask_buf_def[i], - d->mask_buf[i]); - } else { - ret =3D regmap_update_bits(d->map, reg, - d->mask_buf_def[i], d->mask_buf[i]); } - if (ret !=3D 0) - dev_err(d->map->dev, "Failed to sync masks in %x\n", - reg); =20 reg =3D sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { @@ -704,7 +694,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, int ret =3D -ENOMEM; int num_type_reg; u32 reg; - u32 unmask_offset; =20 if (chip->num_regs <=3D 0) return -EINVAL; @@ -832,6 +821,42 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *f= wnode, d->chip =3D chip; d->irq_base =3D irq_base; =20 + if (chip->mask_base && chip->unmask_base && + !chip->mask_unmask_non_inverted) { + /* + * Chips that specify both mask_base and unmask_base used to + * get inverted mask behavior by default, with no way to ask + * for the normal, non-inverted behavior. This "inverted by + * default" behavior is deprecated, but we have to support it + * until existing drivers have been fixed. + * + * Existing drivers should be updated by swapping mask_base + * and unmask_base and setting mask_unmask_non_inverted=3Dtrue. + * New drivers should always set the flag. + */ + dev_warn(map->dev, "mask_base and unmask_base are inverted, please fix i= t"); + + /* Might as well warn about mask_invert while we're at it... */ + if (chip->mask_invert) + dev_warn(map->dev, "mask_invert=3Dtrue ignored"); + + d->mask_base =3D chip->unmask_base; + d->unmask_base =3D chip->mask_base; + } else if (chip->mask_invert) { + /* + * Swap the roles of mask_base and unmask_base if the bits are + * inverted. This is deprecated, drivers should use unmask_base + * directly. + */ + dev_warn(map->dev, "mask_invert=3Dtrue is deprecated; please switch to u= nmask_base"); + + d->mask_base =3D chip->unmask_base; + d->unmask_base =3D chip->mask_base; + } else { + d->mask_base =3D chip->mask_base; + d->unmask_base =3D chip->unmask_base; + } + if (chip->irq_reg_stride) d->irq_reg_stride =3D chip->irq_reg_stride; else @@ -854,28 +879,27 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *= fwnode, /* Mask all the interrupts by default */ for (i =3D 0; i < chip->num_regs; i++) { d->mask_buf[i] =3D d->mask_buf_def[i]; - if (!chip->mask_base) - continue; - - reg =3D sub_irq_reg(d, d->chip->mask_base, i); =20 - if (chip->mask_invert) + if (d->mask_base) { + reg =3D sub_irq_reg(d, d->mask_base, i); ret =3D regmap_update_bits(d->map, reg, - d->mask_buf[i], ~d->mask_buf[i]); - else if (d->chip->unmask_base) { - unmask_offset =3D d->chip->unmask_base - - d->chip->mask_base; - ret =3D regmap_update_bits(d->map, - reg + unmask_offset, - d->mask_buf[i], - d->mask_buf[i]); - } else + d->mask_buf_def[i], d->mask_buf[i]); + if (ret) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } + } + + if (d->unmask_base) { + reg =3D sub_irq_reg(d, d->unmask_base, i); ret =3D regmap_update_bits(d->map, reg, - d->mask_buf[i], d->mask_buf[i]); - if (ret !=3D 0) { - dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", - reg, ret); - goto err_alloc; + d->mask_buf_def[i], ~d->mask_buf[i]); + if (ret) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } } =20 if (!chip->init_ack_masked) diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 2b5b07f85cc0..708f36dfaeda 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1451,9 +1451,10 @@ struct regmap_irq_sub_irq_map { * main_status set. * * @status_base: Base status register address. - * @mask_base: Base mask register address. - * @unmask_base: Base unmask register address. for chips who have - * separate mask and unmask registers + * @mask_base: Base mask register address. Mask bits are set to 1 when an + * interrupt is masked, 0 when unmasked. + * @unmask_base: Base unmask register address. Unmask bits are set to 1 w= hen + * an interrupt is unmasked and 0 when masked. * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. @@ -1465,6 +1466,16 @@ struct regmap_irq_sub_irq_map { * @irq_reg_stride: Stride to use for chips where registers are not conti= guous. * @init_ack_masked: Ack all masked interrupts once during initalization. * @mask_invert: Inverted mask register: cleared bits are masked out. + * Deprecated; prefer describing an inverted mask register as + * an unmask register. + * @mask_unmask_non_inverted: Controls mask bit inversion for chips that s= et + * both @mask_base and @unmask_base. If false, mask and unmask bits are + * inverted (which is deprecated behavior); if true, bits will not be + * inverted and the registers keep their normal behavior. Note that if + * you use only one of @mask_base or @unmask_base, this flag has no + * effect and is unnecessary. Any new drivers that set both @mask_base + * and @unmask_base should set this to true to avoid relying on the + * deprecated behavior. * @use_ack: Use @ack register even if it is zero. * @ack_invert: Inverted ack register: cleared bits for ack. * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. @@ -1530,6 +1541,7 @@ struct regmap_irq_chip { unsigned int irq_reg_stride; unsigned int init_ack_masked:1; unsigned int mask_invert:1; + unsigned int mask_unmask_non_inverted:1; unsigned int use_ack:1; unsigned int ack_invert:1; unsigned int clear_ack:1; --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A14C7C433EF for ; Thu, 23 Jun 2022 21:14:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230330AbiFWVOQ (ORCPT ); Thu, 23 Jun 2022 17:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230145AbiFWVNt (ORCPT ); Thu, 23 Jun 2022 17:13:49 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D32995158B for ; Thu, 23 Jun 2022 14:13:45 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id e7so469582wrc.13 for ; Thu, 23 Jun 2022 14:13:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4wAUZpTIJxBkOyoOQbWOwMBIqWSc9cnroPNft8+Q9Og=; b=BtYrJrxQexQXMvNKWGoF2/jsVA2PbyjZYzxFsMhIS7XWRyrwWJujZeBZl37Zwrl1Tz c7WDgmQfJnT4RoL+gGsMFxYHeAWBmaeW+44rC6KzKNyDWE4dl+umzbgSDPKlnaYkaCqP Ziiklr+0xKKaxSKLGpUhh53xwZuh+hjTJoMZ/w1WMiDpPLCF788jRfn8Vlm/irIlzKPl J7QH7OrmyV7eV+cFyJCQuwOYMKNMAF2KU2IOYTk8REyKWyPtrMAR4X/vLcrbHPaNLUde Axzmc/FJHeAe1RQA0cY5zbBsfWq8Ejk9xrmz2beB/mhXaGi8besEK9L9sbtF3LzO1iqO HfOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4wAUZpTIJxBkOyoOQbWOwMBIqWSc9cnroPNft8+Q9Og=; b=6+F8woJumqiEalExb7pLqrj/jhwl+Lkq9LL5HswE4Un25M4d5+dPm53SP+EjgE8pTP qwY/knHSR8MC+9fN9OHjwPLNPOeB6pP333055Ih+zZpjC6nrpX946AcFsFXASobwBnob k+yZLuoT0MxVt9MN4F0UodvtG/eYhJRqnjwE9hU1djIqgcG8xkgb88m+IdG360VCwmlE uSZHWuOkufF0cfvzIhHxVl6NWjHrVanmGd/1ddrtZjJ6IWr5a5I0kFCgOLVN59v2zMyI eZdRSaI3xpIiTiYnLy8IeHG0LntsC9wxhAUt7+95RCjqDa8nbFyCsX9HQfRa9KFkIuCH OwIQ== X-Gm-Message-State: AJIora/4d5BNf9nGcxpaKFXi1S5qwLXqvrO8Dbdx2BPMcmycCKgxA7Xc aOPEl32l823K6RmS1bxJQS4= X-Google-Smtp-Source: AGRyM1tSv1SfX0OYx4eRsSrMWm54i/BOa8nYAGjf4DpF9tgHOiK0heTqQKWhi1W88OreIdL3NoNfgg== X-Received: by 2002:adf:fb49:0:b0:21a:3ccc:fb77 with SMTP id c9-20020adffb49000000b0021a3cccfb77mr10085804wrs.280.1656018824112; Thu, 23 Jun 2022 14:13:44 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id j14-20020adfa54e000000b0021b93b29cacsm468918wrb.99.2022.06.23.14.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:43 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/12] regmap-irq: Add get_irq_reg() callback Date: Thu, 23 Jun 2022 22:14:19 +0100 Message-Id: <20220623211420.918875-12-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace the internal sub_irq_reg() function with a public callback that drivers can use when they have more complex register layouts. The default implementation is regmap_irq_get_irq_reg_linear(), used if the chip doesn't provide its own callback. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 126 ++++++++++++++++++++----------- include/linux/regmap.h | 15 +++- 2 files changed, 93 insertions(+), 48 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index 2c724ae185c4..71de097847a7 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -46,30 +46,12 @@ struct regmap_irq_chip_data { =20 unsigned int irq_reg_stride; =20 + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); + unsigned int clear_status:1; }; =20 -static int sub_irq_reg(struct regmap_irq_chip_data *data, - unsigned int base_reg, int i) -{ - const struct regmap_irq_chip *chip =3D data->chip; - struct regmap *map =3D data->map; - struct regmap_irq_sub_irq_map *subreg; - unsigned int offset; - int reg =3D 0; - - if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { - /* Assume linear mapping */ - reg =3D base_reg + (i * map->reg_stride * data->irq_reg_stride); - } else { - subreg =3D &chip->sub_reg_offsets[i]; - offset =3D subreg->offset[0]; - reg =3D base_reg + offset; - } - - return reg; -} - static inline const struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, int irq) @@ -81,7 +63,13 @@ static bool regmap_irq_can_bulk_read_status(struct regma= p_irq_chip_data *data) { struct regmap *map =3D data->map; =20 + /* + * While possible that a user-defined ->get_irq_reg() callback might + * be linear enough to support bulk reads, most of the time it won't. + * Therefore only allow them if the default callback is being used. + */ return data->irq_reg_stride =3D=3D 1 && map->reg_stride =3D=3D 1 && + data->get_irq_reg =3D=3D regmap_irq_get_irq_reg_linear && !map->use_single_read; } =20 @@ -109,7 +97,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) =20 if (d->clear_status) { for (i =3D 0; i < d->chip->num_regs; i++) { - reg =3D sub_irq_reg(d, d->chip->status_base, i); + reg =3D d->get_irq_reg(d, d->chip->status_base, i); =20 ret =3D regmap_read(map, reg, &val); if (ret) @@ -127,7 +115,7 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) */ for (i =3D 0; i < d->chip->num_regs; i++) { if (d->mask_base) { - reg =3D sub_irq_reg(d, d->mask_base, i); + reg =3D d->get_irq_reg(d, d->mask_base, i); ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret) @@ -136,7 +124,7 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) } =20 if (d->unmask_base) { - reg =3D sub_irq_reg(d, d->unmask_base, i); + reg =3D d->get_irq_reg(d, d->unmask_base, i); ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret) @@ -144,7 +132,7 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) reg); } =20 - reg =3D sub_irq_reg(d, d->chip->wake_base, i); + reg =3D d->get_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) ret =3D regmap_update_bits(d->map, reg, @@ -168,7 +156,7 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) * it'll be ignored in irq handler, then may introduce irq storm */ if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { - reg =3D sub_irq_reg(d, d->chip->ack_base, i); + reg =3D d->get_irq_reg(d, d->chip->ack_base, i); =20 /* some chips ack by write 0 */ if (d->chip->ack_invert) @@ -192,7 +180,7 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) for (i =3D 0; i < d->chip->num_type_reg; i++) { if (!d->type_buf_def[i]) continue; - reg =3D sub_irq_reg(d, d->chip->type_base, i); + reg =3D d->get_irq_reg(d, d->chip->type_base, i); if (d->chip->type_invert) ret =3D regmap_update_bits(d->map, reg, d->type_buf_def[i], ~d->type_buf[i]); @@ -208,8 +196,8 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) if (d->chip->num_virt_regs) { for (i =3D 0; i < d->chip->num_virt_regs; i++) { for (j =3D 0; j < d->chip->num_regs; j++) { - reg =3D sub_irq_reg(d, d->chip->virt_reg_base[i], - j); + reg =3D d->get_irq_reg(d, d->chip->virt_reg_base[i], + j); ret =3D regmap_write(map, reg, d->virt_buf[i][j]); if (ret !=3D 0) dev_err(d->map->dev, @@ -221,7 +209,7 @@ static void regmap_irq_sync_unlock(struct irq_data *dat= a) =20 for (i =3D 0; i < d->chip->num_config_bases; i++) { for (j =3D 0; j < d->chip->num_config_regs; j++) { - reg =3D sub_irq_reg(d, d->chip->config_base[i], j); + reg =3D d->get_irq_reg(d, d->chip->config_base[i], j); ret =3D regmap_write(map, reg, d->config_buf[i][j]); if (ret) dev_err(d->map->dev, @@ -382,14 +370,17 @@ static inline int read_sub_irq_data(struct regmap_irq= _chip_data *data, const struct regmap_irq_chip *chip =3D data->chip; struct regmap *map =3D data->map; struct regmap_irq_sub_irq_map *subreg; + unsigned int reg; int i, ret =3D 0; =20 if (!chip->sub_reg_offsets) { - /* Assume linear mapping */ - ret =3D regmap_read(map, chip->status_base + - (b * map->reg_stride * data->irq_reg_stride), - &data->status_buf[b]); + reg =3D data->get_irq_reg(data, chip->status_base, b); + ret =3D regmap_read(map, reg, &data->status_buf[b]); } else { + /* + * Note we can't use ->get_irq_reg() here because the offsets + * in 'subreg' are *not* interchangeable with indices. + */ subreg =3D &chip->sub_reg_offsets[b]; for (i =3D 0; i < subreg->num_regs; i++) { unsigned int offset =3D subreg->offset[i]; @@ -455,10 +446,18 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) * sake of simplicity. and add bulk reads only if needed */ for (i =3D 0; i < chip->num_main_regs; i++) { - ret =3D regmap_read(map, chip->main_status + - (i * map->reg_stride - * data->irq_reg_stride), - &data->main_status_buf[i]); + /* + * For not_fixed_stride, don't use ->get_irq_reg(). + * It would produce an incorrect result. + */ + if (data->chip->not_fixed_stride) + reg =3D chip->main_status + + i * map->reg_stride * data->irq_reg_stride; + else + reg =3D data->get_irq_reg(data, + chip->main_status, i); + + ret =3D regmap_read(map, reg, &data->main_status_buf[i]); if (ret) { dev_err(map->dev, "Failed to read IRQ status %d\n", @@ -523,7 +522,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) =20 } else { for (i =3D 0; i < data->chip->num_regs; i++) { - unsigned int reg =3D sub_irq_reg(data, + unsigned int reg =3D data->get_irq_reg(data, data->chip->status_base, i); ret =3D regmap_read(map, reg, &data->status_buf[i]); =20 @@ -551,7 +550,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) data->status_buf[i] &=3D ~data->mask_buf[i]; =20 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg =3D sub_irq_reg(data, data->chip->ack_base, i); + reg =3D data->get_irq_reg(data, data->chip->ack_base, i); =20 if (chip->ack_invert) ret =3D regmap_write(map, reg, @@ -611,6 +610,36 @@ static const struct irq_domain_ops regmap_domain_ops = =3D { .xlate =3D irq_domain_xlate_onetwocell, }; =20 +/** + * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback. + * @data: Data for the &struct regmap_irq_chip + * @base: Base register + * @index: Register index + * + * Returns the register address corresponding to the given @base and @index + * by the formula ``base + index * regmap_stride * irq_reg_stride``. + */ +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *da= ta, + unsigned int base, int index) +{ + const struct regmap_irq_chip *chip =3D data->chip; + struct regmap *map =3D data->map; + + /* + * FIXME: This is for backward compatibility and should be removed + * when not_fixed_stride is dropped (it's only used by qcom-pm8008). + */ + if (chip->not_fixed_stride && chip->sub_reg_offsets) { + struct regmap_irq_sub_irq_map *subreg; + + subreg =3D &chip->sub_reg_offsets[0]; + return base + subreg->offset[0]; + } + + return base + index * map->reg_stride * chip->irq_reg_stride; +} +EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); + /** * regmap_irq_set_type_config_simple() - Simple IRQ type configuration cal= lback. * @buf: Buffer containing configuration register values, this is a 2D arr= ay of @@ -862,6 +891,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *f= wnode, else d->irq_reg_stride =3D 1; =20 + if (chip->get_irq_reg) + d->get_irq_reg =3D chip->get_irq_reg; + else + d->get_irq_reg =3D regmap_irq_get_irq_reg_linear; + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf =3D kmalloc_array(chip->num_regs, map->format.val_bytes, @@ -881,7 +915,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, d->mask_buf[i] =3D d->mask_buf_def[i]; =20 if (d->mask_base) { - reg =3D sub_irq_reg(d, d->mask_base, i); + reg =3D d->get_irq_reg(d, d->mask_base, i); ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret) { @@ -892,7 +926,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, } =20 if (d->unmask_base) { - reg =3D sub_irq_reg(d, d->unmask_base, i); + reg =3D d->get_irq_reg(d, d->unmask_base, i); ret =3D regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret) { @@ -906,7 +940,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, continue; =20 /* Ack masked but set interrupts */ - reg =3D sub_irq_reg(d, d->chip->status_base, i); + reg =3D d->get_irq_reg(d, d->chip->status_base, i); ret =3D regmap_read(map, reg, &d->status_buf[i]); if (ret !=3D 0) { dev_err(map->dev, "Failed to read IRQ status: %d\n", @@ -918,7 +952,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, d->status_buf[i] =3D ~d->status_buf[i]; =20 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg =3D sub_irq_reg(d, d->chip->ack_base, i); + reg =3D d->get_irq_reg(d, d->chip->ack_base, i); if (chip->ack_invert) ret =3D regmap_write(map, reg, ~(d->status_buf[i] & d->mask_buf[i])); @@ -943,7 +977,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, if (d->wake_buf) { for (i =3D 0; i < chip->num_regs; i++) { d->wake_buf[i] =3D d->mask_buf_def[i]; - reg =3D sub_irq_reg(d, d->chip->wake_base, i); + reg =3D d->get_irq_reg(d, d->chip->wake_base, i); =20 if (chip->wake_invert) ret =3D regmap_update_bits(d->map, reg, @@ -963,7 +997,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, =20 if (chip->num_type_reg && !chip->type_in_mask) { for (i =3D 0; i < chip->num_type_reg; ++i) { - reg =3D sub_irq_reg(d, d->chip->type_base, i); + reg =3D d->get_irq_reg(d, d->chip->type_base, i); =20 ret =3D regmap_read(map, reg, &d->type_buf_def[i]); =20 diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 708f36dfaeda..ae5f1f7d4b5a 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1424,6 +1424,8 @@ struct regmap_irq_sub_irq_map { unsigned int *offset; }; =20 +struct regmap_irq_chip_data; + /** * struct regmap_irq_chip - Description of a generic regmap irq_chip. * @@ -1515,6 +1517,13 @@ struct regmap_irq_sub_irq_map { * and configure virt regs. Deprecated, use @set_type_config * callback and config registers instead. * @set_type_config: Callback used for configuring irq types. + * @get_irq_reg: Callback for mapping (base register, index) pairs to regi= ster + * addresses. The base register will be one of @status_base, + * @mask_base, etc., @main_status, or any of @config_base. + * The index will be in the range [0, num_main_regs[ for the + * main status base, [0, num_type_settings[ for any config + * register base, and [0, num_regs[ for any other base. + * If unspecified then regmap_irq_get_irq_reg_linear() is used. * @irq_drv_data: Driver specific IRQ data which is passed as parameter= when * driver specific pre/post interrupt handler is called. * @@ -1569,11 +1578,13 @@ struct regmap_irq_chip { unsigned long hwirq, int reg); int (*set_type_config)(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); void *irq_drv_data; }; =20 -struct regmap_irq_chip_data; - +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *da= ta, + unsigned int base, int index); int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int typ= e, const struct regmap_irq *irq_data, int idx); =20 --=20 2.35.1 From nobody Mon Apr 20 01:10:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9EFFC433EF for ; Thu, 23 Jun 2022 21:14:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbiFWVOM (ORCPT ); Thu, 23 Jun 2022 17:14:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbiFWVNt (ORCPT ); Thu, 23 Jun 2022 17:13:49 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CC3750B01 for ; Thu, 23 Jun 2022 14:13:47 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id v14so519768wra.5 for ; Thu, 23 Jun 2022 14:13:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3+h6m2WrlhLKh1rsIi7rtOncBT2rRMbfAs6nZpXF74k=; b=IEoepcsOLywRJfkzkeDDN4hUJr72gij73XggCt8M+g9XqH5VW8ON4SmJS81275UleT guluKyCWuTv+KYj6Q0hEo+8RH3yaJFDjrTw1DHkhGTezpRIKRZPU1dvnPrwjJTsTgfov D37YB111nUeWi7Rk2fPh+09yQzWNole7txWzwIkgAnIuqoONe9/6NVCchJyT9Q6xYuUg tzx9jedq4HQyIhhgw6juknHteusDtMXK9G/kuvmuU7Lj5CP7YBqrzZFRok5cDnOMmVQy tnAorlauwJTHLzfbPU9/1bTmyioJGuw5b5H4sumfvNq1+af3Y5jgvnyIjQnyTlsPk0Ox DVAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3+h6m2WrlhLKh1rsIi7rtOncBT2rRMbfAs6nZpXF74k=; b=FQYJ0zXj84jIdnqy3X+cB/ZJAuKQbZWj1VmEwMINKINNLwOfY2Outl80ffHAqnWHvL DdL5rYX+D+EtlAaFqTIoNPBNO1KkBtB8XrurJT9lcWD9nBYUTBM35dr8Np1pD7yCJlpy yAx11EQ0iGGyOAQS96Ol+BLtGFU+rETLX7ENP2R0wVs5NKjN7tPjB6M0IQO9HoHc0D2h 6kZKxohDPgyJHS8wbjYTb53ZZUrGH3EqogHOyHbtrnDuxnpfNZ96MPGfsKm5dYUacIOS Uwnuesff7Op+vLJS6kEtC04Thp88mD0h5bqPCKttqgYVd923T4eN51ZkVpSJNkU1+a8l rgoQ== X-Gm-Message-State: AJIora89p90I/rWxo43BkIefk4DZVpBHjz5zBMfFyCgzfvSiaWYrRB7w AGreuNwzDfvT4YMsUMZR6vk= X-Google-Smtp-Source: AGRyM1stxdtjDnroLVt8emPiHyEHaaBd1/F/furJ9EGijU99d42NlszL/hF7Gy8C7a+G9bvFvSumOg== X-Received: by 2002:a5d:4649:0:b0:218:4d6c:3f3f with SMTP id j9-20020a5d4649000000b002184d6c3f3fmr10199882wrs.148.1656018825629; Thu, 23 Jun 2022 14:13:45 -0700 (PDT) Received: from localhost (92.40.171.44.threembb.co.uk. [92.40.171.44]) by smtp.gmail.com with ESMTPSA id c17-20020a05600c0ad100b003973ea7e725sm6371287wmr.0.2022.06.23.14.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 14:13:45 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 12/12] regmap-irq: Deprecate the not_fixed_stride flag Date: Thu, 23 Jun 2022 22:14:20 +0100 Message-Id: <20220623211420.918875-13-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> References: <20220623211420.918875-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This flag is a bit of a hack and the same thing can be accomplished using a custom ->get_irq_reg() callback. Add a warning to catch any use of the flag. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 2 ++ include/linux/regmap.h | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index 71de097847a7..a691553a0d6f 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -739,6 +739,8 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fw= node, } =20 if (chip->not_fixed_stride) { + dev_warn(map->dev, "not_fixed_stride is deprecated; use ->get_irq_reg() = instead"); + for (i =3D 0; i < chip->num_regs; i++) if (chip->sub_reg_offsets[i].num_regs !=3D 1) return -EINVAL; diff --git a/include/linux/regmap.h b/include/linux/regmap.h index ae5f1f7d4b5a..84ab1c32271f 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1493,8 +1493,10 @@ struct regmap_irq_chip_data; * registers before unmasking interrupts to clear any bi= ts * set when they were masked. * @not_fixed_stride: Used when chip peripherals are not laid out with fix= ed - * stride. Must be used with sub_reg_offsets containing the - * offsets to each peripheral. + * stride. Must be used with sub_reg_offsets containing the + * offsets to each peripheral. Deprecated; the same thing + * can be accomplished with a @get_irq_reg callback, without + * the need for a @sub_reg_offsets table. * @status_invert: Inverted status register: cleared bits are active inter= rupts. * @runtime_pm: Hold a runtime PM lock on the device when accessing it. * --=20 2.35.1