From nobody Mon Apr 20 01:11:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FD2BC43334 for ; Thu, 23 Jun 2022 10:35:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231163AbiFWKfh (ORCPT ); Thu, 23 Jun 2022 06:35:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230271AbiFWKf0 (ORCPT ); Thu, 23 Jun 2022 06:35:26 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33FBC4AE02; Thu, 23 Jun 2022 03:35:25 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 25NAZ88i091646; Thu, 23 Jun 2022 05:35:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1655980509; bh=m5QqvcwrsHAV/oCLXYttOSy+2USJ5RKvL4/zwQ8pn94=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pbpnXl/uQDlRqmUfvdT6zQqv40wFAPaPnJJ4JkEvfKw8BP4cnPc+cym6Q0CCM1UP5 R+evpwiwcqYk8cS1Xh4A9NAkcFJjUlzyLY/jLOr542RvKOZFMo2EgQKRJPaYdvZloI PLB3hlTKoPisYOtQ7YzMm4hhV/xPgVNOvuib9JWU= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 25NAZ880023468 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Jun 2022 05:35:08 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 23 Jun 2022 05:35:08 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 23 Jun 2022 05:35:08 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 25NAZ7Mt077369; Thu, 23 Jun 2022 05:35:08 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , DRI Development List , Devicetree List , Linux Kernel List , Aradhya Bhatia Subject: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add am625 dss compatible Date: Thu, 23 Jun 2022 16:05:03 +0530 Message-ID: <20220623103504.26866-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220623103504.26866-1-a-bhatia1@ti.com> References: <20220623103504.26866-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ti,am625-dss compatible string. The DSS IP on TI's AM625 SoC is an update from the DSS on TI's AM65X SoC. The former has an additional OLDI TX to enable a 2K resolution on OLDI displays or enable 2 duplicated displayw with a smaller resolution. Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4aac..0fc77674eb50 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -19,7 +19,9 @@ description: | =20 properties: compatible: - const: ti,am65x-dss + enum: + - ti,am65x-dss + - ti,am625-dss =20 reg: description: --=20 2.36.1 From nobody Mon Apr 20 01:11:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6883C433EF for ; Thu, 23 Jun 2022 10:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230034AbiFWKfk (ORCPT ); Thu, 23 Jun 2022 06:35:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbiFWKf0 (ORCPT ); Thu, 23 Jun 2022 06:35:26 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 362604AE07; Thu, 23 Jun 2022 03:35:25 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 25NAZAlK091176; Thu, 23 Jun 2022 05:35:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1655980510; bh=1x+NxdEoiSFo+pDWtHOPBfvhGy1WzeyR8WRyXcD8FVI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MuLzlw3JtfS1TYSeHuzBByUGjAismgWup/i0AW+wjibwKoHcVXMLAzztEW3WmoV4H HN1JdbdxAbvnXFOsNYIPLE4QMPF2VEAjVpFI1CiZhwqwc4CTgD9BPbNnK1R0O1Boj3 Zmd2tEJXflTESmlgIf4ANyrHdoTjUNftNTWm6xxg= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 25NAZAO3024596 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Jun 2022 05:35:10 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 23 Jun 2022 05:35:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 23 Jun 2022 05:35:10 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 25NAZ9qX121441; Thu, 23 Jun 2022 05:35:09 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , DRI Development List , Devicetree List , Linux Kernel List , Aradhya Bhatia Subject: [PATCH 2/2] drm/tidss: Add support for AM625 DSS Date: Thu, 23 Jun 2022 16:05:04 +0530 Message-ID: <20220623103504.26866-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220623103504.26866-1-a-bhatia1@ti.com> References: <20220623103504.26866-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the DSS IP on TI's new AM625 SoC in the tidss driver. Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- drivers/gpu/drm/tidss/tidss_dispc.c | 56 ++++++++++++++++++++++++++++- drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index dae47853b728..f084f0688a54 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -272,6 +272,55 @@ const struct dispc_features dispc_j721e_feats =3D { .vid_order =3D { 1, 3, 0, 2 }, }; =20 +const struct dispc_features dispc_am625_feats =3D { + .max_pclk_khz =3D { + [DISPC_VP_DPI] =3D 165000, + [DISPC_VP_OLDI] =3D 165000, + }, + + .scaling =3D { + .in_width_max_5tap_rgb =3D 1280, + .in_width_max_3tap_rgb =3D 2560, + .in_width_max_5tap_yuv =3D 2560, + .in_width_max_3tap_yuv =3D 4096, + .upscale_limit =3D 16, + .downscale_limit_5tap =3D 4, + .downscale_limit_3tap =3D 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max =3D 32, + }, + + .subrev =3D DISPC_AM625, + + .common =3D "common", + .common_regs =3D tidss_am65x_common_regs, + + .num_vps =3D 2, + .vp_name =3D { "vp1", "vp2" }, + .ovr_name =3D { "ovr1", "ovr2" }, + .vpclk_name =3D { "vp1", "vp2" }, + .vp_bus_type =3D { DISPC_VP_OLDI, DISPC_VP_DPI }, + + .vp_feat =3D { .color =3D { + .has_ctm =3D true, + .gamma_size =3D 256, + .gamma_type =3D TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes =3D 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name =3D { "vid", "vidl1" }, + .vid_lite =3D { false, true, }, + .vid_order =3D { 1, 0 }, +}; + static const u16 *dispc_common_regmap; =20 struct dss_vp_data { @@ -775,6 +824,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc= _device *dispc) return dispc_k2g_read_and_clear_irqstatus(dispc); case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: return dispc_k3_read_and_clear_irqstatus(dispc); default: WARN_ON(1); @@ -790,6 +840,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, di= spc_irq_t mask) break; case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: dispc_k3_set_irqenable(dispc, mask); break; default: @@ -1279,6 +1330,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, = u32 hw_plane, x, y, layer); break; case DISPC_AM65X: + case DISPC_AM625: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); break; @@ -2202,6 +2254,7 @@ static void dispc_plane_init(struct dispc_device *dis= pc) break; case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: dispc_k3_plane_init(dispc); break; default: @@ -2307,6 +2360,7 @@ static void dispc_vp_write_gamma_table(struct dispc_d= evice *dispc, dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_AM65X: + case DISPC_AM625: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_J721E: @@ -2580,7 +2634,7 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, 2, 2), REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); =20 - if (dispc->feat->subrev =3D=3D DISPC_AM65X) + if (dispc->feat->subrev =3D=3D DISPC_AM65X || dispc->feat->subrev =3D=3D = DISPC_AM625) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", REG_GET(dispc, DSS_SYSSTATUS, 5, 5), REG_GET(dispc, DSS_SYSSTATUS, 6, 6), diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index e49432f0abf5..a28005dafdc9 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -61,6 +61,7 @@ enum dispc_dss_subrevision { DISPC_K2G, DISPC_AM65X, DISPC_J721E, + DISPC_AM625, }; =20 struct dispc_features { @@ -88,6 +89,7 @@ struct dispc_features { extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; +extern const struct dispc_features dispc_am625_feats; =20 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index 04cfff89ee51..326059e99696 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -235,6 +235,7 @@ static const struct of_device_id tidss_of_table[] =3D { { .compatible =3D "ti,k2g-dss", .data =3D &dispc_k2g_feats, }, { .compatible =3D "ti,am65x-dss", .data =3D &dispc_am65x_feats, }, { .compatible =3D "ti,j721e-dss", .data =3D &dispc_j721e_feats, }, + { .compatible =3D "ti,am625-dss", .data =3D &dispc_am625_feats, }, { } }; =20 --=20 2.36.1