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23 Jun 2022 17:32:12 +0800 Received: from CSBMAIL1.internal.ite.com.tw (CSBMAIL1.internal.ite.com.tw [192.168.65.58]) by mse.ite.com.tw with ESMTP id 25N9W7mn009951; Thu, 23 Jun 2022 17:32:07 +0800 (GMT-8) (envelope-from allen.chen@ite.com.tw) Received: from VirtualBox.internal.ite.com.tw (192.168.70.46) by CSBMAIL1.internal.ite.com.tw (192.168.65.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.14; Thu, 23 Jun 2022 17:32:07 +0800 From: allen CC: Allen Chen , Pin-yen Lin , Jau-Chih Tseng , Hermes Wu , Kenneth Hung , Allen-kh Cheng , Pin-yen Lin , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Matthias Brugger , "open list:DRM DRIVERS" , open list , "moderated list:ARM/Mediatek SoC support" , "moderated list:ARM/Mediatek SoC support" Subject: [PATCH] drm/bridge: add it6505 driver read config from dt property Date: Thu, 23 Jun 2022 17:31:54 +0800 Message-ID: <20220623093154.52701-1-allen.chen@ite.com.tw> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [192.168.70.46] X-ClientProxiedBy: CSBMAIL1.internal.ite.com.tw (192.168.65.58) To CSBMAIL1.internal.ite.com.tw (192.168.65.58) X-TM-SNTS-SMTP: 532277101033EC0C5799347BF5418EF1C05372C83BD9777B75A722A680D091252002:8 X-MAIL: mse.ite.com.tw 25N9W7mn009951 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: allen chen add read max-lane and max-pixel-clock from dt property Signed-off-by: Allen-kh Cheng Signed-off-by: Pin-yen Lin --- drivers/gpu/drm/bridge/ite-it6505.c | 35 ++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/i= te-it6505.c index 4b673c4792d77..c9121d4635a52 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -436,6 +436,8 @@ struct it6505 { bool powered; bool hpd_state; u32 afe_setting; + u32 max_dpi_pixel_clock; + u32 max_lane_count; enum hdcp_state hdcp_status; struct delayed_work hdcp_work; struct work_struct hdcp_wait_ksv_list; @@ -1466,7 +1468,8 @@ static void it6505_parse_link_capabilities(struct it6= 505 *it6505) it6505->lane_count =3D link->num_lanes; DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training", it6505->lane_count); - it6505->lane_count =3D min_t(int, it6505->lane_count, MAX_LANE_COUNT); + it6505->lane_count =3D min_t(int, it6505->lane_count, + it6505->max_lane_count); =20 it6505->branch_device =3D drm_dp_is_branch(it6505->dpcd); DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device", @@ -2895,7 +2898,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, if (mode->flags & DRM_MODE_FLAG_INTERLACE) return MODE_NO_INTERLACE; =20 - if (mode->clock > DPI_PIXEL_CLK_MAX) + if (mode->clock > it6505->max_dpi_pixel_clock) return MODE_CLOCK_HIGH; =20 it6505->video_info.clock =3D mode->clock; @@ -3057,6 +3060,8 @@ static void it6505_parse_dt(struct it6505 *it6505) { struct device *dev =3D &it6505->client->dev; u32 *afe_setting =3D &it6505->afe_setting; + u32 *max_lane_count =3D &it6505->max_lane_count; + u32 *max_dpi_pixel_clock =3D &it6505->max_dpi_pixel_clock; =20 it6505->lane_swap_disabled =3D device_property_read_bool(dev, "no-laneswap"); @@ -3072,7 +3077,31 @@ static void it6505_parse_dt(struct it6505 *it6505) } else { *afe_setting =3D 0; } - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting); + + if (device_property_read_u32(dev, "max-lane-count", + max_lane_count) =3D=3D 0) { + if (*max_lane_count > 4 || *max_lane_count =3D=3D 3) { + dev_err(dev, "max lane count error, use default"); + *max_lane_count =3D MAX_LANE_COUNT; + } + } else { + *max_lane_count =3D MAX_LANE_COUNT; + } + + if (device_property_read_u32(dev, "max-dpi-pixel-clock", + max_dpi_pixel_clock) =3D=3D 0) { + if (*max_dpi_pixel_clock > 297000) { + dev_err(dev, "max pixel clock error, use default"); + *max_dpi_pixel_clock =3D DPI_PIXEL_CLK_MAX; + } + } else { + *max_dpi_pixel_clock =3D DPI_PIXEL_CLK_MAX; + } + + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u", + it6505->afe_setting, it6505->max_lane_count); + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz", + it6505->max_dpi_pixel_clock); } =20 static ssize_t receive_timing_debugfs_show(struct file *file, char __user = *buf, --=20 2.25.1