From nobody Mon Apr 20 02:46:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F0DAC43334 for ; Thu, 23 Jun 2022 00:25:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358461AbiFWAZ4 (ORCPT ); Wed, 22 Jun 2022 20:25:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357598AbiFWAZp (ORCPT ); Wed, 22 Jun 2022 20:25:45 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85CBF6595 for ; Wed, 22 Jun 2022 17:25:44 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id m14so16762274plg.5 for ; Wed, 22 Jun 2022 17:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zfzPrpeTQ+KQnaPrfJgJ0c6hHvEz6fhi8MYcUz9NJ1A=; b=AD/Q3Vl+uQOyhp98mrf6gVeSAJ07vt0jJkGwNMCYDUs7mmAb37KqIGxXvHqdQmySpF 5PlvLWBI447pET9+OUFzDeTEh47Vk7UahKP1NRTrttZEdWdzZOlgEJBrFtouLFo+qysS yo+ug9wTUy4RJ74lsHb01vODkIhr2u8LbpPQ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zfzPrpeTQ+KQnaPrfJgJ0c6hHvEz6fhi8MYcUz9NJ1A=; b=ZUp2JAcqp4om74NnjUoiNzrOenk+zDPhWBr/x89hk2cH4NpDgG9H+gXt7nzTnmumw5 Rrc0bzV7J4AJEG4POvkpx8dUUbZ2O5kAYe6p4rfrW8OOmzI1+xRT7u00TklXWEadC04z OwQb5vl+begVxcb8uk9qlwuV22r4wIQisAoGLmUtlcJJFPllz4MiKNHLCO4WNZcIisNN l0isUqXfTRhA2v1ttL/+XIJdsZxDO/g6rkf0L1Xe8bnMm2y3yInX4kfRdQCumjUgH3f6 uzd87AzScyMFVbniu9QmMkophGQTLSr23NRtrXFPZxKTk3fdNHaqu82h7Z/pLItOwjDT /2bw== X-Gm-Message-State: AJIora+f2pF3sqbofcKcPIs/fkuwtrt20DNKwfhq/qoMY7HzcmBFWPbI 8gUK2TROv2oUw8QIOUPB1UaurA== X-Google-Smtp-Source: AGRyM1uAcIjLj26SdWCactJRqf1+mYcLWpx5z83YzoAbOeNYSMgDBf7oGeQFNXm6zyu+QDnuj9ToEg== X-Received: by 2002:a17:902:900c:b0:16a:4521:10fd with SMTP id a12-20020a170902900c00b0016a452110fdmr6965194plp.75.1655943943888; Wed, 22 Jun 2022 17:25:43 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:f28c:6f86:743c:1c04]) by smtp.gmail.com with ESMTPSA id j1-20020a170903024100b00163fbb1eec5sm13332705plh.229.2022.06.22.17.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 17:25:43 -0700 (PDT) From: Stephen Boyd To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Kuogee Hsieh Subject: [PATCH v2 1/3] drm/msm/dp: Reorganize code to avoid forward declaration Date: Wed, 22 Jun 2022 17:25:38 -0700 Message-Id: <20220623002540.871994-2-swboyd@chromium.org> X-Mailer: git-send-email 2.37.0.rc0.104.g0611611a94-goog In-Reply-To: <20220623002540.871994-1-swboyd@chromium.org> References: <20220623002540.871994-1-swboyd@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Let's move these functions around to avoid having to forward declare dp_ctrl_on_stream_phy_test_report(). Also remove dp_ctrl_reinitialize_mainlink() forward declaration because we're doing that sort of task. Reviewed-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov Signed-off-by: Stephen Boyd --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 104 +++++++++++++++---------------- 1 file changed, 50 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 703249384e7c..bd445e683cfc 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1238,8 +1238,6 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_privat= e *ctrl, return -ETIMEDOUT; } =20 -static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl); - static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, int *training_step) { @@ -1534,38 +1532,6 @@ static int dp_ctrl_link_maintenance(struct dp_ctrl_p= rivate *ctrl) return ret; } =20 -static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl); - -static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) -{ - int ret =3D 0; - - if (!ctrl->link->phy_params.phy_test_pattern_sel) { - drm_dbg_dp(ctrl->drm_dev, - "no test pattern selected by sink\n"); - return ret; - } - - /* - * The global reset will need DP link related clocks to be - * running. Add the global reset just before disabling the - * link clocks and core clocks. - */ - ret =3D dp_ctrl_off(&ctrl->dp_ctrl); - if (ret) { - DRM_ERROR("failed to disable DP controller\n"); - return ret; - } - - ret =3D dp_ctrl_on_link(&ctrl->dp_ctrl); - if (!ret) - ret =3D dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl); - else - DRM_ERROR("failed to enable DP link controller\n"); - - return ret; -} - static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) { bool success =3D false; @@ -1618,6 +1584,56 @@ static bool dp_ctrl_send_phy_test_pattern(struct dp_= ctrl_private *ctrl) return success; } =20 +static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl) +{ + int ret; + struct dp_ctrl_private *ctrl; + + ctrl =3D container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + ctrl->dp_ctrl.pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; + + ret =3D dp_ctrl_enable_stream_clocks(ctrl); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + return ret; + } + + dp_ctrl_send_phy_test_pattern(ctrl); + + return 0; +} + +static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) +{ + int ret =3D 0; + + if (!ctrl->link->phy_params.phy_test_pattern_sel) { + drm_dbg_dp(ctrl->drm_dev, + "no test pattern selected by sink\n"); + return ret; + } + + /* + * The global reset will need DP link related clocks to be + * running. Add the global reset just before disabling the + * link clocks and core clocks. + */ + ret =3D dp_ctrl_off(&ctrl->dp_ctrl); + if (ret) { + DRM_ERROR("failed to disable DP controller\n"); + return ret; + } + + ret =3D dp_ctrl_on_link(&ctrl->dp_ctrl); + if (!ret) + ret =3D dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl); + else + DRM_ERROR("failed to enable DP link controller\n"); + + return ret; +} + void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; @@ -1815,26 +1831,6 @@ static int dp_ctrl_link_retrain(struct dp_ctrl_priva= te *ctrl) return dp_ctrl_setup_main_link(ctrl, &training_step); } =20 -static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl) -{ - int ret; - struct dp_ctrl_private *ctrl; - - ctrl =3D container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - - ctrl->dp_ctrl.pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; - - ret =3D dp_ctrl_enable_stream_clocks(ctrl); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - return ret; - } - - dp_ctrl_send_phy_test_pattern(ctrl); - - return 0; -} - int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) { int ret =3D 0; --=20 https://chromeos.dev From nobody Mon Apr 20 02:46:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26B72C433EF for ; Thu, 23 Jun 2022 00:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358273AbiFWAZx (ORCPT ); Wed, 22 Jun 2022 20:25:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356325AbiFWAZq (ORCPT ); Wed, 22 Jun 2022 20:25:46 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7AA1657C for ; Wed, 22 Jun 2022 17:25:45 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id f65so17574056pgc.7 for ; Wed, 22 Jun 2022 17:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H6qSawmSOE0g+G17lDgx8kU+lzdqvSemPlHNSvMb5tk=; b=XnyGlbS4vaapAKkhYTqyVkESDe7A7zE3gMtloSytSjGCJjuxi7PKhdvHfq6P4jhwCH d4G7oo1AUOHBClCaK2fUkM2s3/1vjeBgoRK20vMDuV05YCxkgXVOFp5tvDu2afEs5CPo 2P/vjlTxTEkviTte3/Rq38O86AVdmxyNqwXhM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H6qSawmSOE0g+G17lDgx8kU+lzdqvSemPlHNSvMb5tk=; b=JJyxOThhXuxTNe4hpUPVo0yC8Bc5KM3RzSRMIItdUo4klfVl0UtxXeFptirGEaAd1n y7JvvGtcIjUbDG7gR7DNYsGyqS3ndHSArw3NM4pXFMQRVixqJhXN69Wng7GYdhrCR571 xH/Y2yW4Hd2AGdT0N2EQ4LN80Hw9XrCFsGEMSQxe0TWE2fxIp0WZ7D3GKyAr+Ssb8Lvr Cl6Es/Rw7FY3ha9f9L+i5TXGWANnnz3ylrn9H3T+t++URc52focbINtcL/pwBj+fwhhn NAA79gKzKFy6r/FIId0I0WtTyy2/j09KqvCGsadPdVyGbRa6Cre5AFkQkgfbuNS43+va +9aQ== X-Gm-Message-State: AJIora8aoZWS3BhMTADdlCj51j4OEn3JW225n2eUulqwSCsS0/TXwxyJ 1prmPoTOhExP4wBiRITMudD1jKmETyvtCQ== X-Google-Smtp-Source: AGRyM1sgkJVP/5fHJ7JoP3ZxYX7bmkjH/csMdww5Is6SN+y0K2vNw3Jg0vNS/CskM7SJcGXx3NttBA== X-Received: by 2002:a63:6205:0:b0:40d:2af5:3c8a with SMTP id w5-20020a636205000000b0040d2af53c8amr4774656pgb.437.1655943945267; Wed, 22 Jun 2022 17:25:45 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:f28c:6f86:743c:1c04]) by smtp.gmail.com with ESMTPSA id j1-20020a170903024100b00163fbb1eec5sm13332705plh.229.2022.06.22.17.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 17:25:44 -0700 (PDT) From: Stephen Boyd To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Kuogee Hsieh Subject: [PATCH v2 2/3] drm/msm/dp: Remove pixel_rate from struct dp_ctrl Date: Wed, 22 Jun 2022 17:25:39 -0700 Message-Id: <20220623002540.871994-3-swboyd@chromium.org> X-Mailer: git-send-email 2.37.0.rc0.104.g0611611a94-goog In-Reply-To: <20220623002540.871994-1-swboyd@chromium.org> References: <20220623002540.871994-1-swboyd@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This struct member is stored to in the function that calls the function which uses it. That's possible with a function argument instead of storing to a struct member. Pass the pixel_rate as an argument instead to simplify the code. Note that dp_ctrl_link_maintenance() was storing the pixel_rate but never using it so we just remove the assignment from there. Cc: Kuogee Hsieh Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov --- dp_ctrl_on_link() almost doesn't even use the pixel_clk either. It just prints the value. I kept it around because maybe it is useful? But if not, then we can remove even more code. drivers/gpu/drm/msm/dp/dp_ctrl.c | 60 ++++++++++++-------------------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 - 2 files changed, 22 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index bd445e683cfc..feb26d4d6e97 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1357,25 +1357,7 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_= ctrl_private *ctrl) if (ret) DRM_ERROR("Unable to start link clocks. ret=3D%d\n", ret); =20 - drm_dbg_dp(ctrl->drm_dev, "link rate=3D%d pixel_clk=3D%d\n", - ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); - - return ret; -} - -static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) -{ - int ret =3D 0; - - dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", - ctrl->dp_ctrl.pixel_rate * 1000); - - ret =3D dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); - if (ret) - DRM_ERROR("Unabled to start pixel clocks. ret=3D%d\n", ret); - - drm_dbg_dp(ctrl->drm_dev, "link rate=3D%d pixel_clk=3D%d\n", - ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); + drm_dbg_dp(ctrl->drm_dev, "link rate=3D%d\n", ctrl->link->link_params.rat= e); =20 return ret; } @@ -1517,8 +1499,6 @@ static int dp_ctrl_link_maintenance(struct dp_ctrl_pr= ivate *ctrl) ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; =20 - ctrl->dp_ctrl.pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; - ret =3D dp_ctrl_setup_main_link(ctrl, &training_step); if (ret) goto end; @@ -1588,14 +1568,16 @@ static int dp_ctrl_on_stream_phy_test_report(struct= dp_ctrl *dp_ctrl) { int ret; struct dp_ctrl_private *ctrl; + unsigned long pixel_rate; =20 ctrl =3D container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); =20 - ctrl->dp_ctrl.pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; + pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; + dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1= 000); =20 - ret =3D dp_ctrl_enable_stream_clocks(ctrl); + ret =3D dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + DRM_ERROR("Unable to start pixel clocks. ret=3D%d\n", ret); return ret; } =20 @@ -1704,11 +1686,12 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) { int rc =3D 0; struct dp_ctrl_private *ctrl; - u32 rate =3D 0; + u32 rate; int link_train_max_retries =3D 5; u32 const phy_cts_pixel_clk_khz =3D 148500; u8 link_status[DP_LINK_STATUS_SIZE]; unsigned int training_step; + unsigned long pixel_rate; =20 if (!dp_ctrl) return -EINVAL; @@ -1716,25 +1699,24 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) ctrl =3D container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); =20 rate =3D ctrl->panel->link_info.rate; + pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; =20 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); =20 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { drm_dbg_dp(ctrl->drm_dev, "using phy test link parameters\n"); - if (!ctrl->panel->dp_mode.drm_mode.clock) - ctrl->dp_ctrl.pixel_rate =3D phy_cts_pixel_clk_khz; + if (!pixel_rate) + pixel_rate =3D phy_cts_pixel_clk_khz; } else { ctrl->link->link_params.rate =3D rate; ctrl->link->link_params.num_lanes =3D ctrl->panel->link_info.num_lanes; - ctrl->dp_ctrl.pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; } =20 - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%d\n", + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, - ctrl->dp_ctrl.pixel_rate); - + pixel_rate); =20 rc =3D dp_ctrl_enable_mainlink_clocks(ctrl); if (rc) @@ -1836,6 +1818,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool f= orce_link_train) int ret =3D 0; bool mainlink_ready =3D false; struct dp_ctrl_private *ctrl; + unsigned long pixel_rate; unsigned long pixel_rate_orig; =20 if (!dp_ctrl) @@ -1843,15 +1826,14 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool= force_link_train) =20 ctrl =3D container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); =20 - ctrl->dp_ctrl.pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; + pixel_rate =3D pixel_rate_orig =3D ctrl->panel->dp_mode.drm_mode.clock; =20 - pixel_rate_orig =3D ctrl->dp_ctrl.pixel_rate; if (dp_ctrl->wide_bus_en) - ctrl->dp_ctrl.pixel_rate >>=3D 1; + pixel_rate >>=3D 1; =20 - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%d\n", + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); + ctrl->link->link_params.num_lanes, pixel_rate); =20 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ ret =3D dp_ctrl_enable_mainlink_clocks(ctrl); @@ -1861,9 +1843,11 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool = force_link_train) } } =20 - ret =3D dp_ctrl_enable_stream_clocks(ctrl); + dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1= 000); + + ret =3D dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + DRM_ERROR("Unable to start pixel clocks. ret=3D%d\n", ret); goto end; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index b563e2e3bfe5..9f29734af81c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -16,7 +16,6 @@ struct dp_ctrl { bool orientation; atomic_t aborted; - u32 pixel_rate; bool wide_bus_en; }; =20 --=20 https://chromeos.dev From nobody Mon Apr 20 02:46:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AEF7C433EF for ; Thu, 23 Jun 2022 00:26:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358717AbiFWAZ6 (ORCPT ); Wed, 22 Jun 2022 20:25:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357211AbiFWAZr (ORCPT ); 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charset="utf-8" This API isn't really more than a couple lines now that we don't store the pixel_rate to the struct member. Inline it into the caller. Cc: Kuogee Hsieh Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 44 ++++++++++++-------------------- 1 file changed, 17 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index feb26d4d6e97..e475f4ca078a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1564,36 +1564,15 @@ static bool dp_ctrl_send_phy_test_pattern(struct dp= _ctrl_private *ctrl) return success; } =20 -static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl) +static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) { int ret; - struct dp_ctrl_private *ctrl; unsigned long pixel_rate; =20 - ctrl =3D container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - - pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; - dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1= 000); - - ret =3D dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); - if (ret) { - DRM_ERROR("Unable to start pixel clocks. ret=3D%d\n", ret); - return ret; - } - - dp_ctrl_send_phy_test_pattern(ctrl); - - return 0; -} - -static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) -{ - int ret =3D 0; - if (!ctrl->link->phy_params.phy_test_pattern_sel) { drm_dbg_dp(ctrl->drm_dev, "no test pattern selected by sink\n"); - return ret; + return 0; } =20 /* @@ -1608,12 +1587,23 @@ static int dp_ctrl_process_phy_test_request(struct = dp_ctrl_private *ctrl) } =20 ret =3D dp_ctrl_on_link(&ctrl->dp_ctrl); - if (!ret) - ret =3D dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl); - else + if (ret) { DRM_ERROR("failed to enable DP link controller\n"); + return ret; + } =20 - return ret; + pixel_rate =3D ctrl->panel->dp_mode.drm_mode.clock; + dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1= 000); + + ret =3D dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + return ret; + } + + dp_ctrl_send_phy_test_pattern(ctrl); + + return 0; } =20 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) --=20 https://chromeos.dev