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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:28:57 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v7 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Date: Thu, 23 Jun 2022 01:28:41 +0200 Message-Id: <20220622232846.852771-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace &rpmhpd power domain integers with their respective defines in order to improve legibility. Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio Reviewed-by: Vinod Koul --- Changes since v6 - Add r-b - Konrad arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index c0137bdcf94b..52428b6df64e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1656,8 +1656,8 @@ mpss: remoteproc@4080000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 0>, - <&rpmhpd 12>; + power-domains =3D <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MSS>; power-domain-names =3D "cx", "mss"; =20 interconnects =3D <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; @@ -2167,8 +2167,8 @@ slpi: remoteproc@5c00000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains =3D <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names =3D "lcx", "lmx"; =20 memory-region =3D <&pil_slpi_mem>; @@ -2235,8 +2235,8 @@ cdsp: remoteproc@98900000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 0>, - <&rpmhpd 10>; + power-domains =3D <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; power-domain-names =3D "cx", "mxc"; =20 interconnects =3D <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -2540,8 +2540,8 @@ adsp: remoteproc@17300000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains =3D <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names =3D "lcx", "lmx"; =20 memory-region =3D <&pil_adsp_mem>; --=20 2.34.1 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCF40C43334 for ; Wed, 22 Jun 2022 23:29:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377413AbiFVX3L (ORCPT ); Wed, 22 Jun 2022 19:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376841AbiFVX3B (ORCPT ); Wed, 22 Jun 2022 19:29:01 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A9C2424AB for ; Wed, 22 Jun 2022 16:28:59 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id c4so480374plc.8 for ; Wed, 22 Jun 2022 16:28:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qwNXvCrvi/OZdFl2f8xJQENyAxQ/emZPF2dzsTw9IUM=; b=XOoedqlQUyF3VUj8BGxrkmP+v2JV/rYmxRLPZ8RpbDs6VcwU9xBilV2RLmRMdeZNgy gvY5A06a8ZwODBPWd8Km8FRP/X6B08AbZTvlZbuLcYHlk1hceSCIpgakxY8HHksWxlvd tfm6tGbsKSs+s3XRVM/6olle1PDQVmzyvQt+S+PGfs22q5f/QSqx3aB8Y9KLgTUNHmH+ cjDKStXwREYvK9KB0zD019upcg9DmUx3Pwh6fu3w52ov16siEqQpyPFmNhYtPTsLvZqq xCqjGIogzr2W0zg7rCpZFkJZv/uDIBSla3138kPi6FUzqm7sItBtX1xGEZE85wPEjVJQ kGeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qwNXvCrvi/OZdFl2f8xJQENyAxQ/emZPF2dzsTw9IUM=; b=1VG5RfVVuyZVie9C1MpXBGq0NPrckY+2tS/ekRuNBXv8a5iJXEUxbOp+tXPf2uDKxY Ro18xugRTqSrMlkUTHfM2vahDkvsbNmMTvslEHPeoahv4AgJFyu+fQoD8IGskggq/dBy DOOiMC2loPneRRhI/T4VsS240gDw+x+Gi99OPoRrcxnPF7ibRZ/RjOSjtULM0uFCPeNt r0x8+yLXHILNx4Jo6REqc5rGcl7kJFEPNguqvKRxgrbxZN5Ki4xvcpBZPvoQ9QrHSW8+ uXsKvo9ZmaOFZytcYKvIiiBdD2goyPJmsw7RcxYEKyVNlgTQAGjIsnl1W3EfqO0uvEZM YRyg== X-Gm-Message-State: AJIora9cS1aRK39o8FLfpygntmaDkd+0+cg+PDYS1R1aj9BaB8tzx9yu JjoPiN2q9xPiGyg44GhE/blKZQ== X-Google-Smtp-Source: AGRyM1uL/SEvPdnLiHk3Sr/parryx1VKsiJTCjYQvsboSgUi7cRDO2htPOdj4eaqpCEL0Uy8xomeDg== X-Received: by 2002:a17:903:2452:b0:16a:38f9:ade9 with SMTP id l18-20020a170903245200b0016a38f9ade9mr10367874pls.152.1655940538855; Wed, 22 Jun 2022 16:28:58 -0700 (PDT) Received: from prec5560.. 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:28:58 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v7 2/6] clk: qcom: add support for SM8350 GPUCC Date: Thu, 23 Jun 2022 01:28:42 +0200 Message-Id: <20220622232846.852771-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss Signed-off-by: Jonathan Marek Reviewed-by: Vinod Koul --- Changes since v1 - Remove .name assignments for clk_parent_data - Dmitry - Use ARRAY_SIZE where possible - Dmitry - Remove commented out code - Dmitry - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry - Assign .parent_hws instead of .hw - Dmitry Changes since v2 - Switch license to dual BSD/GPL - Bjorn - Add Jonathans SoB - Jonathan - Add Linaro to copyright statement - Bjorn - Make .hw.init assignment const - Bjorn - Extract & deduplicate bi_tcxo parent_data - Bjorn - Removed further .name assignment - Bjorn - Move of_device_id declaration - Bjorn Changes since v3 - Change license to BSD/GPL - Rob/Bjorn - Switch from .fw_name to .index Changes since v4 - Change year of copyright statement - Change to dual license for header file - Rob Changes since v5 - Change hex to lower case - Konrad Changes since v6 - Change hex to lower case - Konrad - Change license go GPL 2.0 only - Konrad drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bc4dcf356d82..b11235c21952 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -712,6 +712,14 @@ config SM_GPUCC_8250 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_GPUCC_8350 + tristate "SM8350 Graphics Clock Controller" + select SM_GCC_8350 + help + Support for the graphics clock controller on SM8350 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 36789f5233ef..ef9c64824424 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) +=3D gcc-sm8450.o obj-$(CONFIG_SM_GPUCC_6350) +=3D gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) +=3D gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) +=3D gpucc-sm8250.o +obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8150) +=3D videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm835= 0.c new file mode 100644 index 000000000000..d13fa813d190 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-divider.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_5lpe_vco[] =3D { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x18, + .alpha =3D 0x6000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2a9a699c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static const struct clk_parent_data gpu_cc_parent =3D { + .fw_name =3D "bi_tcxo", +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_pll0", + .parent_data =3D &gpu_cc_parent, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x1a, + .alpha =3D 0xaaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2a9a699c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x100, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_pll1", + .parent_data =3D &gpu_cc_parent, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + gpu_cc_parent, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .fw_name =3D "gcc_gpu_gpll0_clk_src" }, + { .fw_name =3D "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + gpu_cc_parent, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .fw_name =3D "gcc_gpu_gpll0_clk_src" }, + { .fw_name =3D "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x1120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x117c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src =3D { + .reg =3D 0x11c0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "gpu_cc_hub_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src =3D { + .reg =3D 0x11bc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x1078, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1078, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk =3D { + .halt_reg =3D 0x1170, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1170, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x107c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x107c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk =3D { + .halt_reg =3D 0x1088, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1088, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_apb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x1098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1098, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_at_clk =3D { + .halt_reg =3D 0x1080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_qdss_at_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_trig_clk =3D { + .halt_reg =3D 0x1094, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1094, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_qdss_trig_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk =3D { + .halt_reg =3D 0x1084, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1084, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_qdss_tsctr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { + .halt_reg =3D 0x108c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_snoc_dvm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk =3D { + .halt_reg =3D 0x1004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_aon_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x109c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x109c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x120c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x120c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x1064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk =3D { + .halt_reg =3D 0x105c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x105c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_qdss_tsctr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk =3D { + .halt_reg =3D 0x1058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_vsense_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x5000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x5000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x1178, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1178, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x1204, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1204, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk =3D { + .halt_reg =3D 0x802c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x802c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_mnd1x_0_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_mnd1x_1_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x1090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1090, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc =3D { + .gdscr =3D 0x106c, + .gds_hw_ctrl =3D 0x1540, + .pd =3D { + .name =3D "gpu_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc =3D { + .gdscr =3D 0x100c, + .clamp_io_ctrl =3D 0x1508, + .pd =3D { + .name =3D "gpu_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_sm8350_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] =3D &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_QDSS_AT_CLK] =3D &gpu_cc_cx_qdss_at_clk.clkr, + [GPU_CC_CX_QDSS_TRIG_CLK] =3D &gpu_cc_cx_qdss_trig_clk.clkr, + [GPU_CC_CX_QDSS_TSCTR_CLK] =3D &gpu_cc_cx_qdss_tsctr_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_QDSS_TSCTR_CLK] =3D &gpu_cc_gx_qdss_tsctr_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] =3D &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] =3D &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] =3D &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] =3D &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm8350_resets[] =3D { + [GPUCC_GPU_CC_ACD_BCR] =3D { 0x1160 }, + [GPUCC_GPU_CC_CB_BCR] =3D { 0x116c }, + [GPUCC_GPU_CC_CX_BCR] =3D { 0x1068 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] =3D { 0x1174 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] =3D { 0x10a0 }, + [GPUCC_GPU_CC_GMU_BCR] =3D { 0x111c }, + [GPUCC_GPU_CC_GX_BCR] =3D { 0x1008 }, + [GPUCC_GPU_CC_XO_BCR] =3D { 0x1000 }, +}; + +static struct gdsc *gpu_cc_sm8350_gdscs[] =3D { + [GPU_CX_GDSC] =3D &gpu_cx_gdsc, + [GPU_GX_GDSC] =3D &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm8350_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8030, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8350_desc =3D { + .config =3D &gpu_cc_sm8350_regmap_config, + .clks =3D gpu_cc_sm8350_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sm8350_clocks), + .resets =3D gpu_cc_sm8350_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sm8350_resets), + .gdscs =3D gpu_cc_sm8350_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sm8350_gdscs), +}; + +static int gpu_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &gpu_cc_sm8350_desc); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); +} + +static const struct of_device_id gpu_cc_sm8350_match_table[] =3D { + { .compatible =3D "qcom,sm8350-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); + +static struct platform_driver gpu_cc_sm8350_driver =3D { + .probe =3D gpu_cc_sm8350_probe, + .driver =3D { + .name =3D "sm8350-gpucc", + .of_match_table =3D gpu_cc_sm8350_match_table, + }, +}; + +static int __init gpu_cc_sm8350_init(void) +{ + return platform_driver_register(&gpu_cc_sm8350_driver); +} +subsys_initcall(gpu_cc_sm8350_init); + +static void __exit gpu_cc_sm8350_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm8350_driver); +} +module_exit(gpu_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); +MODULE_LICENSE("GPL v2"); --=20 2.34.1 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF5AFC433EF for ; Wed, 22 Jun 2022 23:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377056AbiFVX3X (ORCPT ); Wed, 22 Jun 2022 19:29:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377319AbiFVX3B (ORCPT ); Wed, 22 Jun 2022 19:29:01 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5266A424A3 for ; Wed, 22 Jun 2022 16:29:00 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id h192so17489786pgc.4 for ; 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:28:59 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Dmitry Baryshkov , Rob Herring Subject: [PATCH v7 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Thu, 23 Jun 2022 01:28:43 +0200 Message-Id: <20220622232846.852771-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- Changes since v3 - Separate from qcom,gpucc - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v5 - Add Ack - Rob Changes since v5 - Reverted split from dispcc-sm8250 - Re-added tags from v3 .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm83= 50.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml= b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss + +description: | + Qualcomm graphics clock control module which supports the clocks, resets= and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@3d90000 { + compatible =3D "qcom,sm8350-gpucc"; + reg =3D <0 0x03d90000 0 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bin= dings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif --=20 2.34.1 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A97D8C433EF for ; Wed, 22 Jun 2022 23:29:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377478AbiFVX3R (ORCPT ); Wed, 22 Jun 2022 19:29:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377362AbiFVX3C (ORCPT ); Wed, 22 Jun 2022 19:29:02 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 245A1424B9 for ; Wed, 22 Jun 2022 16:29:01 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id q140so17467601pgq.6 for ; Wed, 22 Jun 2022 16:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kOuRlogJlISSUuhoPrdGlX4HtJb8KRIbCtQdJSjTJ80=; b=gVNgju02wyEdMONFSVTm5rM4W1+RuFdWkoOZov6Wn+B1tccRI1n6akQAmndPzLGuS1 kojsGnjjFSrMsNNFVRWlcxrwr9x1HUtzIU/ZIP7WQwuFSq0sUFe4WB2g533MKbqjyobI K+jxjwQeDjy5+nPFNg7uQ+6vHGHKJGr5KQ0a7g4aZ9HcnnH9I9iL8jfyD8JHFiz0m2Pl 8E7vviw7JjAYPTZqBGsDM301l2S2VpmERYQDyjoyngsqOhvaHHVLdN1TLqhjBIQuNpxS 0P9JE72CUCQCjhwa3Acz4icRVgqc1lz06DGrmUVMb0rq7MJjd7E604tNJto8DiQRGgQn qp1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kOuRlogJlISSUuhoPrdGlX4HtJb8KRIbCtQdJSjTJ80=; b=xGEYGOUo8dSZvHLpviB/E51uMMOr8JcJD1c7zMSP5pyjZMEaUegpyESFeab1CfoDEl dQ19k/eRZn/LfrZBUfIcJNM8Wn0wJIP65QF6YiarXjo/3L8zZLZXl7sa8j7fFnbSz+3L HITM3kqeUCO0ippPvmgky6C/oBh7y19BI3p1UdTmUZlZSFvugDkqUGK5CmvQBFyVOgjK jtCoBQkfv2hQiJ0yVO3UzXcIA3tdpA0yCSlP3jBRStu1ehsvcOAC4B7v9jgYR8NekPzY iTcu43ckcso8AmBbqdfbFKgBWmvuEjoyb16fmtQIBMIsALI27QR4hoiu+UTlFxxk+faE tBqQ== X-Gm-Message-State: AJIora9nOXqZpkcQVEv6bNtQkbDjWdYnIImWA5L7+4K4ewncZVxjWq1o IlKpatTJQhBjhUOo28XW2YEL5g== X-Google-Smtp-Source: AGRyM1ujMNgtP1ufAw+LiDAqmEI8zhGI22PKa61FiRsoqBCXTFpV6aDfOM4FmJ+ANFE3X121FZGbSQ== X-Received: by 2002:a05:6a00:2402:b0:4e1:46ca:68bd with SMTP id z2-20020a056a00240200b004e146ca68bdmr37528941pfh.70.1655940540554; Wed, 22 Jun 2022 16:29:00 -0700 (PDT) Received: from prec5560.. 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:29:00 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v7 4/6] clk: qcom: add support for SM8350 DISPCC Date: Thu, 23 Jun 2022 01:28:44 +0200 Message-Id: <20220622232846.852771-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jonathan Marek Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Vinod Koul --- Changes since v1 - Remove comment - Dmitry Changes since v2 - Add my SoB - Bjorn - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag Changes since v3 - Add kconfig dependency on SM_GCC_8350 - Konrad - Change hex to lowercase - Konrad - Split from dispcc-sm8250.c implementation - Switch from .fw_name to .index Changes since v4 - Hex to lowercase - Konrad - Remove bad match table entries - Konrad Changes since v5 - Reverted split from dispcc-sm8250 - Re-added tags from v3 Changes since v6 - Added kconfig dependency - Konrad - Don't remove comment - Konrad drivers/clk/qcom/Kconfig | 6 +-- drivers/clk/qcom/dispcc-sm8250.c | 63 +++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b11235c21952..efdef8fbf008 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -618,11 +618,11 @@ config SM_DISPCC_6125 splash screen =20 config SM_DISPCC_8250 - tristate "SM8150 and SM8250 Display Clock Controller" - depends on SM_GCC_8150 || SM_GCC_8250 + tristate "SM8150/SM8250/SM8350 Display Clock Controller" + depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8150 and SM8250 devices. + SM8150/SM8250/SM8350 devices. Say Y if you want to support display devices and functionality such as splash screen. =20 diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8= 250.c index db9379634fb2..39b344ebb049 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] =3D { { 249600000, 2000000000, 0 }, }; =20 +static struct pll_vco lucid_5lpe_vco[] =3D { + { 249600000, 1750000000, 0 }, +}; + static struct alpha_pll_config disp_cc_pll0_config =3D { .l =3D 0x47, .alpha =3D 0xE000, @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match= _table[] =3D { { .compatible =3D "qcom,sc8180x-dispcc" }, { .compatible =3D "qcom,sm8150-dispcc" }, { .compatible =3D "qcom,sm8250-dispcc" }, + { .compatible =3D "qcom,sm8350-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_devic= e *pdev) return PTR_ERR(regmap); } =20 - /* note: trion =3D=3D lucid, except for the prepare() op */ + /* Apply differences for SM8150 and SM8350 */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION !=3D CLK_ALPHA_PLL_TYPE_LUCID); if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { @@ -1270,6 +1275,62 @@ static int disp_cc_sm8250_probe(struct platform_devi= ce *pdev) disp_cc_pll1_config.config_ctl_hi1_val =3D 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val =3D 0x000000D0; disp_cc_pll1_init.ops =3D &clk_alpha_pll_trion_ops; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc= ")) { + static struct clk_rcg2 * const rcgs[] =3D { + &disp_cc_mdss_byte0_clk_src, + &disp_cc_mdss_byte1_clk_src, + &disp_cc_mdss_dp_aux1_clk_src, + &disp_cc_mdss_dp_aux_clk_src, + &disp_cc_mdss_dp_link1_clk_src, + &disp_cc_mdss_dp_link_clk_src, + &disp_cc_mdss_dp_pixel1_clk_src, + &disp_cc_mdss_dp_pixel2_clk_src, + &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_mdp_clk_src, + &disp_cc_mdss_pclk0_clk_src, + &disp_cc_mdss_pclk1_clk_src, + &disp_cc_mdss_rot_clk_src, + &disp_cc_mdss_vsync_clk_src, + }; + static struct clk_regmap_div * const divs[] =3D { + &disp_cc_mdss_byte0_div_clk_src, + &disp_cc_mdss_byte1_div_clk_src, + &disp_cc_mdss_dp_link1_div_clk_src, + &disp_cc_mdss_dp_link_div_clk_src, + }; + unsigned int i; + static bool offset_applied; + + /* + * note: trion =3D=3D lucid, except for the prepare() op + * only apply the offsets once (in case of deferred probe) + */ + if (!offset_applied) { + for (i =3D 0; i < ARRAY_SIZE(rcgs); i++) + rcgs[i]->cmd_rcgr -=3D 4; + + for (i =3D 0; i < ARRAY_SIZE(divs); i++) { + divs[i]->reg -=3D 4; + divs[i]->width =3D 4; + } + + disp_cc_mdss_ahb_clk.halt_reg -=3D 4; + disp_cc_mdss_ahb_clk.clkr.enable_reg -=3D 4; + + offset_applied =3D true; + } + + disp_cc_mdss_ahb_clk_src.cmd_rcgr =3D 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val =3D 0x2a9a699c; + disp_cc_pll0_config.test_ctl_hi1_val =3D 0x01800000; + disp_cc_pll0_init.ops =3D &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table =3D lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val =3D 0x2a9a699c; + disp_cc_pll1_config.test_ctl_hi1_val =3D 0x01800000; + disp_cc_pll1_init.ops =3D &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table =3D lucid_5lpe_vco; } =20 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); --=20 2.34.1 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06827C43334 for ; Wed, 22 Jun 2022 23:29:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377432AbiFVX3P (ORCPT ); Wed, 22 Jun 2022 19:29:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377369AbiFVX3D (ORCPT ); Wed, 22 Jun 2022 19:29:03 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD05D424BC for ; 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:29:01 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Rob Herring Subject: [PATCH v7 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Thu, 23 Jun 2022 01:28:45 +0200 Message-Id: <20220622232846.852771-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jonathan Marek Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov --- Changes since v2 - Add SoB - Bjorn Changes since v3 - Separate from qcom,dispcc-sm8x50 - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v4 - Add RB - Rob Changes since v5 - Reverted split from dispcc-sm8250 - Re-added tags from v3 .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yam= l b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250= /SM8350 =20 maintainers: - Jonathan Marek =20 description: | Qualcomm display clock control module which supports the clocks, resets = and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. =20 See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h =20 properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bi= ndings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file --=20 2.34.1 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 668C8C433EF for ; Wed, 22 Jun 2022 23:29:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377509AbiFVX3T (ORCPT ); Wed, 22 Jun 2022 19:29:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377386AbiFVX3D (ORCPT ); Wed, 22 Jun 2022 19:29:03 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E96E424AA for ; Wed, 22 Jun 2022 16:29:02 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id 23so11312695pgc.8 for ; Wed, 22 Jun 2022 16:29:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ry6HLkGyc4JY1yzT6QsAW5x1N1xm0JB7SEDy/5pktSE=; b=oNKxRsOU4pc50gLSBldZGqm/bcScOvod55uXzAd3x3ksz/oGD/RnPyNuOlg3WB+Wnm vAHIXs7S2vgid7AjgLP5TJKsluRi1xamubIqmtiICAqjPaPCJXz7M0oD5pIC3SvHJRco yXhzOgtbakdSQrZ+fkHTrTI7xpFxl+OuWDomZl/pSbls0HyTmivIuFLyHVrtgOkKPRvM UOh8fQPTHXwpFjYUqbVTJ7DawBSg6YKIRzNYqNt+oxJXSQDCSSroj765vsfGhQ1Gx1tD 0eMM4oItqK/+f6ZeXRk8RxBDcugtomHgpS8p6nN0Kr4/YMdAgHBYt+7JzJ7F8ValfotQ Mo8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ry6HLkGyc4JY1yzT6QsAW5x1N1xm0JB7SEDy/5pktSE=; b=ntjzJqz7WrbLRHbsGtzoz0h3SWmyX3aTOP6kbjniJRTVYS1GbbvorouhqpHJ+97Xlq hWnX1DS3hld6LoAvd80Kzlo5a+mZxX8EpKS2u8E1OX3OF0HKAedtn5l7UfyqwC+rvjeb F4rMz0/4PZ2v3Ai5Sfy0inHUOlHG8kDhSnZAPPHIsoA6Wy+kqF+DEOgFE1EE53onI2bk PEMHtcCjCd28ZRoHHMvrIxjtuR1xUOzOr79wSXm/E0dWlVTdJaGBaeDX2+Kj3+2FDRWU atHI2D42FfOne48iyOAYcIry3cDuKAqycGzgiCHUtmH9IgGtVhmvEP7hXxVFzRFCkcYT lACg== X-Gm-Message-State: AJIora8g+Pcub0D8X+V4E1rQXHnJ1utgnxCTGywa9MHermPT5WnpRZoc wqPwLgMA1gsCZkF8l+DzxqW6MQ== X-Google-Smtp-Source: AGRyM1seRUK0Zn7SnxHrspJOLxYW5N5KYB2xwrDRlbpkDSrBE365AschZ8QAd0viGvrmai91z1+NVw== X-Received: by 2002:a05:6a00:ad0:b0:4e1:2d96:2ab0 with SMTP id c16-20020a056a000ad000b004e12d962ab0mr37790377pfl.3.1655940542086; Wed, 22 Jun 2022 16:29:02 -0700 (PDT) Received: from prec5560.. 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:29:01 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v7 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Date: Thu, 23 Jun 2022 01:28:46 +0200 Message-Id: <20220622232846.852771-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- Changes since v2 - Remove interconnect include - Bjorn Changes since v3 - Switch from .fw_name to .index Changes since v5 - Revert .fw_name to .index change Changes since v6 - Add r-b - Konrad arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 52428b6df64e..99464cd1299e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -2525,6 +2526,31 @@ usb_2_dwc3: usb@a800000 { }; }; =20 + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm8350-dispcc"; + reg =3D <0 0x0af00000 0 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names =3D "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + + power-domains =3D <&rpmhpd SM8350_MMCX>; + power-domain-names =3D "mmcx"; + }; + adsp: remoteproc@17300000 { compatible =3D "qcom,sm8350-adsp-pas"; reg =3D <0 0x17300000 0 0x100>; --=20 2.34.1