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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5353.14 via Frontend Transport; Wed, 22 Jun 2022 17:12:35 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 22 Jun 2022 12:12:32 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , Suravee Suthikulpanit Subject: [PATCH v3 1/7] iommu/amd: Warn when found inconsistency EFR mask Date: Wed, 22 Jun 2022 12:11:25 -0500 Message-ID: <20220622171131.11870-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220622171131.11870-1-suravee.suthikulpanit@amd.com> References: <20220622171131.11870-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e64dc68c-774a-4c0a-79c8-08da547266b5 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0077:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:35.0645 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e64dc68c-774a-4c0a-79c8-08da547266b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0077 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The function check_feature_on_all_iommus() checks to ensure if an IOMMU feature support bit is set on the Extended Feature Register (EFR). Current logic iterates through all IOMMU, and returns false when it found the first unset bit. To provide more thorough checking, modify the logic to iterate through all IOMMUs even when found that the bit is not set, and also throws a FW_BUG warning if inconsistency is found. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 3dd0f26039c7..b3e4551ce9dd 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -261,18 +261,29 @@ int amd_iommu_get_num_iommus(void) } =20 #ifdef CONFIG_IRQ_REMAP +/* + * Iterate through all the IOMMUs to verify if the specified + * EFR bitmask of IOMMU feature are set. + * Warn and return false if found inconsistency. + */ static bool check_feature_on_all_iommus(u64 mask) { bool ret =3D false; struct amd_iommu *iommu; =20 for_each_iommu(iommu) { - ret =3D iommu_feature(iommu, mask); - if (!ret) + bool tmp =3D iommu_feature(iommu, mask); + + if ((ret !=3D tmp) && + !list_is_first(&iommu->list, &amd_iommu_list)) { + pr_err(FW_BUG "Found inconsistent EFR mask (%#llx) on iommu%d (%04x:%02= x:%02x.%01x).\n", + mask, iommu->index, iommu->pci_seg->id, PCI_BUS_NUM(iommu->devid= ), + PCI_SLOT(iommu->devid), PCI_FUNC(iommu->devid)); return false; + } + ret =3D tmp; } - - return true; + return ret; } #endif =20 --=20 2.32.0 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9569C433EF for ; Wed, 22 Jun 2022 17:12:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377215AbiFVRMt (ORCPT ); Wed, 22 Jun 2022 13:12:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377134AbiFVRMk (ORCPT ); Wed, 22 Jun 2022 13:12:40 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2070.outbound.protection.outlook.com [40.107.92.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81432658F for ; Wed, 22 Jun 2022 10:12:39 -0700 (PDT) ARC-Seal: i=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:36.8300 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c45be15b-5043-4a96-de9b-08da547267c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6112 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ACPI IVRS table can contain multiple IVHD blocks. Each block contains information used to initialize each IOMMU instance. Currently, init_iommu_all sequentially process IVHD block and initialize IOMMU instance one-by-one. However, certain features require all IOMMUs to be configured in the same way system-wide. In case certain IVHD blocks contain inconsistent information (most likely FW bugs), the driver needs to go through and try to revert settings on IOMMUs that have already been configured. A solution is to split IOMMU initialization into 3 phases: Phase1 : Processes information of the IVRS table for all IOMMU instances. This allow all IVHDs to be processed prior to enabling features. Phase2 : Early feature support check on all IOMMUs (using information in IVHD blocks. Phase3 : Iterates through all IOMMU instances and enabling features. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index b3e4551ce9dd..5f86e357dbaa 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1692,7 +1692,6 @@ static int __init init_iommu_one(struct amd_iommu *io= mmu, struct ivhd_header *h, struct acpi_table_header *ivrs_base) { struct amd_iommu_pci_seg *pci_seg; - int ret; =20 pci_seg =3D get_pci_segment(h->pci_seg, ivrs_base); if (pci_seg =3D=3D NULL) @@ -1773,6 +1772,13 @@ static int __init init_iommu_one(struct amd_iommu *i= ommu, struct ivhd_header *h, if (!iommu->mmio_base) return -ENOMEM; =20 + return init_iommu_from_acpi(iommu, h); +} + +static int __init init_iommu_one_late(struct amd_iommu *iommu) +{ + int ret; + if (alloc_cwwb_sem(iommu)) return -ENOMEM; =20 @@ -1794,10 +1800,6 @@ static int __init init_iommu_one(struct amd_iommu *i= ommu, struct ivhd_header *h, if (amd_iommu_pre_enabled) amd_iommu_pre_enabled =3D translation_pre_enabled(iommu); =20 - ret =3D init_iommu_from_acpi(iommu, h); - if (ret) - return ret; - if (amd_iommu_irq_remap) { ret =3D amd_iommu_create_irq_domain(iommu); if (ret) @@ -1808,7 +1810,7 @@ static int __init init_iommu_one(struct amd_iommu *io= mmu, struct ivhd_header *h, * Make sure IOMMU is not considered to translate itself. The IVRS * table tells us so, but this is a lie! */ - pci_seg->rlookup_table[iommu->devid] =3D NULL; + iommu->pci_seg->rlookup_table[iommu->devid] =3D NULL; =20 return 0; } @@ -1853,6 +1855,7 @@ static int __init init_iommu_all(struct acpi_table_he= ader *table) end +=3D table->length; p +=3D IVRS_HEADER_LENGTH; =20 + /* Phase 1: Process all IVHD blocks */ while (p < end) { h =3D (struct ivhd_header *)p; if (*p =3D=3D amd_iommu_target_ivhd_type) { @@ -1878,6 +1881,15 @@ static int __init init_iommu_all(struct acpi_table_h= eader *table) } WARN_ON(p !=3D end); =20 + /* Phase 2 : Early feature support check */ + + /* Phase 3 : Enabling IOMMU features */ + for_each_iommu(iommu) { + ret =3D init_iommu_one_late(iommu); + if (ret) + return ret; + } + return 0; } =20 --=20 2.32.0 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD47C433EF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:37.7206 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac8852e3-5fcb-4cb5-c22e-08da5472684a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2411 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" EFR[SNPSup] needs to be checked early in the boot process, since it is used to determine how IOMMU driver configures other IOMMU features and data structures. This check can be done as soon as the IOMMU driver finishes parsing IVHDs. Introduce a variable for tracking the SNP support status, which is initialized before enabling the rest of IOMMU features. Also report IOMMU SNP support information for each IOMMU. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 5f86e357dbaa..013c55e3c2f2 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -166,6 +166,8 @@ static bool amd_iommu_disabled __initdata; static bool amd_iommu_force_enable __initdata; static int amd_iommu_target_ivhd_type; =20 +static bool amd_iommu_snp_sup; + LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ @@ -260,7 +262,6 @@ int amd_iommu_get_num_iommus(void) return amd_iommus_present; } =20 -#ifdef CONFIG_IRQ_REMAP /* * Iterate through all the IOMMUs to verify if the specified * EFR bitmask of IOMMU feature are set. @@ -285,7 +286,6 @@ static bool check_feature_on_all_iommus(u64 mask) } return ret; } -#endif =20 /* * For IVHD type 0x11/0x40, EFR is also available via IVHD. @@ -368,7 +368,7 @@ static void iommu_set_cwwb_range(struct amd_iommu *iomm= u) u64 start =3D iommu_virt_to_phys((void *)iommu->cmd_sem); u64 entry =3D start & PM_ADDR_MASK; =20 - if (!iommu_feature(iommu, FEATURE_SNP)) + if (!amd_iommu_snp_sup) return; =20 /* Note: @@ -783,7 +783,7 @@ static void *__init iommu_alloc_4k_pages(struct amd_iom= mu *iommu, void *buf =3D (void *)__get_free_pages(gfp, order); =20 if (buf && - iommu_feature(iommu, FEATURE_SNP) && + amd_iommu_snp_sup && set_memory_4k((unsigned long)buf, (1 << order))) { free_pages((unsigned long)buf, order); buf =3D NULL; @@ -1882,6 +1882,7 @@ static int __init init_iommu_all(struct acpi_table_he= ader *table) WARN_ON(p !=3D end); =20 /* Phase 2 : Early feature support check */ + amd_iommu_snp_sup =3D check_feature_on_all_iommus(FEATURE_SNP); =20 /* Phase 3 : Enabling IOMMU features */ for_each_iommu(iommu) { @@ -2118,6 +2119,9 @@ static void print_iommu_info(void) if (iommu->features & FEATURE_GAM_VAPIC) pr_cont(" GA_vAPIC"); =20 + if (iommu->features & FEATURE_SNP) + pr_cont(" SNP"); + pr_cont("\n"); } } --=20 2.32.0 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE6CC433EF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:38.2206 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f3f0cad-d186-42ec-0c09-08da54726897 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1844 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Brijesh Singh To support SNP, IOMMU needs to be enabled, and prohibits IOMMU configurations where DTE[Mode]=3D0, which means it cannot be supported with IOMMU passthrough domain (a.k.a IOMMU_DOMAIN_IDENTITY), and when AMD IOMMU driver is configured to not use the IOMMU host (v1) page table. Otherwise, RMP table initialization could cause the system to crash. The request to enable SNP support in IOMMU must be done before PCI initialization state of the IOMMU driver because enabling SNP affects how IOMMU driver sets up IOMMU data structures (i.e. DTE). Unlike other IOMMU features, SNP feature does not have an enable bit in the IOMMU control register. Instead, the IOMMU driver introduces an amd_iommu_snp_en variable to track enabling state of SNP. Introduce amd_iommu_snp_enable() for other drivers to request enabling the SNP support in IOMMU, which checks all prerequisites and determines if the feature can be safely enabled. Please see the IOMMU spec section 2.12 for further details. Reviewed-by: Robin Murphy Co-developed-by: Suravee Suthikulpanit Signed-off-by: Suravee Suthikulpanit Signed-off-by: Brijesh Singh --- drivers/iommu/amd/amd_iommu_types.h | 5 ++++ drivers/iommu/amd/init.c | 44 +++++++++++++++++++++++++++-- drivers/iommu/amd/iommu.c | 4 +-- include/linux/amd-iommu.h | 4 +++ 4 files changed, 53 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 73b729be7410..ce4db2835b36 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -463,6 +463,9 @@ extern bool amd_iommu_irq_remap; /* kmem_cache to get tables with 128 byte alignement */ extern struct kmem_cache *amd_iommu_irq_cache; =20 +/* SNP is enabled on the system? */ +extern bool amd_iommu_snp_en; + #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff) #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff) #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) |= \ @@ -1013,4 +1016,6 @@ extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; #endif =20 +extern struct iommu_ops amd_iommu_ops; + #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 013c55e3c2f2..c62fb4470519 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -95,8 +95,6 @@ * out of it. */ =20 -extern const struct iommu_ops amd_iommu_ops; - /* * structure describing one IOMMU in the ACPI table. Typically followed by= one * or more ivhd_entrys. @@ -168,6 +166,9 @@ static int amd_iommu_target_ivhd_type; =20 static bool amd_iommu_snp_sup; =20 +bool amd_iommu_snp_en; +EXPORT_SYMBOL(amd_iommu_snp_en); + LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ @@ -3549,3 +3550,42 @@ int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8= bank, u8 cntr, u8 fxn, u64 =20 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); } + +#ifdef CONFIG_AMD_MEM_ENCRYPT +int amd_iommu_snp_enable(void) +{ + /* + * The SNP support requires that IOMMU must be enabled, and is + * not configured in the passthrough mode. + */ + if (no_iommu || iommu_default_passthrough()) { + pr_err("SNP: IOMMU is disabled or configured in passthrough mode, SNP ca= nnot be supported"); + return -EINVAL; + } + + /* + * Prevent enabling SNP after IOMMU_ENABLED state because this process + * affect how IOMMU driver sets up data structures and configures + * IOMMU hardware. + */ + if (init_state > IOMMU_ENABLED) { + pr_err("SNP: Too late to enable SNP for IOMMU.\n"); + return -EINVAL; + } + + amd_iommu_snp_en =3D amd_iommu_snp_sup; + if (!amd_iommu_snp_en) + return -EINVAL; + + pr_info("SNP enabled\n"); + + /* Enforce IOMMU v1 pagetable when SNP is enabled. */ + if (amd_iommu_pgtable !=3D AMD_IOMMU_V1) { + pr_warn("Force to using AMD IOMMU v1 page table due to SNP\n"); + amd_iommu_pgtable =3D AMD_IOMMU_V1; + amd_iommu_ops.pgsize_bitmap =3D AMD_IOMMU_PGSIZES; + } + + return 0; +} +#endif diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 86045dc50a0f..0792cd618dba 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -71,7 +71,7 @@ LIST_HEAD(acpihid_map); * Domain for untranslated devices - only allocated * if iommu=3Dpt passed on kernel cmd line. */ -const struct iommu_ops amd_iommu_ops; +struct iommu_ops amd_iommu_ops; =20 static ATOMIC_NOTIFIER_HEAD(ppr_notifier); int amd_iommu_max_glx_val =3D -1; @@ -2412,7 +2412,7 @@ static int amd_iommu_def_domain_type(struct device *d= ev) return 0; } =20 -const struct iommu_ops amd_iommu_ops =3D { +struct iommu_ops amd_iommu_ops =3D { .capable =3D amd_iommu_capable, .domain_alloc =3D amd_iommu_domain_alloc, .probe_device =3D amd_iommu_probe_device, diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 58e6c3806c09..953e6f12fa1c 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -206,4 +206,8 @@ int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 ba= nk, u8 cntr, u8 fxn, u64 *value); struct amd_iommu *get_amd_iommu(unsigned int idx); =20 +#ifdef CONFIG_AMD_MEM_ENCRYPT +int amd_iommu_snp_enable(void); +#endif + #endif /* _ASM_X86_AMD_IOMMU_H */ --=20 2.32.0 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C9CFC433EF for ; Wed, 22 Jun 2022 17:13:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377288AbiFVRNF (ORCPT ); Wed, 22 Jun 2022 13:13:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377221AbiFVRMu (ORCPT ); Wed, 22 Jun 2022 13:12:50 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2043.outbound.protection.outlook.com [40.107.237.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06B25E0CB for ; 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Wed, 22 Jun 2022 17:12:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5353.14 via Frontend Transport; Wed, 22 Jun 2022 17:12:39 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 22 Jun 2022 12:12:35 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , Suravee Suthikulpanit Subject: [PATCH v3 5/7] iommu/amd: Set translation valid bit only when IO page tables are in use Date: Wed, 22 Jun 2022 12:11:29 -0500 Message-ID: <20220622171131.11870-6-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220622171131.11870-1-suravee.suthikulpanit@amd.com> References: <20220622171131.11870-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 82e9f8b7-ef1a-4ee2-3bd4-08da5472694c X-MS-TrafficTypeDiagnostic: CY4PR12MB1734:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:39.4080 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82e9f8b7-ef1a-4ee2-3bd4-08da5472694c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1734 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On AMD system with SNP enabled, IOMMU hardware checks the host translation valid (TV) and guest translation valid (GV) bits in the device table entry (DTE) before accessing the corresponded page tables. However, current IOMMU driver sets the TV bit for all devices regardless of whether the host page table is in use. This results in ILLEGAL_DEV_TABLE_ENTRY event for devices, which do not the host page table root pointer set up. Thefore, when SNP is enabled, only set TV bit when DMA remapping is not used, which is when domain ID in the AMD IOMMU device table entry (DTE) is zero. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 3 ++- drivers/iommu/amd/iommu.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index c62fb4470519..f5695ccb7c81 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2544,7 +2544,8 @@ static void init_device_table_dma(struct amd_iommu_pc= i_seg *pci_seg) =20 for (devid =3D 0; devid <=3D pci_seg->last_bdf; ++devid) { __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_VALID); - __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_TRANSLATION); + if (!amd_iommu_snp_en) + __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_TRANSLATION); } } =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0792cd618dba..4f4571d3ff61 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1563,7 +1563,14 @@ static void set_dte_entry(struct amd_iommu *iommu, u= 16 devid, (domain->flags & PD_GIOV_MASK)) pte_root |=3D DTE_FLAG_GIOV; =20 - pte_root |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; + pte_root |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V; + + /* + * When SNP is enabled, Only set TV bit when IOMMU + * page translation is in use. + */ + if (!amd_iommu_snp_en || (domain->id !=3D 0)) + pte_root |=3D DTE_FLAG_TV; =20 flags =3D dev_table[devid].data[1]; =20 @@ -1625,7 +1632,11 @@ static void clear_dte_entry(struct amd_iommu *iommu,= u16 devid) struct dev_table_entry *dev_table =3D get_dev_table(iommu); =20 /* remove entry from the device table seen by the hardware */ - dev_table[devid].data[0] =3D DTE_FLAG_V | DTE_FLAG_TV; + dev_table[devid].data[0] =3D DTE_FLAG_V; + + if (!amd_iommu_snp_en) + dev_table[devid].data[0] |=3D DTE_FLAG_TV; + dev_table[devid].data[1] &=3D DTE_FLAG_MASK; =20 amd_iommu_apply_erratum_63(iommu, devid); --=20 2.32.0 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F063C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5353.14 via Frontend Transport; Wed, 22 Jun 2022 17:12:39 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 22 Jun 2022 12:12:35 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , Suravee Suthikulpanit Subject: [PATCH v3 6/7] iommu/amd: Do not support IOMMU_DOMAIN_IDENTITY after SNP is enabled Date: Wed, 22 Jun 2022 12:11:30 -0500 Message-ID: <20220622171131.11870-7-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220622171131.11870-1-suravee.suthikulpanit@amd.com> References: <20220622171131.11870-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 96a36770-816e-4e0b-ac49-08da5472699f X-MS-TrafficTypeDiagnostic: DM4PR12MB5216:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:39.9548 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96a36770-816e-4e0b-ac49-08da5472699f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5216 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Once SNP is enabled (by executing SNP_INIT command), IOMMU can no longer support the passthrough domain (i.e. IOMMU_DOMAIN_IDENTITY). The SNP_INIT command is called early in the boot process, and would fail if the kernel is configure to default to passthrough mode. After the system is already booted, users can try to change IOMMU domain type of a particular IOMMU group. In this case, the IOMMU driver needs to check the SNP-enable status and return failure when requesting to change domain type to identity. Therefore, return failure when trying to allocate identity domain. Reviewed-by: Robin Murphy Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4f4571d3ff61..7093e26fec59 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2119,6 +2119,14 @@ static struct iommu_domain *amd_iommu_domain_alloc(u= nsigned type) { struct protection_domain *domain; =20 + /* + * Since DTE[Mode]=3D0 is prohibited on SNP-enabled system, + * default to use IOMMU_DOMAIN_DMA[_FQ]. + */ + if (WARN_ONCE(amd_iommu_snp_en && (type =3D=3D IOMMU_DOMAIN_IDENTITY), + "Cannot allocate identity domain due to SNP\n")) + return NULL; + domain =3D protection_domain_alloc(type); if (!domain) return NULL; --=20 2.32.0 From nobody Mon Apr 20 02:46:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43E9CC43334 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2022 17:12:40.7829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13066489-84b4-4d34-0697-08da54726a1e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1527 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The IOMMUv2 APIs (for supporting shared virtual memory with PASID) configures the domain with IOMMU v2 page table, and sets DTE[Mode]=3D0. This configuration cannot be supported on SNP-enabled system. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index f5695ccb7c81..4c9b96160a8b 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -3448,7 +3448,12 @@ __setup("ivrs_acpihid", parse_ivrs_acpihid); =20 bool amd_iommu_v2_supported(void) { - return amd_iommu_v2_present; + /* + * Since DTE[Mode]=3D0 is prohibited on SNP-enabled system + * (i.e. EFR[SNPSup]=3D1), IOMMUv2 page table cannot be used without + * setting up IOMMUv1 page table. + */ + return amd_iommu_v2_present && !amd_iommu_snp_en; } EXPORT_SYMBOL(amd_iommu_v2_supported); =20 --=20 2.32.0