From nobody Sat Sep 21 23:31:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15B47C43334 for ; Wed, 22 Jun 2022 09:06:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357119AbiFVJG4 (ORCPT ); Wed, 22 Jun 2022 05:06:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356308AbiFVJGM (ORCPT ); Wed, 22 Jun 2022 05:06:12 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DFFB2251E; Wed, 22 Jun 2022 02:06:07 -0700 (PDT) X-UUID: c50ded026a214356aade371bea5fc932-20220622 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:f81614f0-ff3f-4552-bf4e-6190cdfff317,OB:10,L OB:30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham, ACTION:release,TS:100 X-CID-INFO: VERSION:1.1.6,REQID:f81614f0-ff3f-4552-bf4e-6190cdfff317,OB:10,LOB :30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:100 X-CID-META: VersionHash:b14ad71,CLOUDID:79ccbd2d-1756-4fa3-be7f-474a6e4be921,C OID:9e1b96a75a71,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: c50ded026a214356aade371bea5fc932-20220622 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 699344263; Wed, 22 Jun 2022 17:06:02 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 22 Jun 2022 17:06:01 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Jun 2022 17:06:00 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 22 Jun 2022 17:05:59 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v3 10/10] net: ethernet: mtk-star-emac: enable half duplex hardware support Date: Wed, 22 Jun 2022 17:05:45 +0800 Message-ID: <20220622090545.23612-11-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220622090545.23612-1-biao.huang@mediatek.com> References: <20220622090545.23612-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current driver don't support 100/10M duplex half function. This patch enable half duplex capability in hardware. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 30 ++++++++----------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/et= hernet/mediatek/mtk_star_emac.c index 87e5bc9c343a..67e85705b770 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -883,32 +883,26 @@ static void mtk_star_phy_config(struct mtk_star_priv = *priv) val <<=3D MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD; =20 val |=3D MTK_STAR_BIT_PHY_CTRL1_AN_EN; - val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; - val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; - /* Only full-duplex supported for now. */ - val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; - - regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); - if (priv->pause) { - val =3D MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; - val <<=3D MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; - val |=3D MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; + val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; + val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; + val |=3D MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; } else { - val =3D 0; + val &=3D ~MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; + val &=3D ~MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; + val &=3D ~MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; } + regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); =20 + val =3D MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; + val <<=3D MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; + val |=3D MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; regmap_update_bits(priv->regs, MTK_STAR_REG_FC_CFG, MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH | MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR, val); =20 - if (priv->pause) { - val =3D MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; - val <<=3D MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; - } else { - val =3D 0; - } - + val =3D MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; + val <<=3D MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; regmap_update_bits(priv->regs, MTK_STAR_REG_EXT_CFG, MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS, val); } --=20 2.25.1