From nobody Sat Sep 21 23:23:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65C82C433EF for ; Tue, 21 Jun 2022 11:37:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349745AbiFULhu (ORCPT ); Tue, 21 Jun 2022 07:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349622AbiFULhq (ORCPT ); Tue, 21 Jun 2022 07:37:46 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 354E629CAA; Tue, 21 Jun 2022 04:37:40 -0700 (PDT) X-UUID: 705b56a7b998466c9086d6f8d6819dee-20220621 X-CID-P-RULE: Spam_GS6885AD X-CID-O-INFO: VERSION:1.1.6,REQID:95bc9bd3-5037-46eb-9811-fb50ad3f26a5,OB:0,LO B:10,IP:0,URL:5,TC:0,Content:0,EDM:25,RT:0,SF:95,FILE:0,RULE:Spam_GS6885AD ,ACTION:quarantine,TS:125 X-CID-INFO: VERSION:1.1.6,REQID:95bc9bd3-5037-46eb-9811-fb50ad3f26a5,OB:0,LOB: 10,IP:0,URL:5,TC:0,Content:0,EDM:25,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:125 X-CID-META: VersionHash:b14ad71,CLOUDID:0abb1238-5e4b-44d7-80b2-bb618cb09d29,C OID:efe3ace09479,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:5,IP:nil,UR L:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 705b56a7b998466c9086d6f8d6819dee-20220621 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 687725283; Tue, 21 Jun 2022 19:37:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 21 Jun 2022 19:37:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 21 Jun 2022 19:37:33 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v13 03/14] drm/mediatek: dpi: Add support for quantization range Date: Tue, 21 Jun 2022 19:37:21 +0800 Message-ID: <20220621113732.11595-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220621113732.11595-1-rex-bc.chen@mediatek.com> References: <20220621113732.11595-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For RGB colorimetry, CTA-861 support both limited and full range data when receiving video with RGB color space. We use drm_default_rgb_quant_range() to determine the correct setting. Signed-off-by: Bo-Chen Chen Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++------------ 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index f66a121ba0c9..24f4b5618276 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -244,16 +244,30 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dp= i, u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } =20 -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, + struct mtk_dpi_yc_limit limit; + + if (drm_default_rgb_quant_range(&dpi->mode) =3D=3D + HDMI_QUANTIZATION_RANGE_LIMITED) { + limit.y_bottom =3D 0x10; + limit.y_top =3D 0xfe0; + limit.c_bottom =3D 0x10; + limit.c_top =3D 0xfe0; + } else { + limit.y_bottom =3D 0; + limit.y_top =3D 0xfff; + limit.c_bottom =3D 0; + limit.c_top =3D 0xfff; + } + + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, Y_LIMINT_TOP_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, C_LIMIT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK); } =20 @@ -458,7 +472,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; @@ -493,11 +506,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); =20 - limit.c_bottom =3D 0x0010; - limit.c_top =3D 0x0FE0; - limit.y_bottom =3D 0x0010; - limit.y_top =3D 0x0FE0; - dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol =3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -545,7 +553,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); =20 - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); --=20 2.18.0