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[71.202.34.56]) by smtp.gmail.com with ESMTPSA id k7-20020a63ab47000000b00408af01cb42sm10061676pgp.81.2022.06.20.22.35.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 22:35:35 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Stephen Boyd , Alexandru M Stan , Douglas Anderson , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 1/5] arm64: dts: qcom: sc7180: Add wormdingler dts files Date: Mon, 20 Jun 2022 22:33:47 -0700 Message-Id: <20220620223345.v9.1.Id769ddc5dbf570ccb511db96da59f97d08f75a9c@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220621053351.650431-1-joebar@chromium.org> References: <20220621053351.650431-1-joebar@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wormdingler is a trogdor-based board, shipping to customers as the Lenovo IdeaPad Chromebook Duet 3. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with the camera (sc7180-trogdor-mipi-camera.dtsi) #include removed. Signed-off-by: Joseph S. Barrera III --- (no changes since v7) Changes in v7: - Restore changes requested by Doug. Changes in v6: - Only include sc7180.dtsi in sc7180-trogdor.dtsi (19794489fa24). - Simplify spi0/spi6 labeling (d277cab7afc7). - Simplify trackpad enabling (51d30402be75). - Accidentally deleted changes requested by Doug. Changes in v5: - Replaced _ in node name with - - Ordered nodes by name Changes in v4: - Cleaned up rt5682s files - Restored camcc definition - Added missing version history Changes in v3: - Removed camcc definition Changes in v2: - Word wrapped patch description. - Removed "Author" from patch description. - Fixed whitespace around "en_pp3300_dx_edp" arch/arm64/boot/dts/qcom/Makefile | 6 + .../sc7180-trogdor-wormdingler-rev0-boe.dts | 22 + .../sc7180-trogdor-wormdingler-rev0-inx.dts | 22 + .../qcom/sc7180-trogdor-wormdingler-rev0.dtsi | 53 +++ ...0-trogdor-wormdingler-rev1-boe-rt5682s.dts | 29 ++ .../sc7180-trogdor-wormdingler-rev1-boe.dts | 28 ++ ...0-trogdor-wormdingler-rev1-inx-rt5682s.dts | 29 ++ .../sc7180-trogdor-wormdingler-rev1-inx.dts | 22 + .../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 408 ++++++++++++++++++ 9 files changed, 619 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 0-boe.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 0-inx.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 0.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 1-boe-rt5682s.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 1-boe.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 1-inx-rt5682s.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev= 1-inx.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 2f8aec2cc6db..e4114e22548a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -81,6 +81,12 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev0-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev1-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev1-inx-rt5682s.d= tb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev1-boe-rt5682s.d= tb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.d= ts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts new file mode 100644 index 000000000000..d6ed7d0afe4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 =3D> 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model =3D "Google Wormdingler rev0 BOE panel board"; + compatible =3D "google,wormdingler-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible =3D "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.d= ts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts new file mode 100644 index 000000000000..c03525ea64ca --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 =3D> 0 + * - bits 7..4: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model =3D "Google Wormdingler rev0 INX panel board"; + compatible =3D "google,wormdingler-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible =3D "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi = b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi new file mode 100644 index 000000000000..db29e0cba29d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +&avdd_lcd { + gpio =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios =3D <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ +&avdd_lcd_en { + pinmux { + pins =3D "gpio80"; + }; + + pinconf { + pins =3D "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins =3D "gpio81"; + }; + + pinconf { + pins =3D "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins =3D "gpio76"; + }; + + pinconf { + pins =3D "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-r= t5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-r= t5682s.dts new file mode 100644 index 000000000000..aa605885c371 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.= dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x401 =3D> 1025 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-boe.dts" + +/ { + model =3D "Google Wormdingler rev1+ (BOE, rt5682s)"; + compatible =3D "google,wormdingler-sku1025", "qcom,sc7180"; +}; + +&alc5682 { + compatible =3D "realtek,rt5682s"; + realtek,dmic1-clk-pin =3D <2>; + realtek,dmic-clk-rate-hz =3D <2048000>; +}; + +&sound { + compatible =3D "google,sc7180-trogdor"; + model =3D "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.d= ts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts new file mode 100644 index 000000000000..c5b0658bd632 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x400 =3D> 1024 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model =3D "Google Wormdingler rev1+ BOE panel board"; + compatible =3D "google,wormdingler-sku1024", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top =3D /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-rescode-offset-bot =3D /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-drive-ldo-level =3D <450>; +}; + +&panel { + compatible =3D "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-r= t5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-r= t5682s.dts new file mode 100644 index 000000000000..7116c44c8d85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.= dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0001 =3D> 1 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-inx.dts" + +/ { + model =3D "Google Wormdingler rev1+ (INX, rt5682s)"; + compatible =3D "google,wormdingler-sku1", "qcom,sc7180"; +}; + +&alc5682 { + compatible =3D "realtek,rt5682s"; + realtek,dmic1-clk-pin =3D <2>; + realtek,dmic-clk-rate-hz =3D <2048000>; +}; + +&sound { + compatible =3D "google,sc7180-trogdor"; + model =3D "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.d= ts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts new file mode 100644 index 000000000000..dd34a2297ea0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0000 =3D> 0 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model =3D "Google Wormdingler rev1+ INX panel board"; + compatible =3D "google,wormdingler-sku0", "qcom,sc7180"; +}; + +&panel { + compatible =3D "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arc= h/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi new file mode 100644 index 000000000000..701dd11a12cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/ { + avdd_lcd: avdd-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd_lcd"; + + gpio =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&avdd_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "avee_lcd"; + + gpio =3D <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&avee_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + pp1800_ts: + v1p8_mipi: v1p8-mipi { + compatible =3D "regulator-fixed"; + regulator-name =3D "v1p8_mipi"; + + gpio =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_1800_en>; + + vin-supply =3D <&pp3300_a>; + }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pm6150_adc_tm 1>; + sustainable-power =3D <574>; + + trips { + skin_temp_alert0: trip-point0 { + temperature =3D <58000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature =3D <62500>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + skin-temp-crit { + temperature =3D <68000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&skin_temp_alert0>; + cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip =3D <&skin_temp_alert1>; + cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&backlight { + pwms =3D <&cros_ec_pwm 0>; +}; + +&camcc { + status =3D "okay"; +}; + +&cros_ec { + base_detection: cbas { + compatible =3D "google,cros-cbas"; + }; +}; + +&dsi0 { + + panel: panel@0 { + reg =3D <0>; + enable-gpios =3D <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_reset_1800>; + avdd-supply =3D <&avdd_lcd>; + avee-supply =3D <&avee_lcd>; + pp1800-supply =3D <&v1p8_mipi>; + pp3300-supply =3D <&pp3300_dx_edp>; + backlight =3D <&backlight>; + rotation =3D <270>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + panel_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&i2c4 { + status =3D "okay"; + clock-frequency =3D <400000>; + + ap_ts: touchscreen@1 { + compatible =3D "hid-over-i2c"; + reg =3D <0x01>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_int_l>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <9 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms =3D <70>; + hid-descr-addr =3D <0x0001>; + + vdd-supply =3D <&pp3300_ts>; + vddl-supply =3D <&pp1800_ts>; + }; +}; + +&pm6150_adc { + skin-temp-thermistor@4d { + reg =3D ; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + }; +}; + +&pm6150_adc_tm { + status =3D "okay"; + + skin-temp-thermistor@1 { + reg =3D <1>; + io-channels =3D <&pm6150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; +}; + +&pp1800_uf_cam { + status =3D "okay"; +}; + +&pp1800_wf_cam { + status =3D "okay"; +}; + +&pp2800_uf_cam { + status =3D "okay"; +}; + +&pp2800_wf_cam { + status =3D "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant =3D "GO_WORMDINGLER"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio =3D <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins =3D "gpio85"; + }; + + pinconf { + pins =3D "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names =3D "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins =3D "gpio88"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio88"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins =3D "gpio21"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio21"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins =3D "gpio86"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio86"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins =3D "gpio87"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio87"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.31.0 From nobody Sun Apr 26 08:21:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74D7DC43334 for ; Tue, 21 Jun 2022 05:35:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345253AbiFUFfr (ORCPT ); Tue, 21 Jun 2022 01:35:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345110AbiFUFfk (ORCPT ); Tue, 21 Jun 2022 01:35:40 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A40D21E10 for ; Mon, 20 Jun 2022 22:35:38 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id y13-20020a17090a154d00b001eaaa3b9b8dso12251126pja.2 for ; Mon, 20 Jun 2022 22:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/HCZkBQUvOL343dE4cxY4+++wGcoTs8rO+O+El91LTM=; b=Rc1d9eGfF4WEdSZlKQhtkTLBRFfr7o73ZnrZPhLPC5EYUqBV9r1tSIy07G4NGvSTT+ KFzTXqZGez06AzLYvAGKweqCnjPVnd+tYQwMmrsgpBM5VL1ePGDEK/j7f1whykasndKa BSzdwFZX7yjiPKfg7btRIQm00jV5ngbjst5oQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/HCZkBQUvOL343dE4cxY4+++wGcoTs8rO+O+El91LTM=; b=NpU5AHffGP1HuwoGPnkh8r4zEPcPfN4XrU/rQQGih3u5cGfOqe3wlEM5hjDVoWjwmb +U9EdYBcq74xKl+y4s4AaVDlMeFK5sG4luXYRfI7cvKe6s9qv0/nUp8E2a1OSPu7EKr6 aoI3ZkGaBthMJ8HBKOjJqxqrxitstj+Ak4ZusbePdQpj4wtQ+CpPJ3xHD2E2t4d4LArX OE5/6u9mO7EGkq58qzyFSYwsIARE2AapBjmnRklzk/K8gin+Z0ozib03dep35XIabn1Z JorqNqRhyHXqPlt/BhAkZoyU7bmN/mBKXmJYdT/ojJhMjS6gupQwvAAN/UTbmxKfl1Tx /UjA== X-Gm-Message-State: AJIora+TpSAKcJCasoKN0heV31Sfc1aD7m413kLYAOEtbltAtuKzIc1l /DoGr6qxPDCu2GykB2RXTVPnbd8WEDrCFQ== X-Google-Smtp-Source: AGRyM1sm6apulC6zBjrM5ofpgu5csFNRtAA/vSsXhmGvna+BHWbI+wABgZn04uxXqqDMd6UQ1vSQ5w== X-Received: by 2002:a17:90b:4b0a:b0:1e3:1823:ca9f with SMTP id lx10-20020a17090b4b0a00b001e31823ca9fmr42328994pjb.12.1655789737471; Mon, 20 Jun 2022 22:35:37 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id k7-20020a63ab47000000b00408af01cb42sm10061676pgp.81.2022.06.20.22.35.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 22:35:37 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Stephen Boyd , Alexandru M Stan , Douglas Anderson , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 2/5] arm64: dts: qcom: sc7180: Add quackingstick dts files Date: Mon, 20 Jun 2022 22:33:48 -0700 Message-Id: <20220620223345.v9.2.I0977b1a08830d0caa8bfb1bdedb4ecceac709a7f@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220621053351.650431-1-joebar@chromium.org> References: <20220621053351.650431-1-joebar@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Quackingstick is a trogdor-based board. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with downstream bits removed. Signed-off-by: Joseph S. Barrera III --- (no changes since v8) Changes in v8: - Incorporate the deletion of the usb_c1 node from 9f9fb70a7294. Changes in v7: - Restore changes requested by Doug. - Only include sc7180.dtsi in sc7180-trogdor.dtsi (19794489fa24). - Simplify spi0/spi6 labeling (d277cab7afc7). - Simplify trackpad enabling (51d30402be75). Changes in v6: - Accidentally deleted changes requested by Doug. Changes in v5: - Remove extra newline - Add comment that compatible will be filled in per-board Changes in v4: - Add missing version history Changes in v3: - First inclusion in this series arch/arm64/boot/dts/qcom/Makefile | 2 + .../sc7180-trogdor-quackingstick-r0-lte.dts | 38 +++ .../qcom/sc7180-trogdor-quackingstick-r0.dts | 26 ++ .../qcom/sc7180-trogdor-quackingstick.dtsi | 318 ++++++++++++++++++ 4 files changed, 384 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r= 0-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r= 0.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.d= tsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index e4114e22548a..7268086f66e8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-quackingstick-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-quackingstick-r0-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev0-boe.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev0-inx.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-wormdingler-rev1-boe.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.d= ts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts new file mode 100644 index 000000000000..35e8945fc56d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 =3D> 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick-r0.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model =3D "Google Quackingstick (rev0+) with LTE"; + compatible =3D "google,quackingstick-sku1536", "qcom,sc7180"; +}; + +&ap_sar_sensor { + compatible =3D "semtech,sx9324"; + semtech,ph0-pin =3D <3 1 3>; + semtech,ph1-pin =3D <2 1 2>; + semtech,ph2-pin =3D <3 3 1>; + semtech,ph3-pin =3D <1 3 3>; + semtech,ph01-resolution =3D <1024>; + semtech,ph23-resolution =3D <1024>; + semtech,startup-sensor =3D <1>; + semtech,ph01-proxraw-strength =3D <3>; + semtech,ph23-proxraw-strength =3D <3>; + semtech,avg-pos-strength =3D <256>; + + /delete-property/ svdd-supply; + vdd-supply =3D <&pp1800_prox>; +}; + +&ap_sar_sensor_i2c { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts new file mode 100644 index 000000000000..5c81e44ed4a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x601 =3D> 1537 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick.dtsi" + +/ { + model =3D "Google Quackingstick (rev0+)"; + compatible =3D "google,quackingstick-sku1537", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top =3D /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-rescode-offset-bot =3D /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-drive-ldo-level =3D <375>; +}; + +&panel { + compatible =3D "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/a= rch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi new file mode 100644 index 000000000000..574b78eb4f28 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + ppvar_lcd: ppvar-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_lcd"; + + gpio =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ppvar_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + v1p8_disp: v1p8-disp { + compatible =3D "regulator-fixed"; + regulator-name =3D "v1p8_disp"; + + gpio =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pp1800_disp_on>; + + vin-supply =3D <&pp3300_a>; + }; +}; + +&backlight { + pwms =3D <&cros_ec_pwm 0>; +}; + +&camcc { + status =3D "okay"; +}; + +&dsi0 { + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg =3D <0>; + enable-gpios =3D <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd_rst>; + avdd-supply =3D <&ppvar_lcd>; + pp1800-supply =3D <&v1p8_disp>; + pp3300-supply =3D <&pp3300_dx_edp>; + backlight =3D <&backlight>; + rotation =3D <270>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + panel_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; + clock-frequency =3D <400000>; + + ap_ts: touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <9 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms =3D <20>; + hid-descr-addr =3D <0x0001>; + + vdd-supply =3D <&pp3300_ts>; + }; +}; + +&sdhc_2 { + status =3D "okay"; +}; + +&pp1800_uf_cam { + status =3D "okay"; +}; + +&pp1800_wf_cam { + status =3D "okay"; +}; + +&pp2800_uf_cam { + status =3D "okay"; +}; + +&pp2800_wf_cam { + status =3D "okay"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins =3D "gpio67"; + }; + + pinconf { + pins =3D "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names =3D "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "", + "", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "SD_CD_ODL", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "PP1800_DISP_ON", + "LCD_RST", + "PPVAR_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + lcd_rst: lcd-rst { + pinmux { + pins =3D "gpio87"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio87"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + ppvar_lcd_en: ppvar-lcd-en { + pinmux { + pins =3D "gpio88"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio88"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + pp1800_disp_on: pp1800-disp-on { + pinmux { + pins =3D "gpio86"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio86"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.31.0 From nobody Sun Apr 26 08:21:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE997C433EF for ; Tue, 21 Jun 2022 05:35:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345318AbiFUFfv (ORCPT ); Tue, 21 Jun 2022 01:35:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344382AbiFUFfm (ORCPT ); Tue, 21 Jun 2022 01:35:42 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20E5F21E28 for ; Mon, 20 Jun 2022 22:35:40 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id q140so12111634pgq.6 for ; Mon, 20 Jun 2022 22:35:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mr7cpuqmRn6xpaNrj0168JJ9U51NmQAWQUP19BgumiU=; b=M25eIGtflDF6vpDzQphXIkpeUIYdc+hIfRGepH8xAPaOCGfFS4y+9ga/xWp+bpdFyJ pxQ56zgOmn77/2mluGl7W5pyqP8ZO2bnT8R2YMumgz8CSODhpwmyTHX7ZID/oyeREN3a r8sizf92J6ZFiAjX+j7Gki5el8v3BjUFmXO9o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mr7cpuqmRn6xpaNrj0168JJ9U51NmQAWQUP19BgumiU=; b=KUAPE7iiDTdwtOnapEB0fYnoyVz0ef8SNgHiMlcVRMfx5FwvzWLOFDISE75HadG4kB kQShy5tNwbPVUA97Z+HVxhdFFsD5GFYMotG/vpK5yZRpKdFVMZks+Jg16tAkpbhRjEBb MuziYFXG+9uqlF9Y7lmFaRMDLQmlk53YaOrydBEIoFaq61yv3b/fZWFqHxDtSlIEWBaU /ipe9sGaHrRbhYh7a7ePQx8dt1ADbOT/BTb5GepujIUCP/LOWrDklImWTcsh1F8SOQYy J1fWqzzoRLqiGu+9mb6oXQxmAigkIySsB1RB33Bd6GoXqFC/OdZC/WF6mLQmR70Mnzqq 1nIQ== X-Gm-Message-State: AJIora/QSPGQmX8wY8IYFx2npU4IzMojjrSJDb/GtfUa6k5JNXSiBhsH 5mf3Oftl8ZhPBGgxjGS6duT06YthZefeMQ== X-Google-Smtp-Source: AGRyM1sKiNCr9wo6OiAP+abgdfm9ByOFLSfK3Ky459A42M/fL6qODyYaySFvG/ImFcnUmK+5AzshRA== X-Received: by 2002:a63:ff0c:0:b0:3fd:29dd:c478 with SMTP id k12-20020a63ff0c000000b003fd29ddc478mr24429571pgi.291.1655789738983; Mon, 20 Jun 2022 22:35:38 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id k7-20020a63ab47000000b00408af01cb42sm10061676pgp.81.2022.06.20.22.35.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 22:35:38 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Stephen Boyd , Alexandru M Stan , Douglas Anderson , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 3/5] arm64: dts: qcom: sc7180: Add mrbland dts files Date: Mon, 20 Jun 2022 22:33:49 -0700 Message-Id: <20220620223345.v9.3.I71176ebf7e5aebddb211f00e805b32c08376d1be@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220621053351.650431-1-joebar@chromium.org> References: <20220621053351.650431-1-joebar@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mrbland is a trogdor-based board. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with downstream bits removed. Signed-off-by: Joseph S. Barrera III --- (no changes since v7) Changes in v7: - Restore mrbland patch. - Only include sc7180.dtsi in sc7180-trogdor.dtsi (19794489fa24). - Simplify spi0/spi6 labeling (d277cab7afc7). - Simplify trackpad enabling (51d30402be75). Changes in v6: - Remove mrbland patch. Changes in v5: - Replace _ in node name with - - Order nodes by name. - Add comment that compatible will be filled in per-board. Changes in v4: - Add missing version history Changes in v2: - Add word wrapping to patch description. - Remove "Author" from patch description. - Fix whitespace around "en_pp3300_dx_edp". arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcom/sc7180-trogdor-mrbland-rev0-auo.dts | 22 ++ .../qcom/sc7180-trogdor-mrbland-rev0-boe.dts | 22 ++ .../dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 53 +++ .../qcom/sc7180-trogdor-mrbland-rev1-auo.dts | 22 ++ .../qcom/sc7180-trogdor-mrbland-rev1-boe.dts | 24 ++ .../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 344 ++++++++++++++++++ 7 files changed, 491 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-au= o.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-bo= e.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dt= si create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-au= o.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-bo= e.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 7268086f66e8..5cfd6316768c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limoze= en-r9.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev0-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev1-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts new file mode 100644 index 000000000000..2767817fb053 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 =3D> 0 + * - bits 7..4: Panel ID: 0x0 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model =3D "Google Mrbland rev0 AUO panel board"; + compatible =3D "google,mrbland-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible =3D "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts new file mode 100644 index 000000000000..711485574a03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 =3D> 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model =3D "Google Mrbland rev0 BOE panel board"; + compatible =3D "google,mrbland-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible =3D "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/ar= ch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi new file mode 100644 index 000000000000..7bc8402c018e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +&avdd_lcd { + gpio =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios =3D <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ +&avdd_lcd_en { + pinmux { + pins =3D "gpio80"; + }; + + pinconf { + pins =3D "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins =3D "gpio81"; + }; + + pinconf { + pins =3D "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins =3D "gpio76"; + }; + + pinconf { + pins =3D "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts new file mode 100644 index 000000000000..275313ef7554 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 =3D> 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model =3D "Google Mrbland rev1+ AUO panel board"; + compatible =3D "google,mrbland-sku1536", "qcom,sc7180"; +}; + +&panel { + compatible =3D "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts new file mode 100644 index 000000000000..87c6b6c30b5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x300 =3D> 768 + * - bits 11..8: Panel ID: 0x3 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model =3D "Google Mrbland (rev1 - 2) BOE panel board"; + /* Uses ID 768 on rev1 and 1024 on rev2+ */ + compatible =3D "google,mrbland-sku1024", "google,mrbland-sku768", + "qcom,sc7180"; +}; + +&panel { + compatible =3D "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/ar= m64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi new file mode 100644 index 000000000000..33d1d8a29038 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + avdd_lcd: avdd-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd_lcd"; + + gpio =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&avdd_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "avee_lcd"; + + gpio =3D <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&avee_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + v1p8_mipi: v1p8-mipi { + compatible =3D "regulator-fixed"; + regulator-name =3D "v1p8_mipi"; + + gpio =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_1800_en>; + + vin-supply =3D <&pp3300_a>; + }; +}; + +&backlight { + pwms =3D <&cros_ec_pwm 0>; +}; + +&camcc { + status =3D "okay"; +}; + +&dsi0 { + + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg =3D <0>; + enable-gpios =3D <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_reset_1800>; + avdd-supply =3D <&avdd_lcd>; + avee-supply =3D <&avee_lcd>; + pp1800-supply =3D <&v1p8_mipi>; + pp3300-supply =3D <&pp3300_dx_edp>; + backlight =3D <&backlight>; + rotation =3D <270>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + panel_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; + clock-frequency =3D <400000>; + + ap_ts: touchscreen@5d { + compatible =3D "goodix,gt7375p"; + reg =3D <0x5d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios =3D <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&pp3300_ts>; + }; +}; + +&pp1800_uf_cam { + status =3D "okay"; +}; + +&pp1800_wf_cam { + status =3D "okay"; +}; + +&pp2800_uf_cam { + status =3D "okay"; +}; + +&pp2800_wf_cam { + status =3D "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant =3D "GO_MRBLAND"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio =3D <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins =3D "gpio85"; + }; + + pinconf { + pins =3D "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names =3D "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins =3D "gpio88"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio88"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins =3D "gpio21"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio21"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins =3D "gpio86"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio86"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins =3D "gpio87"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio87"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.31.0 From nobody Sun Apr 26 08:21:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C3F9C43334 for ; Tue, 21 Jun 2022 05:35:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345340AbiFUFfy (ORCPT ); Tue, 21 Jun 2022 01:35:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343970AbiFUFfm (ORCPT ); Tue, 21 Jun 2022 01:35:42 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC83321E29 for ; Mon, 20 Jun 2022 22:35:40 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id y13-20020a17090a154d00b001eaaa3b9b8dso12251126pja.2 for ; Mon, 20 Jun 2022 22:35:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xXd1KzPN8325jLEKqOHa0b97rFoJeR8zNzYO50dB/a0=; b=E8H0HEG0SkeqLSPJ5+Xw3E9cZxyrmj0Nbd1K1Fa2wAnuJnzVbtu1o/pnQg/CdLqZCC f9hqYL537CXY/WAhu5F8n85FuyPvxwkQCPWU6CotlqEyvtDb1GbJBEhF0dVr+zayK84X rme/A/zVPD2oNfqmRY5mULRjX7t+WieQ8l0Bc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xXd1KzPN8325jLEKqOHa0b97rFoJeR8zNzYO50dB/a0=; b=rFxT5gzO1mIYi/XS3/PR9M/u8U1qEBe0FZR32L/eYpi5j5kF4JsupzTtg3zuxAcNAd NP7oBt8NNjf6Hm7LJ6sZOW2XoJ4DSCguVYwbfV5k/RWbfjDoHfhbYTGw2epttO5ypV+N N4npQzsIs/OlGSWassW9k5nswLG0f139aXTpUEhTA5HgnZb7CTc7g1lkwiiXArw2UNcf 4dopub7xg5Szj5QCA5AF9+pPeSaniy5DBLu2RjlgRqYGA/qZitHWg6RxasPmt4kukmat qwCU03xH33rI73W219+ak1Myl4yiTd0W+VkNAJu9I2z5d/5w+s9lPddN5Uhn9FvNOlIN gobQ== X-Gm-Message-State: AJIora9+V2iwhf1S0IFmKs0RjhZeV1KoKocKH58J1P7Swq/+1MwwFhpj bspK+PLWXGnedHLcY98hVyXitJYsZ3l78w== X-Google-Smtp-Source: AGRyM1tuIfAE7/FnfAc3YajmkxHscQMyRYRW+ACuiMAk2eTVzdQlHZlXlRpWcB6uB9j3aIgtsmUwew== X-Received: by 2002:a17:90b:4f4a:b0:1e3:49c9:aab0 with SMTP id pj10-20020a17090b4f4a00b001e349c9aab0mr41780809pjb.223.1655789740306; Mon, 20 Jun 2022 22:35:40 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id k7-20020a63ab47000000b00408af01cb42sm10061676pgp.81.2022.06.20.22.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 22:35:39 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Stephen Boyd , Alexandru M Stan , Douglas Anderson , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 4/5] arm64: dts: qcom: sc7180: Add pazquel dts files Date: Mon, 20 Jun 2022 22:33:50 -0700 Message-Id: <20220620223345.v9.4.I41e2c2dc12961fe000ebc4d4ef6f0bc5da1259ea@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220621053351.650431-1-joebar@chromium.org> References: <20220621053351.650431-1-joebar@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Pazquel is a trogdor-based board. These dts files are unchanged copies from the downstream Chrome OS 5.4 kernel. Signed-off-by: Joseph S. Barrera III --- Changes in v9: - Restore two lines accidentally removed from ap_sar_sensor. - Simplify trackpad enabling (51d30402be75). Changes in v7: - Only include sc7180.dtsi in sc7180-trogdor.dtsi (19794489fa24). - Simplify spi0/spi6 labeling (d277cab7afc7). - Remove #include of . - Accidentally removed two lines from ap_sar_sensor. Changes in v6: - Copy changes to ap_sar_sensor from v5.4. - Add #include of . Changes in v4: - Fix description (no downstream bits removed). - Add missing version history. Changes in v3: - First inclusion in series. arch/arm64/boot/dts/qcom/Makefile | 4 + .../sc7180-trogdor-pazquel-lte-parade.dts | 22 ++ .../qcom/sc7180-trogdor-pazquel-lte-ti.dts | 22 ++ .../qcom/sc7180-trogdor-pazquel-parade.dts | 17 ++ .../dts/qcom/sc7180-trogdor-pazquel-ti.dts | 17 ++ .../boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 221 ++++++++++++++++++ 6 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-par= ade.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.= dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.= dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5cfd6316768c..dc26704dfe34 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -79,6 +79,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev0= -auo.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev0-boe.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev1-auo.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pazquel-lte-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pazquel-lte-ti.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pazquel-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pazquel-ti.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts= b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts new file mode 100644 index 000000000000..ecedab8d1662 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model =3D "Google Pazquel (Parade,LTE)"; + compatible =3D "google,pazquel-sku4", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts b/a= rch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts new file mode 100644 index 000000000000..7863191d92f5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model =3D "Google Pazquel (TI,LTE)"; + compatible =3D "google,pazquel-sku0", "google,pazquel-sku2", "qcom,sc7180= "; +}; + +&ap_sar_sensor_i2c { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts b/a= rch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts new file mode 100644 index 000000000000..fc53b221b3b6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model =3D "Google Pazquel (Parade)"; + compatible =3D "google,pazquel-sku5", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts b/arch/= arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts new file mode 100644 index 000000000000..4431b83c2acb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model =3D "Google Pazquel (TI)"; + compatible =3D "google,pazquel-sku1", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/ar= m64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi new file mode 100644 index 000000000000..5485f50f89ad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +#include "sc7180-trogdor.dtsi" + +&ap_sar_sensor { + compatible =3D "semtech,sx9324"; + semtech,ph0-pin =3D <1 3 3>; + semtech,ph1-pin =3D <3 1 3>; + semtech,ph2-pin =3D <1 3 3>; + semtech,ph3-pin =3D <0 0 0>; + semtech,ph01-resolution =3D <1024>; + semtech,ph23-resolution =3D <1024>; + semtech,startup-sensor =3D <1>; + semtech,ph01-proxraw-strength =3D <3>; + semtech,ph23-proxraw-strength =3D <1>; + semtech,avg-pos-strength =3D <128>; + semtech,input-analog-gain =3D <0>; + semtech,cs-idle-sleep =3D "gnd"; + + /delete-property/ svdd-supply; + vdd-supply =3D <&pp1800_prox>; +}; + +/delete-node/&trackpad; +&ap_tp_i2c { + trackpad: trackpad@15 { + status =3D "okay"; + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tp_int_odl>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply =3D <&pp3300_fp_tp>; + post-power-on-delay-ms =3D <100>; + hid-descr-addr =3D <0x0001>; + + wakeup-source; + }; +}; + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible =3D "edp-panel"; +}; + +&pp3300_dx_edp { + gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&en_pp3300_dx_edp { + pinmux { + pins =3D "gpio67"; + }; + + pinconf { + pins =3D "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names =3D "TP_INT_ODL", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "", + "", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; --=20 2.31.0 From nobody Sun Apr 26 08:21:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7CB0C433EF for ; Tue, 21 Jun 2022 05:36:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345371AbiFUFgA (ORCPT ); Tue, 21 Jun 2022 01:36:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345243AbiFUFfn (ORCPT ); Tue, 21 Jun 2022 01:35:43 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D5DB21E32 for ; Mon, 20 Jun 2022 22:35:42 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id i8-20020a17090aee8800b001ecc929d14dso679418pjz.0 for ; Mon, 20 Jun 2022 22:35:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DU5fNNWXPYhNYwE/lt4TzVrSslQtW1sH0pS8VT3mUe4=; b=V1aVo0F+hLQz5DkiDdx6+8MFZfPeIdkr6uGkQUXvfEb8iwC1e2dGqcJT5DePaMFM2e MMC0Clkv2wiraOnPJOxAfnipUVLaOYE6V/S6783xPchvgH9xN/+cILgvs7zR/OH1FjwT RM3fw2y1qIBYy53/Hw4xM1OXeX8A7gBBsNHmE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DU5fNNWXPYhNYwE/lt4TzVrSslQtW1sH0pS8VT3mUe4=; b=T6qTzzZyfEWfyAEKO3zET5SS7sp8tfRHKrs/ouWmDyDilWsLggIkdCsrDcrw50W/3R KhbfrBxNPBWiZzZNRiuUY9Z6kPTYvYAuePpdV9wJCoQGwFZxrTpHarMEe8bi3KnqRqFD 5F/nQIPz6zQublk0J4L2zgAL3uSQk2hMjg7Qs58Ipwe43Qk6VTVypvo6PD6Mkme5nPEZ HfLhIQp8rsXpzGn90n6hQsIf+JUk5S3A/bN8LfC3YHgeHGrlvCMb9O+lq6KNviLVKwNm THTrPSZG2c21AbzDKfNCXMcWh6pl5FDb3ch/S3Xhu2pTcUIeiw8tBwk/xzXSbWJoLxzq AC8g== X-Gm-Message-State: AJIora+vy0d+bfQYriaQAFr0R7wEYrJn4ePq7eL/CfqVHEMwPAQhMG1h 0cNJn+qb7r882IO4JU9uWBZRykd0dDygFg== X-Google-Smtp-Source: AGRyM1vDyVVoCHuwAkTocq2fs04cgzgt0HD90UQ04mcql8E3CuEXBqCcPFm6LjBcbkzKr1Uo45Dtjw== X-Received: by 2002:a17:902:e889:b0:16a:3c79:f92f with SMTP id w9-20020a170902e88900b0016a3c79f92fmr369757plg.51.1655789741555; Mon, 20 Jun 2022 22:35:41 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id k7-20020a63ab47000000b00408af01cb42sm10061676pgp.81.2022.06.20.22.35.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 22:35:41 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Stephen Boyd , Alexandru M Stan , Douglas Anderson , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v9 5/5] arm64: dts: qcom: sc7180: Add kingoftown dts files Date: Mon, 20 Jun 2022 22:33:51 -0700 Message-Id: <20220620223345.v9.5.Ib62291487a664a65066d18a3e83c5428a6d2cc6c@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220621053351.650431-1-joebar@chromium.org> References: <20220621053351.650431-1-joebar@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Kingoftown is a trogdor-based board. These dts files are unchanged copies from the downstream Chrome OS 5.4 kernel. Signed-off-by: Joseph S. Barrera III --- Changes in v9: - Simplify trackpad enabling (51d30402be75). Changes in v7: - Simplify spi0/spi6 labeling (d277cab7afc7). - Remove #include of . Changes in v6: - Add #include of from v5.4. Changes in v4: - Fix description (no downstream bits removed). - Add missing version history. Changes in v2: - First inclusion in series. arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/sc7180-trogdor-kingoftown-r0.dts | 44 ++++ .../dts/qcom/sc7180-trogdor-kingoftown-r1.dts | 17 ++ .../dts/qcom/sc7180-trogdor-kingoftown.dtsi | 224 ++++++++++++++++++ 4 files changed, 287 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.d= ts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.d= ts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index dc26704dfe34..a9f2ad013179 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -60,6 +60,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r3-lte= .dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-homestar-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-kingoftown-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-kingoftown-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/ar= ch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts new file mode 100644 index 000000000000..85aec1be98fc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model =3D "Google Kingoftown (rev0)"; + compatible =3D "google,kingoftown-rev0", "qcom,sc7180"; +}; + +/* + * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a + * power rail instead, since kingoftown does not have FP. + */ +&pp3300_fp_tp { + gpio =3D <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_fp_rails>; +}; + +&tlmm { + en_fp_rails: en-fp-rails { + pinmux { + pins =3D "gpio74"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio74"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts b/ar= ch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts new file mode 100644 index 000000000000..2be9138ba89f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model =3D "Google Kingoftown (rev1+)"; + compatible =3D "google,kingoftown", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch= /arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi new file mode 100644 index 000000000000..2268f3e7b5f2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +&alc5682 { + compatible =3D "realtek,rt5682s"; + realtek,dmic1-clk-pin =3D <2>; + realtek,dmic-clk-rate-hz =3D <2048000>; +}; + +&ap_tp_i2c { + status =3D "okay"; +}; + +ap_ts_pen_1v8: &i2c4 { + status =3D "okay"; + clock-frequency =3D <400000>; + + ap_ts: touchscreen@10 { + compatible =3D "elan,ekth3500"; + reg =3D <0x10>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply =3D <&pp3300_ts>; + + reset-gpios =3D <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible =3D "edp-panel"; +}; + +&pp3300_dx_edp { + gpio =3D <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&sound { + compatible =3D "google,sc7180-trogdor"; + model =3D "sc7180-rt5682s-max98357a-1mic"; +}; + +&wifi { + qcom,ath10k-calibration-variant =3D "GO_KINGOFTOWN"; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&en_pp3300_dx_edp { + pinmux { + pins =3D "gpio67"; + }; + + pinconf { + pins =3D "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names =3D "TP_INT_L", /* 0 */ + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", /* 10 */ + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", /* 20 */ + "", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "", + "", /* 30 */ + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", /* 40 */ + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", /* 50 */ + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", /* 60 */ + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", /* 70 */ + "", + "", + "", + "EN_FP_RAILS", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", /* 80 */ + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", /* 90 */ + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", /* 100 */ + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", /* 110 */ + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; --=20 2.31.0