From nobody Fri Apr 24 12:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00DFEC43334 for ; Mon, 20 Jun 2022 15:54:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243037AbiFTPy2 (ORCPT ); Mon, 20 Jun 2022 11:54:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbiFTPyV (ORCPT ); Mon, 20 Jun 2022 11:54:21 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9F531D31E; Mon, 20 Jun 2022 08:54:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 782936148E; Mon, 20 Jun 2022 15:54:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06C44C3411B; Mon, 20 Jun 2022 15:54:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655740458; bh=KtWEptVGxksrRg8rkZA74nxyhIwgcnJ5Ar0DUkK8+cU=; h=From:To:Cc:Subject:Date:From; b=qx2jdZwEvDyPwpqdHbgZT83fAScKchJVA1I0Tqdy1L7kg4seMsOcQbc5gu3CtaoRP cMGNxS38aQ28PMoBkV9A0OB6mXBKLBk78S04Kv1mZUCyHfTrCk6IGW4shlVH4uqt0S 2QjSTdWJY0zULwQet5tKN6yxmQI2qtoGTpJQkF0ObHdMoex4VbkrOFk6Ys4nZxqu7j LHVFDxBG5qHZ/e6sVmX5vMdgvvJlVdWgphrDHAdJJ87e84knmIIau/yhYn2VPSP5O+ ySoD0xfMosUjdKibAzrz8LeUSc42wVpP8thvbrr6IOPpELL0DhpZ3113Apgqx+YI9j AtvkTFucEMT/g== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, peterz@infradead.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren Subject: [PATCH V5] riscv: Add qspinlock support Date: Mon, 20 Jun 2022 11:54:04 -0400 Message-Id: <20220620155404.1968739-1-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guo Ren Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9 ("asm-generic: qspinlock: Indicate the use of mixed-size atomics"). - RISC-V atomic_*_release()/atomic_*_acquire() are implemented with own relaxed version plus acquire/release_fence for RCsc synchronization. - RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions). Some riscv cores such as BOOMv3 & XiangShan could provide strict & strong forward guarantee (The cache line would be kept in an exclusive state for Backoff cycles, and only this core's interrupt could break the LR/SC pair). - RISC-V could provide cheap atomic_fetch_or_acquire() with RCsc. - RISC-V only provides relaxed xhg16 to support qspinlock. The first version of patch was made in 2019.1 [1]. The second version was made in 2020.11 [2]. [1] https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclar= k@mac.com/#r [2] https://lore.kernel.org/linux-riscv/1606225437-22948-2-git-send-email-g= uoren@kernel.org/ Change V5: - Update comment with RISC-V forward guarantee feature. - Back to V3 direction and optimize asm code. Change V4: - Remove custom sub-word xchg implementation - Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock Change V3: - Coding convention by Peter Zijlstra's advices Change V2: - Coding convention in cmpxchg.h - Re-implement short xchg - Remove char & cmpxchg implementations Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra Cc: Waiman Long Cc: Arnd Bergmann Cc: Palmer Dabbelt Reported-by: kernel test robot --- arch/riscv/Kconfig | 9 +++++++++ arch/riscv/include/asm/Kbuild | 4 ++-- arch/riscv/include/asm/cmpxchg.h | 16 ++++++++++++++++ arch/riscv/include/asm/spinlock.h | 12 ++++++++++++ arch/riscv/include/asm/spinlock_types.h | 12 ++++++++++++ 5 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/include/asm/spinlock.h create mode 100644 arch/riscv/include/asm/spinlock_types.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32ffef9f6e5b..3b0b117b4e95 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -333,6 +333,15 @@ config NODES_SHIFT Specify the maximum number of NUMA Nodes available on the target system. Increases memory reserved to accommodate various tables. =20 +config RISCV_USE_QUEUED_SPINLOCKS + bool "Using queued spinlock instead of ticket-lock" + depends on SMP && MMU + select ARCH_USE_QUEUED_SPINLOCKS + default y if NUMA + help + Make sure your micro arch LL/SC has a strong forward progress guarantee. + Otherwise, stay at ticket-lock. + config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 504f8b7e72d4..e066ccab6417 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -2,10 +2,10 @@ generic-y +=3D early_ioremap.h generic-y +=3D flat.h generic-y +=3D kvm_para.h +generic-y +=3D mcs_spinlock.h generic-y +=3D parport.h -generic-y +=3D spinlock.h -generic-y +=3D spinlock_types.h generic-y +=3D qrwlock.h generic-y +=3D qrwlock_types.h +generic-y +=3D qspinlock.h generic-y +=3D user.h generic-y +=3D vmlinux.lds.h diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 12debce235e5..f7f8e359d3ac 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -17,6 +17,22 @@ __typeof__(new) __new =3D (new); \ __typeof__(*(ptr)) __ret; \ switch (size) { \ + case 2: \ + u32 temp; \ + u32 shif =3D ((ulong)__ptr & 2) ? 16 : 0; \ + u32 mask =3D 0xffff << shif; \ + __ptr =3D (__typeof__(ptr))((ulong)__ptr & ~(ulong)2); \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " and %1, %0, %z3\n" \ + " or %1, %1, %z4\n" \ + " sc.w %1, %1, %2\n" \ + " bnez %1, 0b\n" \ + : "=3D&r" (__ret), "=3D&r" (temp), "+A" (*__ptr) \ + : "rJ" (~mask), "rJ" (__new << shif) \ + : "memory"); \ + __ret =3D (__ret & mask) >> shif; \ + break; \ case 4: \ __asm__ __volatile__ ( \ " amoswap.w %0, %2, %1\n" \ diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spi= nlock.h new file mode 100644 index 000000000000..fd3fd09cff52 --- /dev/null +++ b/arch/riscv/include/asm/spinlock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_SPINLOCK_H +#define __ASM_SPINLOCK_H + +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS +#include +#include +#else +#include +#endif + +#endif /* __ASM_SPINLOCK_H */ diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/a= sm/spinlock_types.h new file mode 100644 index 000000000000..9281237b5f4e --- /dev/null +++ b/arch/riscv/include/asm/spinlock_types.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_SPINLOCK_TYPES_H +#define __ASM_SPINLOCK_TYPES_H + +#ifdef CONFIG_ARCH_USE_QUEUED_SPINLOCKS +#include +#include +#else +#include +#endif + +#endif /* __ASM_SPINLOCK_TYPES_H */ --=20 2.36.1