From nobody Sun Apr 26 09:36:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A8F6CCA47F for ; Sun, 19 Jun 2022 16:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235852AbiFSQuZ (ORCPT ); Sun, 19 Jun 2022 12:50:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234800AbiFSQuW (ORCPT ); Sun, 19 Jun 2022 12:50:22 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AB7963F6 for ; Sun, 19 Jun 2022 09:50:19 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id i81-20020a1c3b54000000b0039c76434147so6687418wma.1 for ; Sun, 19 Jun 2022 09:50:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OdzijZhojJfexvUiHUDLq5z4PsGSFwQ1Ytr2BP9BCIg=; b=PWA4JJOFAtMdKuAwHauf5W0ilkam9+c284EfGOoeFfBxf73/U3WhmRonRDLM9YkFq7 bXrvdq1MvbW4jcJQNEfv99schOsEgU8AxXsLtq8HqNmK8RTgB+WPs3prQdtrSpXphsv3 PDKpjD2sE+YGBKavd99Z/4KdZH8b+vD/EGw1aMT/nhcIx17IdEMnfi0klW+QvxETCrdu ufR/+VR5poo6Nnp+w5yM2u4joLnHecINMOecWblxkbCXSka3zerwe2DdgAGjrgl063bq OeLVMsyhBjIQnxfYid1cwKIYct0v1Lb4aYeptnBNQIH+0Ki8ewyuz2pi/YMcTgDZS6VM So3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OdzijZhojJfexvUiHUDLq5z4PsGSFwQ1Ytr2BP9BCIg=; b=IquOo+EXH2nnAlDQ6Ef+u+AUkcg0AgQK0h6BlKauLvavzhpufKmEDgm7YESioNrwOz zKjsPrNoB4T51JQ1RQyD6g7Kio0orJW4PKk3Fam5aqyeHeSAZMaGsoVOY04++0gZ2I4z kaY6sf0Yb+yPUIj/Aq4X2V2hURWBe6LekTsQ3AFsDwjEubxvhc6CLSkm6nhE744ZqrrT 0tRZsdMbWK8D8xBuzcI0AtbjeuLkfdrwKfTrKsMwEuAgDF5FQ71BKyliblNwz5eYjzrp 0VUEaB9j3HvJ9hKnJhFVvZlFF4U6rQE8+C212fyb/MN+4EjU5yuNeP2H0krUYsZDNvA+ sOgQ== X-Gm-Message-State: AOAM533/pNUvnSBXgmjMKe2rMzA8BfolaLKpQi/mgCP1j4a6upEQNueX xokOQNVi7xvOfgkF62rd11oHiyLQvaViSAlvwis= X-Google-Smtp-Source: ABdhPJz0xPBZmWQTo9K8KRhE/AtjcNNKaUjJZKnJFvDuhZ5Qur5cAWc+N3xl1u+1XObV9D2uRhHE6g== X-Received: by 2002:a05:600c:3048:b0:39c:4c03:d54f with SMTP id n8-20020a05600c304800b0039c4c03d54fmr30692648wmh.89.1655657418512; Sun, 19 Jun 2022 09:50:18 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:17 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 1/6] dt-bindings: clk: microchip: mpfs: add reset controller support Date: Sun, 19 Jun 2022 17:49:31 +0100 Message-Id: <20220619164935.1492823-2-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "peripheral" devices on PolarFire SoC can be put into reset, so update the device tree binding to reflect the presence of a reset controller. Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/= Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 016a4f378b9b..1d0b6a4fda42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -40,8 +40,21 @@ properties: const: 1 description: | The clock consumer should specify the desired clock by having the cl= ock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/micro= chip,mpfs-clock.h - for the full list of PolarFire clock IDs. + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so = from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st of + PolarFire clock IDs. + const: 1 =20 required: - compatible --=20 2.36.1 From nobody Sun Apr 26 09:36:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B4BCCA481 for ; Sun, 19 Jun 2022 16:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236231AbiFSQu2 (ORCPT ); Sun, 19 Jun 2022 12:50:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229490AbiFSQuW (ORCPT ); Sun, 19 Jun 2022 12:50:22 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB23963A3 for ; Sun, 19 Jun 2022 09:50:21 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id h14-20020a1ccc0e000000b0039eff745c53so488047wmb.5 for ; Sun, 19 Jun 2022 09:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S1wp9fg7GLV3pi+6N9b23chCh97u+d99m5VcERi7ehs=; b=bPnyXKWN64AHnZToeVUO26HMas9/tkxyQqtdLVRhdC+buVatlHnFMXdVVxgkESp/A0 /1fXdPu57m3R1lk+dB2zygAbwZRjSH4KVqkRLvwHDPruj9h14mCjz2zVNu3s5f1awmS0 ewXdPp8hughiHf3N7oWAaA4pNA75h6XO7zS/+w73bY7EoxpqSF1ormze50BhwXH2jj3L lQ5rnsJPdJa6O/VqkNvxSArJLsPmkZh9EP+It4o5yFg+rUYq0lsu6Hm0KD3QL1a+1ofC SMMoEZEFRu5ys/E9neTRnaJM+st+vUuX/9TzcjuY54aS9fckKvnumpv3lIJCcqy4HozJ EAaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S1wp9fg7GLV3pi+6N9b23chCh97u+d99m5VcERi7ehs=; b=flkuUN/JpqZ1Y/YVfyD/SYyBWK1hwZHYVJFlvOKkLBgQuEuPtWa6ax4u7DswxiQoRi 0pXpWao3SdejVn68+vjcqTJ9dmf4klmRDL5msfPUgI9K26ILoHzSmUNAYl/SkXbqt5Ml 3LkhkVgXRRocguGz8KVm28vNfAkwEg10aeZ4A8KDrf0C4tFG2Sop98rJ4zf10EOb8/XB ed/+Qqw51EoRPRNWQjMM+pfTkapf39drws3QRKkqS5pYUPwBarA7DfhJ1AEDKIdH6H/k DRUpFWFoXTLnQLjqAof1M0ZZ2KStCHgFXTHROrYKo0im8Py7CexBDMcwvHLZkotGJtBQ D8tw== X-Gm-Message-State: AJIora+OdtHU6ye82mzvwf88Q3RMNWSA/hD9xMFPqAHGrw56oyapcrnr 8JcaRRIEuE6E9ZeXLD4TSOPItA== X-Google-Smtp-Source: AGRyM1uF0ceBCoDGb8f7820OuMYLUviRQuhZsDcnfdtER4rIoj2V0+8xcQxMV4x24fp4JC4HNI8OQw== X-Received: by 2002:a05:600c:3d18:b0:39c:474c:eb with SMTP id bh24-20020a05600c3d1800b0039c474c00ebmr20396587wmb.87.1655657419809; Sun, 19 Jun 2022 09:50:19 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:19 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 2/6] dt-bindings: net: cdns,macb: document polarfire soc's macb Date: Sun, 19 Jun 2022 17:49:32 +0100 Message-Id: <20220619164935.1492823-3-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Until now the PolarFire SoC (MPFS) has been using the generic "cdns,macb" compatible but has optional reset support. Add a specific compatible which falls back to the currently used generic binding. Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documen= tation/devicetree/bindings/net/cdns,macb.yaml index 86fc31c2d91b..9c92156869b2 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -28,6 +28,7 @@ properties: - enum: - cdns,at91sam9260-macb # Atmel at91sam9 SoCs - cdns,sam9x60-macb # Microchip sam9x60 SoC + - microchip,mpfs-macb # Microchip PolarFire SoC - const: cdns,macb # Generic =20 - items: --=20 2.36.1 From nobody Sun Apr 26 09:36:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B507C43334 for ; Sun, 19 Jun 2022 16:50:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236199AbiFSQuc (ORCPT ); Sun, 19 Jun 2022 12:50:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235667AbiFSQuX (ORCPT ); Sun, 19 Jun 2022 12:50:23 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5617B63C5 for ; Sun, 19 Jun 2022 09:50:22 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id s1so11655755wra.9 for ; Sun, 19 Jun 2022 09:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2U26d1RUDN40F8pXZDx2og6vajjIrs72J5qYfLoOCUY=; b=a/KqKSDua/YhHcpIKxVc8N8J0GVZLdyKnxxK3no+G+TEd54zlxZbnLXf6+9OWzvsxq DOd0uguBWie7LqV06kD7ZewrXbZPCniZgbyif/L35ANFqGvpRp3UwzXxwM1ScFl1R0+R 28pxiiOS0ZDKMTZk0Qk2yfnP6ng/hJ5fwURg02GE+LwyOBgbhADUjLuaQv4os/xaHTBT IFzNk/9XQwZJ/2Tno4ftGaxnf95/ShVfH4KNIDRQFq9WF/zVnQWNH1uLrncHDmAmS3CZ 91gn5GRHKWbHzpo6+ol9JmDwsRhcIqpRtwZLgaOyidCrvd9kWy3GZFXCjX0xopx+CIeq CzyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2U26d1RUDN40F8pXZDx2og6vajjIrs72J5qYfLoOCUY=; b=IO3mHHWEQvaI3NHxIxmDPOycLv+KggaEozmKtmtDWnxoIhT6qJxbqEVng0cpf/7Wk9 PhWYbFPcAe/W2weMBKZxNpQHVNWxesI7/EMATk2wIld7kuPKpjH9Mc+Yt3M3XfqjR2CV 0BAtHFlZ7RXV2Oz1wtUeZw5IP8dLCHvMQiXqX6P2iobUh91kerTbKS2vDSyD7DUYbnQz CziFNYFZr5C4eqvbc23xjM0luyLBWxE5GtBHdUVvw3SFa0p11NKJ4fY+RuRJ1YzOVhXF GQ/2MXvnhw0FkZDShLvjdqMRffhIgzwWhR3EdgkE09jAwI6aFjwZlUvO9lv8XVSjCOkp ILnQ== X-Gm-Message-State: AJIora8/Imx3015Ao2vjZx7dXnzMNJyaJtBypdBzRleLmOeKoT6A0n5E j45Q/y7V1+UgRYtVVLzUMcy88w== X-Google-Smtp-Source: AGRyM1u2F06uLF9I1C9pTm9cF8MTa7GrTptuqR0ZCQFATDOGJcdnLqgdR8SoNllm822PnnzCYlk8BA== X-Received: by 2002:adf:de8d:0:b0:21a:23e0:6881 with SMTP id w13-20020adfde8d000000b0021a23e06881mr18743406wrl.291.1655657420799; Sun, 19 Jun 2022 09:50:20 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:20 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 3/6] clk: microchip: mpfs: add reset controller Date: Sun, 19 Jun 2022 17:49:33 +0100 Message-Id: <20220619164935.1492823-4-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 118 ++++++++++++++++++++++++++++--- include/soc/microchip/mpfs.h | 8 +++ 3 files changed, 116 insertions(+), 11 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index a5a99873c4f5..b46e864b3bd8 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -6,5 +6,6 @@ config COMMON_CLK_PIC32 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST + select AUXILIARY_BUS help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 070c3b896559..19a9f8cd12ff 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -3,12 +3,15 @@ * Daire McNamara, * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. */ +#include "linux/device.h" +#include #include #include #include #include #include #include +#include =20 /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u @@ -28,6 +31,7 @@ #define MSSPLL_FIXED_DIV 4u =20 struct mpfs_clock_data { + struct device *dev; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -302,10 +306,6 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) =20 spin_lock_irqsave(&mpfs_clk_lock, flags); =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val =3D reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); val =3D reg | (1u << periph->shift); writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); @@ -339,12 +339,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *h= w) void __iomem *base_addr =3D periph_hw->sys_base; u32 reg; =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - if ((reg & (1u << periph->shift)) =3D=3D 0u) { - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - if (reg & (1u << periph->shift)) - return 1; - } + reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + if (reg & (1u << periph->shift)) + return 1; =20 return 0; } @@ -438,6 +435,99 @@ static int mpfs_clk_register_periphs(struct device *de= v, struct mpfs_periph_hw_c return 0; } =20 +/* + * Peripheral clock resets + */ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) + +u32 mpfs_reset_read(struct device *dev) +{ + struct mpfs_clock_data *clock_data =3D dev_get_drvdata(dev->parent); + + return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); + +void mpfs_reset_write(struct device *dev, u32 val) +{ + struct mpfs_clock_data *clock_data =3D dev_get_drvdata(dev->parent); + + writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); + +static void mpfs_reset_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev =3D _adev; + + auxiliary_device_delete(adev); +} + +static void mpfs_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev =3D to_auxiliary_dev(dev); + + auxiliary_device_uninit(adev); + + kfree(adev->name); + kfree(adev); +} + +static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_da= ta *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + return ERR_PTR(-ENOMEM); + + adev->name =3D "reset-mpfs"; + adev->dev.parent =3D clk_data->dev; + adev->dev.release =3D mpfs_reset_adev_release; + adev->id =3D 666u; + + ret =3D auxiliary_device_init(adev); + if (ret) { + kfree(adev); + return ERR_PTR(ret); + } + + return adev; +} + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev =3D mpfs_reset_adev_alloc(clk_data); + if (IS_ERR(adev)) + return PTR_ERR(adev); + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + ret =3D devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_ade= v, adev); + if (ret) + return ret; + + return 0; +} + +#else /* !CONFIG_RESET_CONTROLLER */ + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + return 0; +} + +#endif /* !CONFIG_RESET_CONTROLLER */ + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -462,6 +552,8 @@ static int mpfs_clk_probe(struct platform_device *pdev) return PTR_ERR(clk_data->msspll_base); =20 clk_data->hw_data.num =3D num_clks; + clk_data->dev =3D dev; + dev_set_drvdata(dev, clk_data); =20 ret =3D mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_= msspll_clks), clk_data); @@ -481,6 +573,10 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 + ret =3D mpfs_reset_controller_register(clk_data); + if (ret) + return ret; + return ret; } =20 @@ -488,7 +584,7 @@ static const struct of_device_id mpfs_clk_of_match_tabl= e[] =3D { { .compatible =3D "microchip,mpfs-clkcfg", }, {} }; -MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); +MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); =20 static struct platform_driver mpfs_clk_driver =3D { .probe =3D mpfs_clk_probe, diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index 6466515262bd..f916dcde457f 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -40,4 +40,12 @@ struct mpfs_sys_controller *mpfs_sys_controller_get(stru= ct device *dev); =20 #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ =20 +#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) + +u32 mpfs_reset_read(struct device *dev); + +void mpfs_reset_write(struct device *dev, u32 val); + +#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */ + #endif /* __SOC_MPFS_H__ */ --=20 2.36.1 From nobody Sun Apr 26 09:36:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0A2AC433EF for ; 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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:21 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 4/6] reset: add polarfire soc reset support Date: Sun, 19 Jun 2022 17:49:34 +0100 Message-Id: <20220619164935.1492823-5-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Signed-off-by: Conor Dooley --- drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 155 +++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 drivers/reset/reset-mpfs.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..8f7d7cda690d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -122,6 +122,15 @@ config RESET_MCHP_SPARX5 help This driver supports switch core reset for the Microchip Sparx5 SoC. =20 +config RESET_POLARFIRE_SOC + bool "Microchip PolarFire SoC (MPFS) Reset Driver" + depends on AUXILIARY_BUS + default MCHP_CLK_MPFS + help + This driver supports switch core reset for the Microchip PolarFire SoC + + CONFIG_RESET_MPFS + config RESET_MESON tristate "Meson Reset Driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..5fac3a753858 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_RESET_K210) +=3D reset-k210.o obj-$(CONFIG_RESET_LANTIQ) +=3D reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) +=3D reset-lpc18xx.o obj-$(CONFIG_RESET_MCHP_SPARX5) +=3D reset-microchip-sparx5.o +obj-$(CONFIG_RESET_POLARFIRE_SOC) +=3D reset-mpfs.o obj-$(CONFIG_RESET_MESON) +=3D reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) +=3D reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) +=3D reset-npcm.o @@ -38,4 +39,3 @@ obj-$(CONFIG_RESET_UNIPHIER) +=3D reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) +=3D reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) +=3D reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) +=3D reset-zynqmp.o - diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c new file mode 100644 index 000000000000..6c9c10cd9077 --- /dev/null +++ b/drivers/reset/reset-mpfs.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller + * + * Author: Conor Dooley + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * The ENVM reset is the lowest bit in the register & I am using the CLK_F= OO + * defines in the dt to make things easier to configure - so this is accou= nting + * for the offset of 3 there. + */ +#define MPFS_PERIPH_OFFSET CLK_ENVM +#define MPFS_NUM_RESETS 30u + +/* + * Peripheral clock resets + */ + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) +{ + u32 reg; + + reg =3D mpfs_reset_read(rcdev->dev); + reg |=3D (1u << id); + mpfs_reset_write(rcdev->dev, reg); + + dev_dbg(rcdev->dev, + "Asserting reset for device with REG_SUBBLK_RESET_CR index: %u\n", + id); + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) +{ + u32 reg, val; + + reg =3D mpfs_reset_read(rcdev->dev); + val =3D reg & ~(1u << id); + mpfs_reset_write(rcdev->dev, val); + + dev_dbg(rcdev->dev, + "Deasserting device with REG_SUBBLK_RESET_CR index: %u\n", + id); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) +{ + u32 reg =3D mpfs_reset_read(rcdev->dev); + + return (reg & (1u << id)); +} + +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + dev_dbg(rcdev->dev, + "Resetting device with REG_SUBBLK_RESET_CR index: %u\n", + id); + + mpfs_assert(rcdev, id); + + /* Value is stolen from the rcar reset driver, will need changing after R= FC */ + udelay(35); + + mpfs_deassert(rcdev, id); + + return 0; +} + +static const struct reset_control_ops mpfs_reset_ops =3D { + .reset =3D mpfs_reset, + .assert =3D mpfs_assert, + .deassert =3D mpfs_deassert, + .status =3D mpfs_status, +}; + +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int index =3D reset_spec->args[0]; + + /* + * CLK_RESERVED does not map to a clock, but it does map to a reset, + * so it has to be accounted for here. It is the reset for the fabric, + * so if this reset gets called - do not reset it. + */ + if (index =3D=3D CLK_RESERVED) { + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); + return -EINVAL; + } + + if (index < MPFS_PERIPH_OFFSET || index >=3D (MPFS_PERIPH_OFFSET + rcdev-= >nr_resets)) { + dev_err(rcdev->dev, "Invalid reset index %u\n", reset_spec->args[0]); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} + +static int mpfs_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct reset_controller_dev *rcdev; + int ret; + + rcdev =3D devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->dev =3D dev; + rcdev->dev->parent =3D adev->dev.parent; + rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D adev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + ret =3D devm_reset_controller_register(dev, rcdev); + if (!ret) + dev_info(dev, "Registered MPFS reset controller\n"); + + return ret; +} + +static const struct auxiliary_device_id mpfs_reset_ids[] =3D { + { + .name =3D "clk_mpfs.reset-mpfs", + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); + +static struct auxiliary_driver mpfs_reset_driver =3D { + .probe =3D mpfs_reset_probe, + .id_table =3D mpfs_reset_ids, +}; + +module_auxiliary_driver(mpfs_reset_driver); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MCHP_CLK_MPFS); --=20 2.36.1 From nobody Sun Apr 26 09:36:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DCD1CCA480 for ; Sun, 19 Jun 2022 16:50:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236648AbiFSQuj (ORCPT ); Sun, 19 Jun 2022 12:50:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235972AbiFSQuZ (ORCPT ); Sun, 19 Jun 2022 12:50:25 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B7C363C5 for ; Sun, 19 Jun 2022 09:50:24 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id g4so11647697wrh.11 for ; Sun, 19 Jun 2022 09:50:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gopwvsW4YZ7UonEyNdDMzhV85NCQ2TW0QKUGmgQ7L+A=; b=PPRsmuFvXCAnoP528hN1t16BHLynhT/bO2rdEnC0Xz4knixhQo48QsK8CVqIHwVuHt 1MQg+IXAktJOWtHvgZLi01BCJEpfF/f0hjZVEfXIAxarIhHn6jci/o5r56pFckiE8lHO xL59bWW7auYReXeIDVHZsU0rdTbOm3y/6AU5GDj6hfOgM3Z9IUpA6BkY0zdE1EW5fB5f +23QiHLcxNZUnzSIlRpsFejQ2aPd3p1xJe3rpFvVIMpk/4G461je7S5b+gh2lMtMzirn D31QY5/tHoJHPcYQY9eO3U/UXkD5nKSCshArD8i5ieLniTPWojHTEIPDmte7x4BtDIla 3uhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gopwvsW4YZ7UonEyNdDMzhV85NCQ2TW0QKUGmgQ7L+A=; b=CUfssGYreUA1VZC006PTf0UvQmYUWIg/qaje12EmlzQPCZ4sWA8FkCuWdEm0y/gDFQ l1bzYiCwMeVFAAaGj+g4OoJh1rZjBjr6h9m6DOZrpNJ1k1vUkctJydyDEacS+gZ73ola MGfhPCgeB6HtnTS1mj/GXQ0QW1DhaHsh2n7+/76zC0TpRweA3G/cs40EHRK7vmjTkIqq CpPEG7YKfm2V6qUy9anQTgvS/3KrDRN3jP8xCYiZIOt0NMVzDOSCmJO1URQlAFTJfxcN 1UkWkDVeEBdUapszkPN8mUnofoQeWubf1hJah/ggl8jHT3IKlg1gIEX/PwE1tcMxbN4b IthA== X-Gm-Message-State: AJIora/9Tg/1orRP4DyakahD5Ugr/kQmvlQdB6rMfL1w7wPD5LghGUpl QCC5HKr/MU7TBfi6IVx9UA+HWg== X-Google-Smtp-Source: AGRyM1u8/TXPS06SfhDWZfnvfFABhGjitdfgdEIZo8EF7U4BuS6IZE7QVX/Y0ckD0cYHUGtSh+yJwA== X-Received: by 2002:a05:6000:2c7:b0:219:b52d:d122 with SMTP id o7-20020a05600002c700b00219b52dd122mr18399366wry.507.1655657422909; Sun, 19 Jun 2022 09:50:22 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:22 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 5/6] net: macb: add polarfire soc reset support Date: Sun, 19 Jun 2022 17:49:35 +0100 Message-Id: <20220619164935.1492823-6-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley To date, the Microchip PolarFire SoC (MPFS) has been using the cdns,macb compatible, however the generic device does not have reset support. Add a new compatible & .data for MPFS to hook into the reset functionality added for zynqmp support (and make the zynqmp init function generic in the process). Signed-off-by: Conor Dooley --- drivers/net/ethernet/cadence/macb_main.c | 25 +++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index d89098f4ede8..325f0463fd42 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4689,33 +4689,32 @@ static const struct macb_config np4_config =3D { .usrio =3D &macb_default_usrio, }; =20 -static int zynqmp_init(struct platform_device *pdev) +static int init_reset_optional(struct platform_device *pdev) { struct net_device *dev =3D platform_get_drvdata(pdev); struct macb *bp =3D netdev_priv(dev); int ret; =20 if (bp->phy_interface =3D=3D PHY_INTERFACE_MODE_SGMII) { - /* Ensure PS-GTR PHY device used in SGMII mode is ready */ + /* Ensure PHY device used in SGMII mode is ready */ bp->sgmii_phy =3D devm_phy_optional_get(&pdev->dev, NULL); =20 if (IS_ERR(bp->sgmii_phy)) { ret =3D PTR_ERR(bp->sgmii_phy); dev_err_probe(&pdev->dev, ret, - "failed to get PS-GTR PHY\n"); + "failed to get SGMII PHY\n"); return ret; } =20 ret =3D phy_init(bp->sgmii_phy); if (ret) { - dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n", + dev_err(&pdev->dev, "failed to init SGMII PHY: %d\n", ret); return ret; } } =20 - /* Fully reset GEM controller at hardware level using zynqmp-reset driver, - * if mapped in device tree. + /* Fully reset controller at hardware level if mapped in device tree */ ret =3D device_reset_optional(&pdev->dev); if (ret) { @@ -4737,7 +4736,7 @@ static const struct macb_config zynqmp_config =3D { MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH, .dma_burst_length =3D 16, .clk_init =3D macb_clk_init, - .init =3D zynqmp_init, + .init =3D init_reset_optional, .jumbo_max_len =3D 10240, .usrio =3D &macb_default_usrio, }; @@ -4751,6 +4750,17 @@ static const struct macb_config zynq_config =3D { .usrio =3D &macb_default_usrio, }; =20 +static const struct macb_config mpfs_config =3D { + .caps =3D MACB_CAPS_GIGABIT_MODE_AVAILABLE | + MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, + .dma_burst_length =3D 16, + .clk_init =3D macb_clk_init, + .init =3D init_reset_optional, + .usrio =3D &macb_default_usrio, + .jumbo_max_len =3D 10240, +}; + static const struct macb_config sama7g5_gem_config =3D { .caps =3D MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | MACB_CAPS_MIIONRGMII, @@ -4787,6 +4797,7 @@ static const struct of_device_id macb_dt_ids[] =3D { { .compatible =3D "cdns,zynqmp-gem", .data =3D &zynqmp_config}, { .compatible =3D "cdns,zynq-gem", .data =3D &zynq_config }, { .compatible =3D "sifive,fu540-c000-gem", .data =3D &fu540_c000_config }, + { .compatible =3D "microchip,mpfs-macb", .data =3D &mpfs_config }, { .compatible =3D "microchip,sama7g5-gem", .data =3D &sama7g5_gem_config = }, { .compatible =3D "microchip,sama7g5-emac", .data =3D &sama7g5_emac_confi= g }, { /* sentinel */ } --=20 2.36.1 From nobody Sun Apr 26 09:36:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F278BCCA480 for ; Sun, 19 Jun 2022 16:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236706AbiFSQul (ORCPT ); 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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:23 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 6/6] riscv: dts: microchip: add mpfs specific macb reset support Date: Sun, 19 Jun 2022 17:49:36 +0100 Message-Id: <20220619164935.1492823-7-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The macb on PolarFire SoC has reset support which the generic compatible does not use. Add the newly introduced MPFS specific compatible as the primary compatible to avail of this support & wire up the reset to the clock controllers devicetree entry. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 8c3259134194..5a33cbf9467a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -197,6 +197,7 @@ clkcfg: clkcfg@20002000 { reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks =3D <&refclk>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 mmuart0: serial@20000000 { @@ -331,7 +332,7 @@ i2c1: i2c@2010b000 { }; =20 mac0: ethernet@20110000 { - compatible =3D "cdns,macb"; + compatible =3D "microchip,mpfs-macb", "cdns,macb"; reg =3D <0x0 0x20110000 0x0 0x2000>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -340,11 +341,12 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; + resets =3D <&clkcfg CLK_MAC0>; status =3D "disabled"; }; =20 mac1: ethernet@20112000 { - compatible =3D "cdns,macb"; + compatible =3D "microchip,mpfs-macb", "cdns,macb"; reg =3D <0x0 0x20112000 0x0 0x2000>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -353,6 +355,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; + resets =3D <&clkcfg CLK_MAC1>; status =3D "disabled"; }; =20 --=20 2.36.1