From nobody Sat Sep 21 21:24:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 976D1C43334 for ; Fri, 17 Jun 2022 11:13:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382357AbiFQLNB (ORCPT ); Fri, 17 Jun 2022 07:13:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381355AbiFQLMy (ORCPT ); Fri, 17 Jun 2022 07:12:54 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5879422BDC; Fri, 17 Jun 2022 04:12:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7E10F660179B; Fri, 17 Jun 2022 12:12:52 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1655464373; bh=xmGis2wqk9howX9w26cQ+zfn6UOV6aN48S5Z7v46gtI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d6aJc5ZBpfSogs9a0v0NGrgOAbYI1DjWA2fh4Ca4fdxfhEG/SY3mtMVHNhaCcRk87 nUoZKPI2TkMo+wBYdCrWqwCOgCM5S5JROwulsjwuZ2vHa6rq4E2lDwrSbAl2jn+W4v Yx+b++Uw8IKbmozNeBVcgdRjgUVARdC8LuEUG84gGJ16ihaWJ2X9vB+qAJAMgghXCL rJAnUcSAYvVmECmw/b54l0LoRzJiNLHTQKE6R9rIzOGSpc1dPHd/CX6PwSaN0G8lK4 OwtO9dQ6is3aSEMNUh1YTMg94pebEAnoM/kw7fd33R7paFCGtt0CeSRWSK/SF1O/2G BMZu//mmSgMrA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, wenst@chromium.org, angelogioacchino.delregno@collabora.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent Date: Fri, 17 Jun 2022 13:12:47 +0200 Message-Id: <20220617111248.90505-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220617111248.90505-1-angelogioacchino.delregno@collabora.com> References: <20220617111248.90505-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF clock: this is required to trigger clock source selection on CLK_TOP_EDP, while avoiding to manage the enablement of the former separately from the latter in the displayport driver. Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") Signed-off-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Reviewed-by: Bo-Chen Chen --- drivers/clk/mediatek/clk-mt8195-vdo0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/= clk-mt8195-vdo0.c index 261a7f76dd3c..07b46bfd5040 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -37,6 +37,10 @@ static const struct mtk_gate_regs vdo0_2_cg_regs =3D { #define GATE_VDO0_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + static const struct mtk_gate vdo0_clks[] =3D { /* VDO0_0 */ GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0), @@ -85,7 +89,8 @@ static const struct mtk_gate vdo0_clks[] =3D { /* VDO0_2 */ GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0), GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8), - GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp"= , 16), + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", + "top_edp", 16, CLK_SET_RATE_PARENT), }; =20 static int clk_mt8195_vdo0_probe(struct platform_device *pdev) --=20 2.35.1 From nobody Sat Sep 21 21:24:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4C6BC43334 for ; Fri, 17 Jun 2022 11:13:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382368AbiFQLNE (ORCPT ); Fri, 17 Jun 2022 07:13:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382340AbiFQLM4 (ORCPT ); Fri, 17 Jun 2022 07:12:56 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94E3922500; Fri, 17 Jun 2022 04:12:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3BEF6660179C; Fri, 17 Jun 2022 12:12:53 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1655464373; bh=WkHnfO6PWMXpQT5nfqhbXwC+34pz7EH8/LW7Tl1ijxg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Obv9xiDNpffYAoSPYZnZ7QmMSL58msikQgc5w93Wyz9tLLs3ioDEaeEi4WA7DAye8 V+jPOG2RlvhqgzdyqsnybDiaLlvV2VmXujycQ40JFq53x7CoTh5iCLQVC3WKJaLM11 91mKIGRoBqFfOkTMj035vrg4zwH4fzJVo2X/4YNz/a8KMDMeS3tgQMsvqTCW1R4t5a pH/jMI4hpv+NI2nrSC+7BLQMwRLlnqur07BFL57eH3JvEZmo2G6APEErreI91ze/ie nXj8VrldqZDeaQcV9HwIe0m6XB5J3e82urD5+Xp4hva9UJVf7JaCMYYcMca+Xbfah4 WlYFDY9vPFnQw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, wenst@chromium.org, angelogioacchino.delregno@collabora.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent Date: Fri, 17 Jun 2022 13:12:48 +0200 Message-Id: <20220617111248.90505-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220617111248.90505-1-angelogioacchino.delregno@collabora.com> References: <20220617111248.90505-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) and also fix its parent clock name as it has to be "top_dp" for two reasons: - This is its real parent! - Likewise to eDP/VDO0 counterpart, we need clock source selection on CLK_TOP_DP. Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") Signed-off-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Reviewed-by: Bo-Chen Chen --- drivers/clk/mediatek/clk-mt8195-vdo1.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/= clk-mt8195-vdo1.c index 3378487d2c90..d54d7726d186 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -43,6 +43,10 @@ static const struct mtk_gate_regs vdo1_3_cg_regs =3D { #define GATE_VDO1_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 +#define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + #define GATE_VDO1_3(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 @@ -99,7 +103,7 @@ static const struct mtk_gate vdo1_clks[] =3D { GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vp= p", 1), GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vp= p", 9), - GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16), + GATE_VDO1_2_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_R= ATE_PARENT), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "to= p_vpp", 17), /* VDO1_3 */ GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8), --=20 2.35.1