From nobody Mon Apr 27 04:33:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6665CC43334 for ; Fri, 17 Jun 2022 07:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234583AbiFQH1r (ORCPT ); Fri, 17 Jun 2022 03:27:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380440AbiFQH1j (ORCPT ); Fri, 17 Jun 2022 03:27:39 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 310F1D84 for ; Fri, 17 Jun 2022 00:27:34 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id v1so7082896ejg.13 for ; Fri, 17 Jun 2022 00:27:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yhUmQjlVEm98FuejkV49ied/cxReTiKl0adLMVVp/04=; b=Fwy6VFGlfabLlQay+AyWPbhL+ymPIcSSw58I4ati4Gu0SX90FZZKiGyRY5UnAcOseE Y3xhGsNfU1XWjeGEnkOeCvGy/apeySedKcr9vJN8aZiwgr2uLYVnmMexlPpBihkQg5hd FrBxkl+1NsMB326LOIBSFwqXnnYIUqiLXUW0ztajyB2NbM18KVmxAzdaagHfjjjzxr12 zoBq0x3czBzLLcR3X8YtRJaiunBvRQxe+B/o8cSP9qFXVJ5s8DsBsINfLTOn5u5fTzAo ldfOfMYNHM+KpTLP7vSOmCezgWlLpERpCvHziL82YSvjUl5YiJuY2LzqdNF7rTP0WHmq fnEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yhUmQjlVEm98FuejkV49ied/cxReTiKl0adLMVVp/04=; b=2ZE6S3hu2IY2kt+F+DZ6QzFXcssKQzaTNY8yftl551k+zoSZ54PfdBKHhKW3ygo6c1 tua9C3QgA4cvbyyDqRM85m6VHg9l8SdXXx6zIxptkkpoV6bFfkzQFciCL6VVJaqRHl66 AP5+hZurjlYcdhXOSMLRPrJzuNzNgcmBqzKuuTaTEtADGN5No4VczbeRVHXyzFAIDWQY LVoj4lkODq+i4JfH/CxFenoe6AOsRbZiCrWlXCXv+YOncxA3KYvgp+0DNf0lXOaHbsZI 6UgfD2FjQozrYEMOWZRUbuWQ0tVeTnO2QfmXx2ODj6zwzhPQ71dkz1mbrxMxJt/v9Iy0 g6DA== X-Gm-Message-State: AJIora9mfw5BmMcK2ycMI1B5GEDXM8YXitxVqBiV/7Vw3VF0x8h8qOe7 BayaT4OblqVCgLK7efJLBLPAmw== X-Google-Smtp-Source: AGRyM1sHnxSHzWDAa3DPinyDjLvfprasBj5z+3vPJoKmBnT+Zar+MTgF0gDYVJTREtggVIPIp4jIJw== X-Received: by 2002:a17:907:a427:b0:71b:6f0b:8beb with SMTP id sg39-20020a170907a42700b0071b6f0b8bebmr5651272ejc.496.1655450852661; Fri, 17 Jun 2022 00:27:32 -0700 (PDT) Received: from localhost.localdomain ([2001:861:44c0:66c0:d227:8f3c:286a:d9d8]) by smtp.gmail.com with ESMTPSA id n9-20020a170906840900b006fec56a80a8sm1762556ejx.115.2022.06.17.00.27.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jun 2022 00:27:32 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, martin.blumenstingl@googlemail.com, devicetree@vger.kernel.org Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong , Rob Herring Subject: [PATCH v3 1/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Date: Fri, 17 Jun 2022 09:27:18 +0200 Message-Id: <20220617072723.1742668-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617072723.1742668-1-narmstrong@baylibre.com> References: <20220617072723.1742668-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3532; h=from:subject; bh=nfzFDo4vSJe6xj0FTwEJ/U/lIAnr1DaEgJJpcHdVaxw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyqY5ZuFCHuvgCYy0WNIdOndZlC1wP7beVGnIlw N220U86JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqgAKCRB33NvayMhJ0ZnOD/ 448XF+A0HBYCR8G5hsszIj07/nBsQTDfXg2FAGCrmM5l6izU4QwCKijtYxwRJcQUAeI+n2/F3bkehj fuLHK4tfiXXGDNIYISm6fuo3b4OjI5uTJ7TK03SF+kRszl2OACvBIkK91dvD30r9Vt3ukMxOkbP7bR qtDueOf0BcQnXOx+cZ6RAY9LbqdEbmKkTYUIQn+CsVYZ6OSUD57FiN2BILOltKIhdoINejZUnvQbso Nrko/HA5QbZ/6nCqXFmxaGERRxuP/wofeRCdvX1aZXamS2/+7jRPAYZ+hUHIF3EwRTHENxT5FdOsXL 04hdOPjYXQEFWRFQrBnzgQs3uwKruSsG0OIB3Xbug4kUmX8HXSERS1ZnSgV5XOlQBRbQJho9y1a6Lc tsqxbFPHI7sfy/FsgaJhgbqoIF5T5kaI/Wf8+8p3luA+0U28tRkwGad6252bLdjyHxtjSYUIbZ9Bcn dmhwxY36KKto7GqwdbHmyeK2r08GCrSmhfkKuJKS68RPkLG/DWbfPOBHU8b72GFJHaI4QKz5qta8n+ 8ddmyn1Nrgk8NkOGKRqnQEgxqO4qhvLbIGyha4tRf5owRWD9UlhPbS0SFR3/KOx92iZAD5a2QxHLNh RnGc64vBzoOuhrJkCdRvoqCVClQB+8YhKSTGFdRVn25OVDMwH/O91clAu6Fw== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver= (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to = the DW-HDMI Glue on the same Amlogic SoCs. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../display/amlogic,meson-dw-mipi-dsi.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson= -dw-mipi-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mip= i-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mip= i-dsi.yaml new file mode 100644 index 000000000000..e057659545a9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.y= aml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml= #" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Hos= t Controller + +maintainers: + - Neil Armstrong + +description: | + The Amlogic Meson Synopsys Designware Integration is composed of + - A Synopsys DesignWare MIPI DSI Host Controller IP + - A TOP control block controlling the Clocks & Resets of the IP + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-dw-mipi-dsi + + reg: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + minItems: 2 + items: + - const: pclk + - const: px_clk + - const: meas_clk + + resets: + minItems: 1 + + reset-names: + items: + - const: top + + phys: + minItems: 1 + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@7000 { + compatible =3D "amlogic,meson-g12a-dw-mipi-dsi"; + reg =3D <0x6000 0x400>; + resets =3D <&reset_top>; + reset-names =3D "top"; + clocks =3D <&clk_pclk>, <&clk_px>; + clock-names =3D "pclk", "px_clk"; + phys =3D <&mipi_dphy>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* VPU VENC Input */ + mipi_dsi_venc_port: port@0 { + reg =3D <0>; + + mipi_dsi_in: endpoint { + remote-endpoint =3D <&dpi_out>; + }; + }; + + /* DSI Output */ + mipi_dsi_panel_port: port@1 { + reg =3D <1>; + + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; + }; + }; + }; --=20 2.25.1 From nobody Mon Apr 27 04:33:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C5BCCA47C for ; Fri, 17 Jun 2022 07:27:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380520AbiFQH1n (ORCPT ); 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Fri, 17 Jun 2022 00:27:33 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, martin.blumenstingl@googlemail.com, devicetree@vger.kernel.org Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong , Rob Herring Subject: [PATCH v3 2/6] dt-bindings: display: meson-vpu: add third DPI output port Date: Fri, 17 Jun 2022 09:27:19 +0200 Message-Id: <20220617072723.1742668-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617072723.1742668-1-narmstrong@baylibre.com> References: <20220617072723.1742668-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1046; h=from:subject; bh=LQlD6Fu3ObIBtey05krAjcgHoTrbx+0w6dwgfJGEYig=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyrycIYT5c95AzVhdINNgW+nDNvrU5WWX82Nd9Z I9hXFSuJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqwAKCRB33NvayMhJ0aBmEA CiyTyjR1VeKCUk6d+hM4cmyr5iuMn3U9gb5MpoCunBiqjrakoFPCMcqSVEpcqPA9x7IhaB9XJmrKwR VvYXEmIfNtFf8kUDsbbpwa1oisLAvbEw+kklacItIJ3nK2t4tLTljpQFeYgY5ZVENj0c1c49WX9GOq Q8imHKf+JzBRX+SmfOZnGnFS4GD4SqVl+Em+YSzIao68s9VyFxA+RNCv5Jblh2fB6nhJGO9DGsEvo0 NdzdM1DAwftoaVumZefuwzVpZ3stCQe8eiOLa5477MQAyrcIYm2j9dgm6iCnLQxiS5jNhhbtD6j6r0 56zOHNOzd5PIzl7nR2VPluzEs2dwqPg6hCSOfGqDnIxwB7n2pQfwYPTLkAz+TkHFcuLhgrLGV6snPV E2o7RT06OLYigLDikb31GoAF45yQKYiukBnrK51shwdGIxMywmtb1mYNIaR/Y1MPNm2hkkwAtBSzN7 hWS0VQGvG9tzqWm2fCA+qmyFUk8N2yw2hQ2eVaDkta1Un02Guw07WQl08yh8wrYqMQL/3d6cdBhkuP iEyXEGeZ63MpTInEfh+Q163dd3ujrp9JZ1GIqcr5WvjKA9rL0Br5k2NiSOSfKXyPZS9KxUglN5pR+A o2s6Pg0aBIL/dlFyVeSIvp4Y07nhY3rhAopdbKNM3mBVm6pXsNOBVI2gjnEQ== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add third port corresponding to the ENCL DPI encoder used to connect to DSI or LVDS transceivers. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../devicetree/bindings/display/amlogic,meson-vpu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.ya= ml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index 047fd69e0377..fdb42b14a099 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -96,6 +96,11 @@ properties: description: A port node pointing to the HDMI-TX port node. =20 + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node pointing to the DPI port node (e.g. DSI or LVDS transcei= ver). + "#address-cells": const: 1 =20 --=20 2.25.1 From nobody Mon Apr 27 04:33:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39E12C43334 for ; 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Fri, 17 Jun 2022 00:27:34 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, martin.blumenstingl@googlemail.com Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 3/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Date: Fri, 17 Jun 2022 09:27:20 +0200 Message-Id: <20220617072723.1742668-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617072723.1742668-1-narmstrong@baylibre.com> References: <20220617072723.1742668-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=15324; h=from:subject; bh=GRH8VJ/q6ifucq+w9X1KOuURzCabTqKfWbU6rF/v8/Y=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyrUAPveeFxm+fuSZ4x1zCAkI5h0d8QG4M7LP08 PqW+dkSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqwAKCRB33NvayMhJ0aEmD/ oCSAIdkFbPZsPlEbm1mka4T7xzMkDsOKMz3d6BDM/NLKdWHyIPUBDkqvu0BOYNgoGApqleoV4zgmg4 /SOzX85MMeniyn5Z32ZAzAcSyUR1BHdmhuM2cEUOM/QNqG2ebXS6MT4drqW5mhaBydzHWgBJygOe/l vtgH82bcUkBUAo7hPIRhmNy3eYHXqdCDov1DwDjtP0feOR7pwu6Gh79bkPTUBqcck+JMTsA9EKhFjA 58UN87a30FhDFz44yTaYBJ+fDp4gbN4h+hcu+YZAKe41JGHxxzWbQGGu5Uid70WSq8Wh/pXIG0WUsj Y+hn7vy7cXTnJXRHhZH8LEUfarOf+WKxk3VrY7hl4Ly0SgCSDy+p5KaH3fnj6wrzutORvgVvxrQ0R6 pWr1I2nG3MnK8BuRwnIFEMIdcXq93b57dc/CuLsv4GIx4FggQ7k6SpWIqZiu53OpnFDxStuO/nX5WM spQwIRGd+9pXHsn4IOZOSECGWac406gnvNZOIb5De2tdQTnZylae9apSMUsCK4RcrPMKdTe1114lgx heyHwxXx/bSnWmtx1o1sTqB0Gux7L9nQtFSwIw8aN0jRxoIp0LbxMENoMkNPNh7DiOchz7Te9fgpAF 0NrXtKwoqp/yIsDm9I6kjo80X/UDFH6q4EpehAjR96RXslYJ7EMmwyrUEUKQ== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver= on the Amlogic AXG, G12A, G12B & SM1 SoCs. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_registers.h | 25 +++ drivers/gpu/drm/meson/meson_venc.c | 211 +++++++++++++++++++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_vpp.h | 2 + 4 files changed, 242 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meso= n/meson_registers.h index 0f3cafab8860..3d73d00a1f4c 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -812,6 +812,7 @@ #define VENC_STATA 0x1b6d #define VENC_INTCTRL 0x1b6e #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) +#define VENC_INTCTRL_ENCP_LNRST_INT_EN BIT(9) #define VENC_INTFLAG 0x1b6f #define VENC_VIDEO_TST_EN 0x1b70 #define VENC_VIDEO_TST_MDSEL 0x1b71 @@ -1192,7 +1193,11 @@ #define ENCL_VIDEO_PB_OFFST 0x1ca5 #define ENCL_VIDEO_PR_OFFST 0x1ca6 #define ENCL_VIDEO_MODE 0x1ca7 +#define ENCL_PX_LN_CNT_SHADOW_EN BIT(15) #define ENCL_VIDEO_MODE_ADV 0x1ca8 +#define ENCL_VIDEO_MODE_ADV_VFIFO_EN BIT(3) +#define ENCL_VIDEO_MODE_ADV_GAIN_HDTV BIT(4) +#define ENCL_SEL_GAMMA_RGB_IN BIT(10) #define ENCL_DBG_PX_RST 0x1ca9 #define ENCL_DBG_LN_RST 0x1caa #define ENCL_DBG_PX_INT 0x1cab @@ -1219,11 +1224,14 @@ #define ENCL_VIDEO_VOFFST 0x1cc0 #define ENCL_VIDEO_RGB_CTRL 0x1cc1 #define ENCL_VIDEO_FILT_CTRL 0x1cc2 +#define ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER BIT(12) #define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 #define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 #define ENCL_VIDEO_MATRIX_CB 0x1cc5 #define ENCL_VIDEO_MATRIX_CR 0x1cc6 #define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 +#define ENCL_VIDEO_RGBIN_RGB BIT(0) +#define ENCL_VIDEO_RGBIN_ZBLK BIT(1) #define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 #define ENCL_DACSEL_0 0x1cc9 #define ENCL_DACSEL_1 0x1cca @@ -1300,13 +1308,28 @@ #define RDMA_STATUS2 0x1116 #define RDMA_STATUS3 0x1117 #define L_GAMMA_CNTL_PORT 0x1400 +#define L_GAMMA_CNTL_PORT_VCOM_POL BIT(7) /* RW */ +#define L_GAMMA_CNTL_PORT_RVS_OUT BIT(6) /* RW */ +#define L_GAMMA_CNTL_PORT_ADR_RDY BIT(5) /* Read Only */ +#define L_GAMMA_CNTL_PORT_WR_RDY BIT(4) /* Read Only */ +#define L_GAMMA_CNTL_PORT_RD_RDY BIT(3) /* Read Only */ +#define L_GAMMA_CNTL_PORT_TR BIT(2) /* RW */ +#define L_GAMMA_CNTL_PORT_SET BIT(1) /* RW */ +#define L_GAMMA_CNTL_PORT_EN BIT(0) /* RW */ #define L_GAMMA_DATA_PORT 0x1401 #define L_GAMMA_ADDR_PORT 0x1402 +#define L_GAMMA_ADDR_PORT_RD BIT(12) +#define L_GAMMA_ADDR_PORT_AUTO_INC BIT(11) +#define L_GAMMA_ADDR_PORT_SEL_R BIT(10) +#define L_GAMMA_ADDR_PORT_SEL_G BIT(9) +#define L_GAMMA_ADDR_PORT_SEL_B BIT(8) +#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0) #define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 #define L_RGB_BASE_ADDR 0x1405 #define L_RGB_COEFF_ADDR 0x1406 #define L_POL_CNTL_ADDR 0x1407 #define L_DITH_CNTL_ADDR 0x1408 +#define L_DITH_CNTL_DITH10_EN BIT(10) #define L_GAMMA_PROBE_CTRL 0x1409 #define L_GAMMA_PROBE_COLOR_L 0x140a #define L_GAMMA_PROBE_COLOR_H 0x140b @@ -1363,6 +1386,8 @@ #define L_LCD_PWM1_HI_ADDR 0x143f #define L_INV_CNT_ADDR 0x1440 #define L_TCON_MISC_SEL_ADDR 0x1441 +#define L_TCON_MISC_SEL_STV1 BIT(4) +#define L_TCON_MISC_SEL_STV2 BIT(5) #define L_DUAL_PORT_CNTL_ADDR 0x1442 #define MLVDS_CLK_CTL1_HI 0x1443 #define MLVDS_CLK_CTL1_LO 0x1444 diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/mes= on_venc.c index 3c55ed003359..eb2ac0549d46 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -6,6 +6,7 @@ */ =20 #include +#include =20 #include =20 @@ -1557,6 +1558,205 @@ void meson_venc_hdmi_mode_set(struct meson_drm *pri= v, int vic, } EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); =20 +static unsigned short meson_encl_gamma_table[256] =3D { + 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, + 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, + 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184= , 188, + 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248= , 252, + 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312= , 316, + 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376= , 380, + 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440= , 444, + 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504= , 508, + 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568= , 572, + 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632= , 636, + 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696= , 700, + 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760= , 764, + 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824= , 828, + 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888= , 892, + 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952= , 956, + 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012,= 1016, 1020, +}; + +static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data, + u32 rgb_mask) +{ + int i, ret; + u32 reg; + + writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0, + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); + + ret =3D readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT= ), + reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask | + FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); + + for (i =3D 0; i < 256; i++) { + ret =3D readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_POR= T), + reg, reg & L_GAMMA_CNTL_PORT_WR_RDY, + 10, 10000); + if (ret) + pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__); + + writel_relaxed(data[i], priv->io_base + _REG(L_GAMMA_DATA_PORT)); + } + + ret =3D readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT= ), + reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask | + FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0x23), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); +} + +void meson_encl_load_gamma(struct meson_drm *priv) +{ + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_POR= T_SEL_R); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_POR= T_SEL_G); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_POR= T_SEL_B); + + writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, L_GAMMA_CNTL_PORT_EN, + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); +} + +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + const struct drm_display_mode *mode) +{ + unsigned int max_pxcnt; + unsigned int max_lncnt; + unsigned int havon_begin; + unsigned int havon_end; + unsigned int vavon_bline; + unsigned int vavon_eline; + unsigned int hso_begin; + unsigned int hso_end; + unsigned int vso_begin; + unsigned int vso_end; + unsigned int vso_bline; + unsigned int vso_eline; + + max_pxcnt =3D mode->htotal - 1; + max_lncnt =3D mode->vtotal - 1; + havon_begin =3D mode->htotal - mode->hsync_start; + havon_end =3D havon_begin + mode->hdisplay - 1; + vavon_bline =3D mode->vtotal - mode->vsync_start; + vavon_eline =3D vavon_bline + mode->vdisplay - 1; + hso_begin =3D 0; + hso_end =3D mode->hsync_end - mode->hsync_start; + vso_begin =3D 0; + vso_end =3D 0; + vso_bline =3D 0; + vso_eline =3D mode->vsync_end - mode->vsync_start; + + meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_= MODE)); + writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN | + ENCL_VIDEO_MODE_ADV_GAIN_HDTV | + ENCL_SEL_GAMMA_RGB_IN, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER, + priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL)); + writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT)); + writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT)); + writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN)); + writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END)); + writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE)); + writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE)); + + writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN)); + writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END)); + writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN)); + writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END)); + writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE)); + writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE)); + writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK, + priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL)); + + /* default black pattern */ + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR)); + writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN)); + writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0, + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR)); + writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic v= alue */ + + writel_relaxed(L_DITH_CNTL_DITH10_EN, priv->io_base + _REG(L_DITH_CNTL_AD= DR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR)); + + /* Hsync signal for TTL */ + if (mode->flags & DRM_MODE_FLAG_PHSYNC) { + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR)); + } else { + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR)); + } + writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR)); + + /* Vsync signal for TTL */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR)); + if (mode->flags & DRM_MODE_FLAG_PVSYNC) { + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } else { + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } + + /* DE signal */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR)); + + /* Hsync signal */ + writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR)); + writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR)); + + /* Vsync signal */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR)); + + writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR)); + writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2, + priv->io_base + _REG(L_TCON_MISC_SEL_ADDR)); + + priv->venc.current_mode =3D MESON_VENC_MODE_MIPI_DSI; +} +EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set); + void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode) { @@ -1747,8 +1947,15 @@ unsigned int meson_venci_get_field(struct meson_drm = *priv) =20 void meson_venc_enable_vsync(struct meson_drm *priv) { - writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, - priv->io_base + _REG(VENC_INTCTRL)); + switch (priv->venc.current_mode) { + case MESON_VENC_MODE_MIPI_DSI: + writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + break; + default: + writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + } regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); } =20 diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/mes= on_venc.h index 9138255ffc9e..0f59adb1c6db 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -21,6 +21,7 @@ enum { MESON_VENC_MODE_CVBS_PAL, MESON_VENC_MODE_CVBS_NTSC, MESON_VENC_MODE_HDMI, + MESON_VENC_MODE_MIPI_DSI, }; =20 struct meson_cvbs_enci_mode { @@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode { unsigned int analog_sync_adj; }; =20 +/* LCD Encoder gamma setup */ +void meson_encl_load_gamma(struct meson_drm *priv); + /* HDMI Clock parameters */ enum drm_mode_status meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode); @@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int= vic, unsigned int ycrcb_map, bool yuv420_mode, const struct drm_display_mode *mode); +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + const struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv); =20 void meson_venc_enable_vsync(struct meson_drm *priv); diff --git a/drivers/gpu/drm/meson/meson_vpp.h b/drivers/gpu/drm/meson/meso= n_vpp.h index afc9553ed8d3..b790042a1650 100644 --- a/drivers/gpu/drm/meson/meson_vpp.h +++ b/drivers/gpu/drm/meson/meson_vpp.h @@ -12,6 +12,8 @@ struct drm_rect; struct meson_drm; =20 +/* Mux VIU/VPP to ENCL */ +#define MESON_VIU_VPP_MUX_ENCL 0x0 /* Mux VIU/VPP to ENCI */ #define MESON_VIU_VPP_MUX_ENCI 0x5 /* Mux VIU/VPP to ENCP */ --=20 2.25.1 From nobody Mon Apr 27 04:33:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8217C433EF for ; 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Fri, 17 Jun 2022 00:27:35 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, martin.blumenstingl@googlemail.com Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 4/6] drm/meson: vclk: add DSI clock config Date: Fri, 17 Jun 2022 09:27:21 +0200 Message-Id: <20220617072723.1742668-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617072723.1742668-1-narmstrong@baylibre.com> References: <20220617072723.1742668-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3768; h=from:subject; bh=wVEu88z9Tki+VwSbbtWc3B9clOhCXc+ZkFmWDGthpuw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyrS/tyPj3lnnn7HteF8IVQnViij4BcDf57V2+t 0uJANG6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqwAKCRB33NvayMhJ0SmLEA CG35qlOumtls9mivNjWPMKCp0/wz5sEksxVdSfbEF8wJWBnhZNsKMBp/xwx6/zZiD9it5SIAa8wZSz sAgkSM9dmFReB6MziDdFqVJfQTCFbJK1FrQhHL4UyulW3wd1TZwjVMulQ3VUsSOMZEVj4FbRkMOEas SUI9VfH6I6vAjXnoOnbCJCzpnXaAczTQa+0PVZrArw+0YPJhlCl7m9a6rexnjPukfBXi1Uen1A2tDL 1VCWWy2XC67I8YKkdAdhcMHNIk8SEUG48yQn1Yd67cZU+djjCIHpARjU4Wzo6RikJcRLSbLH+hVwUf bhIFuHb2aW9/w9KY8TIKd/GK7yYN6JT1Xz7mkv9JQ8kquj0ePxMU+dz8/kitu8EUe/e4zWjks0w+lU MwQgc0skTGmofkzR5U9MCApU5+gEqfD4SRnKdsBs9A4v/6TdDw1XmL4sgo8Tm9eun4XQ9BRVHyGuwh NFA/760V5/jvamDsQaxtwNGXCwOuKbmv+Wc7CemcxnbaXwwSsUxotln3KREDlkVqK0HJ4Q0uEe/3T8 WGdnSxF3MSBNi/PDN2k2qv9iVndUz5QsVEJ3QFmlGcw2BlpIkSYM72HsrM0Ntt9eC0PwtxJZlssPYS vEoZsRijlKN2TxI28TCeEuYrVlxscjUkjwW95b1lDU9ifjZTuMJkXHNg1h6g== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DSI path used the ENCL pixel encoder, thus this adds a clock config using the HDMI PLL in order to feed the ENCL encoder via the VCLK2 path and the CTS_ENCL clock output. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_vclk.c | 47 ++++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_vclk.h | 1 + 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/mes= on_vclk.c index 2a82119eb58e..5e4d982be1c8 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -55,6 +55,8 @@ #define VCLK2_DIV_MASK 0xff #define VCLK2_DIV_EN BIT(16) #define VCLK2_DIV_RESET BIT(17) +#define CTS_ENCL_SEL_MASK (0xf << 12) +#define CTS_ENCL_SEL_SHIFT 12 #define CTS_VDAC_SEL_MASK (0xf << 28) #define CTS_VDAC_SEL_SHIFT 28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ @@ -83,6 +85,7 @@ #define VCLK_DIV12_EN BIT(4) #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ #define CTS_ENCI_EN BIT(0) +#define CTS_ENCL_EN BIT(3) #define CTS_ENCP_EN BIT(2) #define CTS_VDAC_EN BIT(4) #define HDMI_TX_PIXEL_EN BIT(5) @@ -1024,6 +1027,47 @@ static void meson_vclk_set(struct meson_drm *priv, u= nsigned int pll_base_freq, regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); } =20 +static void meson_dsi_clock_config(struct meson_drm *priv, unsigned int fr= eq) +{ + meson_hdmi_pll_generic_set(priv, freq * 10); + + /* Setup vid_pll divider value /5 */ + meson_vid_pll_set(priv, VID_PLL_DIV_5); + + /* Disable VCLK2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); + + /* Setup the VCLK2 divider value /2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, 2 - 1); + + /* select vid_pll for vclk2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); + + /* enable vclk2 gate */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); + + /* select vclk2_div1 for encl */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT)); + + /* release vclk2_div_reset and enable vclk2_div */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_= RESET, + VCLK2_DIV_EN); + + /* enable vclk2_div1 gate */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV= 1_EN); + + /* reset vclk2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_= SOFT_RESET); + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0); + + /* enable encl_clk */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCL_EN, CTS_ENCL_EN= ); + + usleep_range(10000, 11000); +} + void meson_vclk_setup(struct meson_drm *priv, unsigned int target, unsigned int phy_freq, unsigned int vclk_freq, unsigned int venc_freq, unsigned int dac_freq, @@ -1050,6 +1094,9 @@ void meson_vclk_setup(struct meson_drm *priv, unsigne= d int target, meson_vclk_set(priv, phy_freq, 0, 0, 0, VID_PLL_DIV_5, 2, 1, 1, false, false); return; + } else if (target =3D=3D MESON_VCLK_TARGET_DSI) { + meson_dsi_clock_config(priv, phy_freq); + return; } =20 hdmi_tx_div =3D vclk_freq / dac_freq; diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/mes= on_vclk.h index 60617aaf18dd..1152b3af8d2e 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -17,6 +17,7 @@ enum { MESON_VCLK_TARGET_CVBS =3D 0, MESON_VCLK_TARGET_HDMI =3D 1, MESON_VCLK_TARGET_DMT =3D 2, + MESON_VCLK_TARGET_DSI =3D 3, }; =20 /* 27MHz is the CVBS Pixel Clock */ --=20 2.25.1 From nobody Mon Apr 27 04:33:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F32DC433EF for ; Fri, 17 Jun 2022 07:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380440AbiFQH1w (ORCPT ); Fri, 17 Jun 2022 03:27:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380489AbiFQH1k (ORCPT ); Fri, 17 Jun 2022 03:27:40 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6495F5F44 for ; Fri, 17 Jun 2022 00:27:38 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id n20so337253ejz.10 for ; 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Fri, 17 Jun 2022 00:27:36 -0700 (PDT) Received: from localhost.localdomain ([2001:861:44c0:66c0:d227:8f3c:286a:d9d8]) by smtp.gmail.com with ESMTPSA id n9-20020a170906840900b006fec56a80a8sm1762556ejx.115.2022.06.17.00.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jun 2022 00:27:36 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, martin.blumenstingl@googlemail.com Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong , Jagan Teki Subject: [PATCH v3 5/6] drm/meson: add DSI encoder Date: Fri, 17 Jun 2022 09:27:22 +0200 Message-Id: <20220617072723.1742668-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617072723.1742668-1-narmstrong@baylibre.com> References: <20220617072723.1742668-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8193; h=from:subject; bh=5SY+f9FZbEJP2uh/90AJVMp0SJeiVB72aKbSQ+lKbKw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyrRAp2aas4pFiDuPnKF1I1V3k2lhmdwsB7mny9 9VwsiyqJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqwAKCRB33NvayMhJ0SJlD/ 9gsEdJBcBwjjIuBLZ5IJfYnwhpX6Ey27tU8+qMxilIboOin3AT8ubqLPrr6MPAq20rSuSu+aBk16P/ rIjRrIXcIl/5/BVE2B7nIwPHny9RG9FVnuFir1NiIs1seryI5mYgFixaZ3GvC0MXLQEn7VWERKcccu cuwi+z1Uq8meRNgZnxo7SCZpyJK57xsBP9EGXcOHHuRX4hd70P+gLrNXCk3XGRxeRCF0OxvIFRujrH 3V+rcQdPWXP6ovjtbn3rqnwKRP/OwsfGsqibENIsOox4JAuUO1DILH7WfbiCL9wlwtAc67GUUAejKz QVGacvGOlx/LqsIJ6G6V+i8VeJbtssRbH92WbVRgU9tkRecMBXBA4BHp+mQP0+tLWsPrlulRETkeFA DFhwjq0KdkEPtDCZ1pmmBbQnNb5MzlU8iM37/iSd1DVQzB1U3831FonJW9Fih/gCAZh5pj3e5WeoKE xmYlWH0RdFkqRQ2HHVV0q3oC4qDAwTnFTPjFYxqK697ndkhIuvrNGm+eCPkcwYQY9dCVy4turhCLHE cp0IIGz6ZxMg/Vo91j9WolA+z08rAtQEmlrLOslYVhM5NZ++7pS+75NBk89coZKAfxsKXEiFd2YpWe x4VpRi9gI9p43fw4qhQKEFmDfJbTzEuBDwHJyHz966j2n6aobVBfWLMs7BQg== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds an encoder bridge designed to drive a MIPI-DSI display by using the ENCL encoder through the internal MIPI DSI transceiver connected to the output of the ENCL pixel encoder. Signed-off-by: Neil Armstrong Reviewed-by: Jagan Teki Acked-by: Martin Blumenstingl --- drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_drv.c | 7 + drivers/gpu/drm/meson/meson_encoder_dsi.c | 160 ++++++++++++++++++++++ drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 ++ 4 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 3afa31bdc950..833e18c20603 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -2,7 +2,7 @@ meson-drm-y :=3D meson_drv.o meson_plane.o meson_crtc.o meson_encoder_cvbs= .o meson-drm-y +=3D meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_o= verlay.o meson-drm-y +=3D meson_rdma.o meson_osd_afbcd.o -meson-drm-y +=3D meson_encoder_hdmi.o +meson-drm-y +=3D meson_encoder_hdmi.o meson_encoder_dsi.o =20 obj-$(CONFIG_DRM_MESON) +=3D meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) +=3D meson_dw_hdmi.o diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meso= n_drv.c index 1b70938cfd2c..896994862ad7 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -34,6 +34,7 @@ #include "meson_registers.h" #include "meson_encoder_cvbs.h" #include "meson_encoder_hdmi.h" +#include "meson_encoder_dsi.h" #include "meson_viu.h" #include "meson_vpp.h" #include "meson_rdma.h" @@ -324,6 +325,12 @@ static int meson_drv_bind_master(struct device *dev, b= ool has_components) if (ret) goto exit_afbcd; =20 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + ret =3D meson_encoder_dsi_init(priv); + if (ret) + goto free_drm; + } + ret =3D meson_plane_create(priv); if (ret) goto exit_afbcd; diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/me= son/meson_encoder_dsi.c new file mode 100644 index 000000000000..20485a254ac4 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "meson_drv.h" +#include "meson_encoder_dsi.h" +#include "meson_registers.h" +#include "meson_venc.h" +#include "meson_vclk.h" + +struct meson_encoder_dsi { + struct drm_encoder encoder; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct meson_drm *priv; +}; + +#define bridge_to_meson_encoder_dsi(x) \ + container_of(x, struct meson_encoder_dsi, bridge) + +static int meson_encoder_dsi_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct meson_encoder_dsi *encoder_dsi =3D bridge_to_meson_encoder_dsi(bri= dge); + + return drm_bridge_attach(bridge->encoder, encoder_dsi->next_bridge, + &encoder_dsi->bridge, flags); +} + +static void meson_encoder_dsi_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct meson_encoder_dsi *encoder_dsi =3D bridge_to_meson_encoder_dsi(bri= dge); + struct meson_drm *priv =3D encoder_dsi->priv; + + meson_vclk_setup(priv, MESON_VCLK_TARGET_DSI, mode->clock, 0, 0, 0, false= ); + + meson_venc_mipi_dsi_mode_set(priv, mode); + meson_encl_load_gamma(priv); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFI= FO_EN, + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN)); +} + +static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct meson_encoder_dsi *encoder_dsi =3D bridge_to_meson_encoder_dsi(bri= dge); + struct meson_drm *priv =3D encoder_dsi->priv; + + writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_= EN_CTRL)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); +} + +static void meson_encoder_dsi_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct meson_encoder_dsi *meson_encoder_dsi =3D + bridge_to_meson_encoder_dsi(bridge); + struct meson_drm *priv =3D meson_encoder_dsi->priv; + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MA= TRIX_EN_CTRL)); +} + +static const struct drm_bridge_funcs meson_encoder_dsi_bridge_funcs =3D { + .attach =3D meson_encoder_dsi_attach, + /* + * TOFIX: remove when dw-mipi-dsi moves out of mode_set + * We should get rid of mode_set, but until dw-mipi-dsi uses it + * we need to setup the pixel clock before the following + * bridge tries to setup the HW. + */ + .mode_set =3D meson_encoder_dsi_mode_set, + .atomic_enable =3D meson_encoder_dsi_atomic_enable, + .atomic_disable =3D meson_encoder_dsi_atomic_disable, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, +}; + +int meson_encoder_dsi_init(struct meson_drm *priv) +{ + struct meson_encoder_dsi *meson_encoder_dsi; + struct device_node *remote; + int ret; + + meson_encoder_dsi =3D devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi),= GFP_KERNEL); + if (!meson_encoder_dsi) + return -ENOMEM; + + /* DSI Transceiver Bridge */ + remote =3D of_graph_get_remote_node(priv->dev->of_node, 2, 0); + if (!remote) { + dev_err(priv->dev, "DSI transceiver device is disabled"); + return 0; + } + + meson_encoder_dsi->next_bridge =3D of_drm_find_bridge(remote); + if (!meson_encoder_dsi->next_bridge) { + dev_dbg(priv->dev, "Failed to find DSI transceiver bridge\n"); + return -EPROBE_DEFER; + } + + /* DSI Encoder Bridge */ + meson_encoder_dsi->bridge.funcs =3D &meson_encoder_dsi_bridge_funcs; + meson_encoder_dsi->bridge.of_node =3D priv->dev->of_node; + meson_encoder_dsi->bridge.type =3D DRM_MODE_CONNECTOR_DSI; + + drm_bridge_add(&meson_encoder_dsi->bridge); + + meson_encoder_dsi->priv =3D priv; + + /* Encoder */ + ret =3D drm_simple_encoder_init(priv->drm, &meson_encoder_dsi->encoder, + DRM_MODE_ENCODER_DSI); + if (ret) { + dev_err(priv->dev, "Failed to init DSI encoder: %d\n", ret); + return ret; + } + + meson_encoder_dsi->encoder.possible_crtcs =3D BIT(0); + + /* Attach DSI Encoder Bridge to Encoder */ + ret =3D drm_bridge_attach(&meson_encoder_dsi->encoder, &meson_encoder_dsi= ->bridge, NULL, 0); + if (ret) { + dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); + return ret; + } + + /* + * We should have now in place: + * encoder->[dsi encoder bridge]->[dw-mipi-dsi bridge]->[panel bridge]->[= panel] + */ + + dev_dbg(priv->dev, "DSI encoder initialized\n"); + + return 0; +} diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.h b/drivers/gpu/drm/me= son/meson_encoder_dsi.h new file mode 100644 index 000000000000..0f4b641eb633 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2021 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_ENCODER_DSI_H +#define __MESON_ENCODER_DSI_H + +int meson_encoder_dsi_init(struct meson_drm *priv); + +#endif /* __MESON_ENCODER_DSI_H */ --=20 2.25.1 From nobody Mon Apr 27 04:33:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42922C433EF for ; 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Fri, 17 Jun 2022 00:27:37 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, martin.blumenstingl@googlemail.com Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong , Jagan Teki Subject: [PATCH v3 6/6] drm/meson: add support for MIPI-DSI transceiver Date: Fri, 17 Jun 2022 09:27:23 +0200 Message-Id: <20220617072723.1742668-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617072723.1742668-1-narmstrong@baylibre.com> References: <20220617072723.1742668-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=19338; h=from:subject; bh=PZ8q84CWoxyQYWWZJlYqiLEjqlXVQGbs+CkmFtmQKus=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyrI+Nnb24D4ULuUw4ZkVK61JVQIA3X0+ERI32t APYNolGJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqwAKCRB33NvayMhJ0Z09D/ 9Ig3N4+jj3xC40E0sjrM299BYoBTyHqNHj3Zt1ddJvMvWer2bxHgJsB//dZ9UmdrMfCb+Mjrsz0i6i DACuv59/IwFqHw2xUTUDHT+xO7RpJUkeccvMND/D5MkRT/cauyg8PrqwWA4rY4uiupSc+WHfrQnUjq BgQ0aP+MXnahyFvS1yu9zzrab2Vi25TlxNae8vs6fQx27wYeHArwQCJo5ZQ987dDLOKzQQ7Goz9ji/ 2IAv3XV65VmfVl93pxTga8P9NebQZ+Cpd0TR/4GXmgiBNEnbBRgpv97BLfR0AtPkJXKNacieWNZvT2 PPUC7qfXv6zPRIbE65wneyDV7Em29d8XeueXPt82QvBgmPGEzmSYcraPy90u/9EG1Amr5A4qNKRaTJ rDhmUTfCCFP6c6TRjvLOMRlRup8Rbb5EjIlXloitSwg/yhZpbb5YPtOhZ15EMQKyJjEzibN290waM/ QLdlCOC4qtzLaYmVZUIXagE7B9M1LJipFlsQcn+pGQUfiysejrvX2SSINYWfBOM+y//5+Nj6DTLGWn GEsh61woBPN7d8TFvTELNX3Cu0gMpCZpc1DcaZ2IGQw4aQN/e4SZvYJA1EdsVZYY0lAPLt8sp6VCPF b0VVRv4lCAFzZ8memj9bqb/LdSsCg7zG0Y4gB52E4Hsi7q5pKJ9QvHgSKA2A== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Amlogic G12A/G12B/SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (v= er 1.21a), with a custom glue managing the IP resets, clock and data input similar to = the DW-HDMI Glue on other Amlogic SoCs. This adds support for the Glue managing the transceiver, mimicing the init = flow provided by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digita= l D-PHY and the Analog PHY in the proper way. An optional "MEAS" clock can be enabled to measure the delay between each v= sync feeding the DW-MIPI-DSI transceiver. Signed-off-by: Neil Armstrong Reviewed-by: Jagan Teki --- drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 1 + drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 358 ++++++++++++++++++++++ drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 160 ++++++++++ 4 files changed, 526 insertions(+) create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig index 6c70fc3214af..71a1364b51e1 100644 --- a/drivers/gpu/drm/meson/Kconfig +++ b/drivers/gpu/drm/meson/Kconfig @@ -17,3 +17,10 @@ config DRM_MESON_DW_HDMI default y if DRM_MESON select DRM_DW_HDMI imply DRM_DW_HDMI_I2S_AUDIO + +config DRM_MESON_DW_MIPI_DSI + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display" + depends on DRM_MESON + default y if DRM_MESON + select DRM_DW_MIPI_DSI + select GENERIC_PHY_MIPI_DPHY diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 833e18c20603..43071bdbd4b9 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -6,3 +6,4 @@ meson-drm-y +=3D meson_encoder_hdmi.o meson_encoder_dsi.o =20 obj-$(CONFIG_DRM_MESON) +=3D meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) +=3D meson_dw_hdmi.o +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) +=3D meson_dw_mipi_dsi.o diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/me= son/meson_dw_mipi_dsi.c new file mode 100644 index 000000000000..52c8578914b6 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include