From nobody Mon Apr 27 08:41:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35C8BC43334 for ; Wed, 15 Jun 2022 07:08:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346468AbiFOHIy (ORCPT ); Wed, 15 Jun 2022 03:08:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345141AbiFOHIe (ORCPT ); Wed, 15 Jun 2022 03:08:34 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 073F92899B; Wed, 15 Jun 2022 00:08:33 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id o8so14060861wro.3; Wed, 15 Jun 2022 00:08:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2KF9TQbXAQaO0+lCyq0Pm6oIczmP+NGAwWhS+H2ag0I=; b=nxWF6vfTvRMvqC2OXTc3S/F+H+7Bp4aNqsHfCWFGbhvnC89Nsh4G1mSULS0/5MQzhg Y4gYcTjH23l/4iioN81St/KfV2pKDfU2dChXQa8ne8Ju02ic0Bm0pb9DyM6QoGlSwugH C016lNxcQmDW+Uq1yBA+1QBVY9R1cLptRhLP3RaRu7ioPf/Wvl7fbsRDz4Ah4XRajARo ogU5SI4Fh1D/SrNhvlKAlgJJqDYVMIIZYxU4+UjQ0OI542E624niyk/e0b6svEnHLKc5 EnpBTsa6H381WNxwnRuHe8oc8nLYsm2eBCKd27ZyXg5pmZKgCjZPOFQZYpTeCG5yTL5O 3HLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2KF9TQbXAQaO0+lCyq0Pm6oIczmP+NGAwWhS+H2ag0I=; b=UuJvtikB1iSY/3G1+3sya2YomHUj2fVnc4H4bQaflXGXM9xrFUTBLu4IFqccvf+W5p 5xQbRWrTyVJaDC6vHfYOcbYXpaZiWqWF87vmpjHNc/QGKQ37MjgQoG7rkIKPiRl/IwQ1 FoWZS/hnlyySTk1O7dG6quhZm7toWGP7TKiV/xfsIu3lU+qsYV0YNJn722AJ/LcoiOiD UJ4c2cM1KLR85aIUmvUle7XMwue2uVqRwCnA+rcmjuqT53ZTG6loQT3YtcVd+auUWVQ/ psQlfl9TIr0/Vaj5Ph58WoU5Uf8yoUbk1NLUwguhhUw0+Vd54fBUSZXzH24POjEjCY/I AVqw== X-Gm-Message-State: AJIora/6ivXLElD9lzQUIwFkNofOYj/5X01Ksr3L4ePc6HwlFjqDqNCN XVfNWOO6pa1K9Mqpn53d6bCvKO9sjkE= X-Google-Smtp-Source: AGRyM1tmEsuVgCBD/+wsO6NoYwOMQq6OCjFfmW6ttsay5izsZH2En83dJmD0ZLslZ5fHuRWzOobvwg== X-Received: by 2002:a05:6000:1445:b0:219:f383:40bc with SMTP id v5-20020a056000144500b00219f38340bcmr8447579wrx.53.1655276911312; Wed, 15 Jun 2022 00:08:31 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id i8-20020adffc08000000b0020c5253d8d0sm13562708wrr.28.2022.06.15.00.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 00:08:31 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: pwm: Add Mstar MSC313e PWM devicetree bindings documentation Date: Wed, 15 Jun 2022 09:08:09 +0200 Message-Id: <20220615070813.7720-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615070813.7720-1-romain.perier@gmail.com> References: <20220615070813.7720-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the documentation for the devicetree bindings of the Mstar MSC313e RTC driver, it includes MSC313e SoCs and SSD20xd. Signed-off-by: Romain Perier --- .../bindings/pwm/mstar,msc313e-pwm.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml b= /Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml new file mode 100644 index 000000000000..82f2357db085 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mstar,msc313e-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mstar MSC313e PWM controller + +allOf: + - $ref: "pwm.yaml#" + +maintainers: + - Daniel Palmer + - Romain Perier + +properties: + compatible: + oneOf: + - items: + - enum: + - mstar,msc313e-pwm + - mstar,ssd20xd-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm: pwm@3400 { + compatible =3D "mstar,msc313e-pwm"; + reg =3D <0x3400 0x400>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + }; --=20 2.35.1 From nobody Mon Apr 27 08:41:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49C10C433EF for ; Wed, 15 Jun 2022 07:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346529AbiFOHJA (ORCPT ); Wed, 15 Jun 2022 03:09:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345826AbiFOHIh (ORCPT ); Wed, 15 Jun 2022 03:08:37 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2417F286D2; Wed, 15 Jun 2022 00:08:34 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id w17so6540713wrg.7; Wed, 15 Jun 2022 00:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e1JEyMw9//6WaRTsGHLxDJ16bO40ZkIq+CAqfAPgOBs=; b=LcmSyFxRL1x5dkrrPS9mqDn4YSZOSAuYFfX+t/Bvsbzqx0rSGdnPI/UaAOwHHU8hj1 aN2D0pili4usxNogYd8qWsAJp15z6uHTsDaVt0e5rkZxm65VrKKD7FC9CdrFWMqbet0V QxwZZXBH+l3BslD+clW5X0f+OyP6rM+syhFsxS7JWLSAOfElJ8oRSFnzeEzRiFe7V4GN r/NonVO7rNapzHRgnuvHZTx6GHLc941p2NDp2l29aFYS7B56zTa2KTBH4h/MgXhzINap a9o9b+BiG266NGMSunIVj3Eiek9NR+HJo5vvZ/8GLonuoyNOiLdjVvO8EbAkoiSZWlDg nbZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e1JEyMw9//6WaRTsGHLxDJ16bO40ZkIq+CAqfAPgOBs=; b=Goybmv3ZvNgqnaiiMFZURfRXE+58BZsrxe/rUmmeM+NO5/kFPm6ixSquZyiR+onZFS P5bbGh1CQxY2lYfjZauCRTu3LpG/V9vlLkszqk9EMh51g4UBzeSeL7hvvwXvDUNfiJ9v ji9S/cDhWLFe/bRDaiZTXre1KbDFOcsknrlXnvJ3+QrSZN3f3SQBx+Qwtk3B4UgNdcKJ lEJiJEnM0lkteixj0DCWifjmuX13wjUQWrzNUxbo0wVT/S7Ujony47m8bAXR44sBJFP9 1I4AYUhk+I317qvpNSDyhWKngSffgUL7EexyD0pN6iLVpD3LUyF7AiSsMZxlCbtxSJL3 YqiA== X-Gm-Message-State: AJIora/KQ4vf7MnO+9X3UIL1AIc2Q6zblG8yqctci53mtyyMtqwhrAw0 XFM7qzVr7MmhPblRvdzyVjPB2pe9MZk= X-Google-Smtp-Source: AGRyM1u95w+pcsKEaV4PwxZT/Ixx+GSWE/3S6tT9Z1mAUZqmGQMCxfU51wCfe7Mq6Lnrqnb64uB1Pg== X-Received: by 2002:a05:6000:2c8:b0:218:4982:7f90 with SMTP id o8-20020a05600002c800b0021849827f90mr8470230wry.64.1655276912275; Wed, 15 Jun 2022 00:08:32 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id u18-20020a5d4352000000b002102af52a2csm16343132wrr.9.2022.06.15.00.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 00:08:31 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] pwm: Add support for the MSTAR MSC313 PWM Date: Wed, 15 Jun 2022 09:08:10 +0200 Message-Id: <20220615070813.7720-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615070813.7720-1-romain.perier@gmail.com> References: <20220615070813.7720-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer This adds support for the PWM block on the Mstar MSC313e SoCs and newer. Signed-off-by: Daniel Palmer Co-developed-by: Romain Perier Signed-off-by: Romain Perier --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-msc313e.c | 242 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 254 insertions(+) create mode 100644 drivers/pwm/pwm-msc313e.c diff --git a/MAINTAINERS b/MAINTAINERS index 2316278d9db9..45d001643b93 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2389,6 +2389,7 @@ F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/clocksource/timer-msc313e.c F: drivers/gpio/gpio-msc313.c +F: drivers/pwm/pwm-msc313e.c F: drivers/rtc/rtc-msc313.c F: drivers/watchdog/msc313e_wdt.c F: include/dt-bindings/clock/mstar-* diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 904de8d61828..802573122b25 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -651,6 +651,16 @@ config PWM_VT8500 To compile this driver as a module, choose M here: the module will be called pwm-vt8500. =20 +config PWM_MSC313E + tristate "MStar MSC313e PWM support" + depends on ARCH_MSTARV7 || COMPILE_TEST + help + Generic PWM framework driver for MSTAR MSC313e. + + To compile this driver as a module, choose M here: the module + will be called pwm-msc313e. + + config PWM_XILINX tristate "Xilinx AXI Timer PWM support" depends on OF_ADDRESS diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5c08bdb817b4..e24a48c78335 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -61,4 +61,5 @@ obj-$(CONFIG_PWM_TWL) +=3D pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) +=3D pwm-twl-led.o obj-$(CONFIG_PWM_VISCONTI) +=3D pwm-visconti.o obj-$(CONFIG_PWM_VT8500) +=3D pwm-vt8500.o +obj-$(CONFIG_PWM_MSC313E) +=3D pwm-msc313e.o obj-$(CONFIG_PWM_XILINX) +=3D pwm-xilinx.o diff --git a/drivers/pwm/pwm-msc313e.c b/drivers/pwm/pwm-msc313e.c new file mode 100644 index 000000000000..f20419c6b9be --- /dev/null +++ b/drivers/pwm/pwm-msc313e.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Daniel Palmer + * Copyright (C) 2022 Romain Perier + */ + +#include +#include +#include +#include + +#define DRIVER_NAME "msc313e-pwm" + +#define CHANNEL_OFFSET 0x80 +#define REG_DUTY 0x8 +#define REG_PERIOD 0x10 +#define REG_DIV 0x18 +#define REG_CTRL 0x1c +#define REG_SWRST 0x1fc + +struct msc313e_pwm_channel { + struct regmap_field *clkdiv; + struct regmap_field *polarity; + struct regmap_field *dutyl; + struct regmap_field *dutyh; + struct regmap_field *periodl; + struct regmap_field *periodh; + struct regmap_field *swrst; +}; + +struct msc313e_pwm { + struct regmap *regmap; + struct pwm_chip pwmchip; + struct clk *clk; + struct msc313e_pwm_channel channels[]; +}; + +struct msc313e_pwm_info { + unsigned int channels; +}; + +#define to_msc313e_pwm(ptr) container_of(ptr, struct msc313e_pwm, pwmchip) + +static const struct regmap_config msc313e_pwm_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 16, + .reg_stride =3D 4, +}; + +static const struct msc313e_pwm_info msc313e_data =3D { + .channels =3D 8, +}; + +static const struct msc313e_pwm_info ssd20xd_data =3D { + .channels =3D 4, +}; + +static void msc313e_pwm_writecounter(struct regmap_field *low, struct regm= ap_field *high, u32 value) +{ + regmap_field_write(low, value); + regmap_field_write(high, value >> 16); +} + +static int msc313e_pwm_config(struct pwm_chip *chip, struct pwm_device *de= vice, + int duty_ns, int period_ns) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + unsigned long long nspertick =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_= get_rate(pwm->clk)); + unsigned long long div =3D 1; + + /* fit the period into the period register by prescaling the clk */ + while (DIV_ROUND_CLOSEST_ULL(period_ns, (nspertick =3D DIV_ROUND_CLOSEST_= ULL(nspertick, div))) + > 0x3ffff){ + div++; + if (div > (0xffff + 1)) { + dev_err(chip->dev, "Can't fit period into period register\n"); + return -EINVAL; + } + } + + regmap_field_write(channel->clkdiv, div - 1); + msc313e_pwm_writecounter(channel->dutyl, channel->dutyh, + DIV_ROUND_CLOSEST_ULL(duty_ns, nspertick)); + msc313e_pwm_writecounter(channel->periodl, channel->periodh, + DIV_ROUND_CLOSEST_ULL(period_ns, nspertick)); + + return 0; +}; + +static int msc313e_pwm_set_polarity(struct pwm_chip *chip, struct pwm_devi= ce *device, + enum pwm_polarity polarity) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + unsigned int pol =3D 0; + + if (polarity =3D=3D PWM_POLARITY_INVERSED) + pol =3D 1; + regmap_field_update_bits(channel->polarity, 1, pol); + + return 0; +} + +static int msc313e_pwm_enable(struct pwm_chip *chip, struct pwm_device *de= vice) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + int ret; + + ret =3D clk_prepare_enable(pwm->clk); + if (ret) + return ret; + + regmap_field_write(channel->swrst, 0); + + return 0; +} + +static void msc313e_pwm_disable(struct pwm_chip *chip, struct pwm_device *= device) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + + regmap_field_write(channel->swrst, 1); + clk_disable(pwm->clk); +} + +static int msc313e_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + if (state->enabled) { + msc313e_pwm_enable(chip, pwm); + msc313e_pwm_set_polarity(chip, pwm, state->polarity); + msc313e_pwm_config(chip, pwm, state->duty_cycle, state->period); + } else { + msc313e_pwm_disable(chip, pwm); + } + return 0; +} + +static void msc313e_get_state(struct pwm_chip *chip, struct pwm_device *de= vice, + struct pwm_state *state) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + unsigned int pol =3D 0; + + regmap_field_read(channel->polarity, &pol); + state->polarity =3D pol; +} + +static const struct pwm_ops msc313e_pwm_ops =3D { + .config =3D msc313e_pwm_config, + .set_polarity =3D msc313e_pwm_set_polarity, + .enable =3D msc313e_pwm_enable, + .disable =3D msc313e_pwm_disable, + .apply =3D msc313e_apply, + .get_state =3D msc313e_get_state, + .owner =3D THIS_MODULE +}; + +static int msc313e_pwm_probe(struct platform_device *pdev) +{ + const struct msc313e_pwm_info *match_data; + struct device *dev =3D &pdev->dev; + struct msc313e_pwm *pwm; + __iomem void *base; + int i; + + match_data =3D of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + pwm =3D devm_kzalloc(dev, struct_size(pwm, channels, match_data->channels= ), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), "Cannot get clk\n"); + + pwm->regmap =3D devm_regmap_init_mmio(dev, base, &msc313e_pwm_regmap_conf= ig); + if (IS_ERR(pwm->regmap)) + return dev_err_probe(dev, PTR_ERR(pwm->regmap), "Cannot get regmap\n"); + + for (i =3D 0; i < match_data->channels; i++) { + unsigned int offset =3D CHANNEL_OFFSET * i; + struct reg_field div_clkdiv_field =3D REG_FIELD(offset + REG_DIV, 0, 7); + struct reg_field ctrl_polarity_field =3D REG_FIELD(offset + REG_CTRL, 4,= 4); + struct reg_field dutyl_field =3D REG_FIELD(offset + REG_DUTY, 0, 15); + struct reg_field dutyh_field =3D REG_FIELD(offset + REG_DUTY + 4, 0, 2); + struct reg_field periodl_field =3D REG_FIELD(offset + REG_PERIOD, 0, 15); + struct reg_field periodh_field =3D REG_FIELD(offset + REG_PERIOD + 4, 0,= 2); + struct reg_field swrst_field =3D REG_FIELD(REG_SWRST, i, i); + + pwm->channels[i].clkdiv =3D devm_regmap_field_alloc(dev, pwm->regmap, + div_clkdiv_field); + pwm->channels[i].polarity =3D devm_regmap_field_alloc(dev, pwm->regmap, + ctrl_polarity_field); + pwm->channels[i].dutyl =3D devm_regmap_field_alloc(dev, pwm->regmap, dut= yl_field); + pwm->channels[i].dutyh =3D devm_regmap_field_alloc(dev, pwm->regmap, dut= yh_field); + pwm->channels[i].periodl =3D devm_regmap_field_alloc(dev, pwm->regmap, p= eriodl_field); + pwm->channels[i].periodh =3D devm_regmap_field_alloc(dev, pwm->regmap, p= eriodh_field); + pwm->channels[i].swrst =3D devm_regmap_field_alloc(dev, pwm->regmap, swr= st_field); + } + + pwm->pwmchip.dev =3D dev; + pwm->pwmchip.ops =3D &msc313e_pwm_ops; + pwm->pwmchip.base =3D -1; + pwm->pwmchip.npwm =3D match_data->channels; + pwm->pwmchip.of_xlate =3D of_pwm_xlate_with_flags; + pwm->pwmchip.of_pwm_n_cells =3D 3; + + platform_set_drvdata(pdev, pwm); + + return devm_pwmchip_add(dev, &pwm->pwmchip); +} + +static const struct of_device_id msc313e_pwm_dt_ids[] =3D { + { .compatible =3D "mstar,msc313e-pwm", .data =3D &msc313e_data }, + { .compatible =3D "mstar,ssd20xd-pwm", .data =3D &ssd20xd_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, msc313e_pwm_dt_ids); + +static struct platform_driver msc313e_pwm_driver =3D { + .probe =3D msc313e_pwm_probe, + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D msc313e_pwm_dt_ids, + }, +}; +module_platform_driver(msc313e_pwm_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Mstar MSC313e PWM driver"); +MODULE_AUTHOR("Daniel Palmer "); --=20 2.35.1 From nobody Mon Apr 27 08:41:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AC20C433EF for ; Wed, 15 Jun 2022 07:09:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346399AbiFOHJP (ORCPT ); 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Wed, 15 Jun 2022 00:08:32 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] ARM: dts: mstar: Add pwm device node to infinity Date: Wed, 15 Jun 2022 09:08:11 +0200 Message-Id: <20220615070813.7720-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615070813.7720-1-romain.perier@gmail.com> References: <20220615070813.7720-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the definition of the pwm device node. The PWM being able to work with the oscillator at 12Mhz for now, it shares the same xtal than other devices (rtc or watchdog for instance). Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/msta= r-infinity.dtsi index 441a917b88ba..752f4c26b31c 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -38,6 +38,16 @@ opp-800000000 { }; }; =20 +&soc { + pm_pwm: pwm@1f001da0 { + compatible =3D "mstar,msc313-pwm"; + reg =3D <0x1f001da0 0xc>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + status =3D "disabled"; + }; +}; + &cpu0 { operating-points-v2 =3D <&cpu0_opp_table>; }; --=20 2.35.1 From nobody Mon Apr 27 08:41:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24A10C433EF for ; Wed, 15 Jun 2022 07:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346730AbiFOHJH (ORCPT ); Wed, 15 Jun 2022 03:09:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345951AbiFOHIi (ORCPT ); Wed, 15 Jun 2022 03:08:38 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FF7C2899B; Wed, 15 Jun 2022 00:08:36 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id o37-20020a05600c512500b0039c4ba4c64dso586951wms.2; Wed, 15 Jun 2022 00:08:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cg9l8Dw5kbbaSW9iT/X0V7LIeInZuZuCPQHiyAl6l3A=; b=HSMAYc+f0kXflnPy03sKUdNFiTOuQZ3iMe+rh62nN4LXiC5pFvFZkSxmi7+eXnkHZZ 13FhRm49eumOmOzDZ0vi4jZNma5HJZEMeR1VPXqgNF24XkIWyzsLtYcrg2tgSAC56nng gYGbLWNqfhVJnIaZjqy7RRnUDw9V8BlR6LYF2hEZF851bJbi2O7gO/JOI7TgAnQG0lzj u7TGYOqa0C3DHVmfV9Fln7dswaHmqahG5AKzWlkIhaMXmWofXp9KWk9odTXLBXfcwNSP TnIz0CSDc841W3GpniUIrkM3Rb5HhkH3SK3Ljyhz3aH4vduqqisogxMF+bg+Ms+l4ZFp 2tPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cg9l8Dw5kbbaSW9iT/X0V7LIeInZuZuCPQHiyAl6l3A=; b=IOV2NrtA3yD/HfCbeU1wtynsgHEW91AOfqcLSNBB+rK/c61HPuim/ruh4taLHy5SH6 eTEfU2ZlGzFizd/XOu+iCgPV5TEuPKeg1hSY7zoC54ILpgKfirEV+6d9hyrxVezWLKit nhwyZGhp8HV4vmYMEgHBGfoNXm5ZOyfs3uzb28YA6Wk68/rN9GLpLBft0lNGUZbvhaYq RKNLhmDVpNX4zqhMwz7ESIJG2olCeYYJPZOXp1H6r7EJsPtpaAg9gX3jkzTR2T0hLuXr xpmrfFAsWLuFxPIfepAKN8YpsUBfac+hqBGJmQppnCZv1EIqgptwI4dK8bQwFXfRq+c5 qotQ== X-Gm-Message-State: AOAM530jslE4D4cILVjyYFg5RW/phCL4LCBgrZGV24RAqZdrJe7nboK6 DmJFISaFNnXyNlAOgf6b0pHZIqDk/Sg= X-Google-Smtp-Source: ABdhPJz8/duArN33thJ3UidKgsyl5Z3GS7szdDEqz4eiDcM555QgOBVw1pc9kTlG6+JTXnZMKPrvTA== X-Received: by 2002:a05:600c:240c:b0:39c:5b4b:f3c7 with SMTP id 12-20020a05600c240c00b0039c5b4bf3c7mr8244118wmp.127.1655276914191; Wed, 15 Jun 2022 00:08:34 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id l9-20020a5d4809000000b00219e8d28fb1sm13814277wrq.57.2022.06.15.00.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 00:08:33 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] ARM: dts: mstar: Add pwm device node to infinity3 Date: Wed, 15 Jun 2022 09:08:12 +0200 Message-Id: <20220615070813.7720-5-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615070813.7720-1-romain.perier@gmail.com> References: <20220615070813.7720-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the definition of the pwm device node. The PWM being able to work with the oscillator at 12Mhz for now, it shares the same xtal than other devices (rtc or watchdog for instance). Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity3.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mst= ar-infinity3.dtsi index a56cf29e5d82..aa26f25392d0 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -67,3 +67,13 @@ opp-1512000000 { &imi { reg =3D <0xa0000000 0x20000>; }; + +&riu { + pwm: pwm@3400 { + compatible =3D "mstar,msc313e-pwm"; + reg =3D <0x3400 0x400>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + status =3D "disabled"; + }; +}; --=20 2.35.1 From nobody Mon Apr 27 08:41:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47EE6C43334 for ; Wed, 15 Jun 2022 07:09:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352684AbiFOHJM (ORCPT ); Wed, 15 Jun 2022 03:09:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345944AbiFOHIi (ORCPT ); Wed, 15 Jun 2022 03:08:38 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18ED92937A; Wed, 15 Jun 2022 00:08:36 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id q15so5797397wmj.2; Wed, 15 Jun 2022 00:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XhHHfhBS4JEZS5T4Cqsky8UODYiFkR3zFwNbdfWOgRM=; b=B3CYB6Nl2KGF+oCOFeUR6gZzBF3a3b32bAom3UR9EAoLMEnX+yxruYjwcNyBnMBYkl Dk9BQ01Wzx7JQFlgvVgUTMRUSac8nLBg3mCEVa9T7qiJijaj7dlNeik5AC5x9NSD2ggd KWYDvbjRazPZ3QxQnCG0Ep6zIUM7F8LSdT5qo3J/B8bdJvx07PY3wZlwtePuDNpIXHry AVqwQKpUvEv7KscMM8dojQH/4hQoa0FJx4gF9vfm/LMOS+v1EpZwLwPRkZ6u2WyQFRvG /lDDxNO88QNANusB4C1VCw6pGFEV0gCvpHwAzbxygUE7zrSsmKWlbfSoYR2Ipo0/Wydf czww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XhHHfhBS4JEZS5T4Cqsky8UODYiFkR3zFwNbdfWOgRM=; b=7CGjM8W+htJGrOKACeV2f0ytq05EoI5kR81ZM4hvVz+bvBx7qTSDv0vNPNSPQ7AdLW cfYH/DpCGE70DDRsM2VqpChBi5sNEf/x+0ETh96Q87bVf2Zaoh7cmYxhNCDRogZY1XyJ axR1Y/EC667eEvW6grTB7RErw+tux7EOJm0kBBPexoY+Ac6Oe2rB4ma0Ufr1Xc1KSlOA ukOdYVQnlwvZUHvCi8sawU5DHjwKMpzKaWcPKfvyxied2ji3KHOGPhCBYoQh3TNOWfsT NVPn+ke9sUKorbHzxj1GXz1rziPA8raFpfNKX2A30IOCe6ihOCz3cL3nsd3zdp4sfi6c 44gQ== X-Gm-Message-State: AOAM532VJlZhoPzGRtMaC621lfMrwxeD/0LahkqfQvqugROstzD30hPK fENpHnjGd2sTcktL3hRFnDJAxXo+liY= X-Google-Smtp-Source: ABdhPJx4NWtb3vWFFFfgrtFkg5c3A3KxJh3ThnO9v7JUj7JFhsIT9FFGr1tDDi/+cINTfg5V5a/R7Q== X-Received: by 2002:a7b:ce87:0:b0:39c:5509:660c with SMTP id q7-20020a7bce87000000b0039c5509660cmr8103989wmj.163.1655276915130; Wed, 15 Jun 2022 00:08:35 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id n10-20020a056000170a00b00219fb3a275csm12058044wrc.16.2022.06.15.00.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 00:08:34 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] ARM: dts: mstar: Add pwm device node to infinity2m Date: Wed, 15 Jun 2022 09:08:13 +0200 Message-Id: <20220615070813.7720-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615070813.7720-1-romain.perier@gmail.com> References: <20220615070813.7720-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds definition of the pwm device node, infinity2m has its own hardware variant, so use the one for ssd20xd. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/ms= tar-infinity2m.dtsi index 1b485efd7156..70561e512483 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -32,6 +32,14 @@ cpu1: cpu@1 { }; =20 &riu { + pwm: pwm@3400 { + compatible =3D "mstar,ssd20xd-pwm"; + reg =3D <0x3400 0x400>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + status =3D "disabled"; + }; + smpctrl: smpctrl@204000 { reg =3D <0x204000 0x200>; status =3D "disabled"; --=20 2.35.1