From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF094C43334 for ; Wed, 15 Jun 2022 03:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350734AbiFODwG (ORCPT ); Tue, 14 Jun 2022 23:52:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242691AbiFODvy (ORCPT ); Tue, 14 Jun 2022 23:51:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A07B50052; Tue, 14 Jun 2022 20:51:53 -0700 (PDT) X-UUID: ba15bb8b701041b5a2d5e253e71e6738-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:8fe5c023-5296-4bef-b65a-3b9abb7a4a72,OB:20,L OB:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.6,REQID:8fe5c023-5296-4bef-b65a-3b9abb7a4a72,OB:20,LOB :20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:b14ad71,CLOUDID:99988548-4c92-421c-ad91-b806c0f58b2a,C OID:91aab2dd5763,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: ba15bb8b701041b5a2d5e253e71e6738-20220615 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1940988244; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 15 Jun 2022 11:51:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:47 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 01/10] scsi: ufs: Export ufshcd_uic_change_pwr_mode() Date: Wed, 15 Jun 2022 11:51:37 +0800 Message-ID: <20220615035146.20964-2-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Export ufshcd_uic_change_pwr_mode() to allow vendors to use it for SoC-specific power mode change design limitation. Signed-off-by: Stanley Chu Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufshcd.c | 3 ++- include/ufs/ufshcd.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 936a6d5467c9..19e17c898319 100755 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -4091,7 +4091,7 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, s= truct uic_command *cmd) * * Returns 0 on success, non-zero value on failure */ -static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) +int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) { struct uic_command uic_cmd =3D {0}; int ret; @@ -4116,6 +4116,7 @@ static int ufshcd_uic_change_pwr_mode(struct ufs_hba = *hba, u8 mode) out: return ret; } +EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); =20 int ufshcd_link_recovery(struct ufs_hba *hba) { diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index a92271421718..aa778418703f 100755 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1087,6 +1087,7 @@ extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u= 32 attr_sel, u32 *mib_val, u8 peer); extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, struct ufs_pa_layer_attr *desired_pwr_mode); +extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); =20 /* UIC command interfaces for DME primitives */ #define DME_LOCAL 0 --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A000BC43334 for ; Wed, 15 Jun 2022 03:52:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352180AbiFODwR (ORCPT ); Tue, 14 Jun 2022 23:52:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345973AbiFODwA (ORCPT ); Tue, 14 Jun 2022 23:52:00 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 800CD5007A; Tue, 14 Jun 2022 20:51:56 -0700 (PDT) X-UUID: e022241d994847ea91090fc4d5902a66-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:fdb8ce08-498b-4468-be54-8fde2bd976ac,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.6,REQID:fdb8ce08-498b-4468-be54-8fde2bd976ac,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:b14ad71,CLOUDID:903b42f6-e099-41ba-a32c-13b8bfe63214,C OID:4a4ece901a66,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: e022241d994847ea91090fc4d5902a66-20220615 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1673418355; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 15 Jun 2022 11:51:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:47 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 02/10] scsi: ufs: Fix ADAPT logic for HS-G5 Date: Wed, 15 Jun 2022 11:51:38 +0800 Message-ID: <20220615035146.20964-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ADAPT now is added not only for HS Gear4 mode but also higher gears. Fix the logic for higher gears. Signed-off-by: Stanley Chu Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufshcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 19e17c898319..0d16739c67bb 100755 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -3802,7 +3802,7 @@ int ufshcd_dme_configure_adapt(struct ufs_hba *hba, { int ret; =20 - if (agreed_gear !=3D UFS_HS_G4) + if (agreed_gear < UFS_HS_G4) adapt_val =3D PA_NO_ADAPT; =20 ret =3D ufshcd_dme_set(hba, --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F26C43334 for ; Wed, 15 Jun 2022 03:52:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352565AbiFODwf (ORCPT ); Tue, 14 Jun 2022 23:52:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245517AbiFODv7 (ORCPT ); Tue, 14 Jun 2022 23:51:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75D5E50061; Tue, 14 Jun 2022 20:51:55 -0700 (PDT) X-UUID: 2f8955f5b8404c0891c57a0afd0da378-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:8ee769de-2339-4bcb-9c10-d93837912692,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:d1988548-4c92-421c-ad91-b806c0f58b2a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 2f8955f5b8404c0891c57a0afd0da378-20220615 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1013656087; Wed, 15 Jun 2022 11:51:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 15 Jun 2022 11:51:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:47 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , , Peter Wang Subject: [PATCH v4 03/10] scsi: ufs-mediatek: Introduce workaround for power mode change Date: Wed, 15 Jun 2022 11:51:39 +0800 Message-ID: <20220615035146.20964-4-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: CC Chou Some MediaTek SoC chips need special flow for power mode change, especially for chips supporting HS-G5. Enable the workaround by setting the host-specific capability. Reviewed-by: Stanley Chu Signed-off-by: CC Chou Signed-off-by: Eddie Huang Signed-off-by: Dennis Yu Signed-off-by: Peter Wang Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 60 +++++++++++++++++++++++++++++++-- drivers/ufs/host/ufs-mediatek.h | 1 + include/ufs/unipro.h | 1 + 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index beabc3ccd30b..2931fd21e38a 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -82,6 +82,13 @@ static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba) return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC); } =20 +static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + + return (host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO); +} + static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable) { u32 tmp; @@ -579,6 +586,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) if (of_property_read_bool(np, "mediatek,ufs-broken-vcc")) host->caps |=3D UFS_MTK_CAP_BROKEN_VCC; =20 + if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto")) + host->caps |=3D UFS_MTK_CAP_PMC_VIA_FASTAUTO; + dev_info(hba->dev, "caps: 0x%x", host->caps); } =20 @@ -754,6 +764,26 @@ static int ufs_mtk_init(struct ufs_hba *hba) return err; } =20 +static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba, + struct ufs_pa_layer_attr *dev_req_params) +{ + if (!ufs_mtk_is_pmc_via_fastauto(hba)) + return false; + + if (dev_req_params->hs_rate =3D=3D hba->pwr_info.hs_rate) + return false; + + if (dev_req_params->pwr_tx !=3D FAST_MODE && + dev_req_params->gear_tx < UFS_HS_G4) + return false; + + if (dev_req_params->pwr_rx !=3D FAST_MODE && + dev_req_params->gear_rx < UFS_HS_G4) + return false; + + return true; +} + static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) @@ -763,8 +793,8 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, int ret; =20 ufshcd_init_pwr_dev_param(&host_cap); - host_cap.hs_rx_gear =3D UFS_HS_G4; - host_cap.hs_tx_gear =3D UFS_HS_G4; + host_cap.hs_rx_gear =3D UFS_HS_G5; + host_cap.hs_tx_gear =3D UFS_HS_G5; =20 ret =3D ufshcd_get_pwr_dev_param(&host_cap, dev_max_params, @@ -774,6 +804,32 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, __func__); } =20 + if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) { + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1); + + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), UFS_HS_G1); + + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), + dev_req_params->lane_tx); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), + dev_req_params->lane_rx); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), + dev_req_params->hs_rate); + + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), + PA_NO_ADAPT); + + ret =3D ufshcd_uic_change_pwr_mode(hba, + FASTAUTO_MODE << 4 | FASTAUTO_MODE); + + if (ret) { + dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=3D%d\n", + __func__, ret); + } + } + if (host->hw_ver.major >=3D 3) { ret =3D ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 414dca86c09f..7e1913769671 100755 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -108,6 +108,7 @@ enum ufs_mtk_host_caps { UFS_MTK_CAP_VA09_PWR_CTRL =3D 1 << 1, UFS_MTK_CAP_DISABLE_AH8 =3D 1 << 2, UFS_MTK_CAP_BROKEN_VCC =3D 1 << 3, + UFS_MTK_CAP_PMC_VIA_FASTAUTO =3D 1 << 6, }; =20 struct ufs_mtk_crypt_cfg { diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h index 0521f887e3ac..4b13fbf8ee18 100755 --- a/include/ufs/unipro.h +++ b/include/ufs/unipro.h @@ -229,6 +229,7 @@ enum ufs_hs_gear_tag { UFS_HS_G2, /* HS Gear 2 */ UFS_HS_G3, /* HS Gear 3 */ UFS_HS_G4, /* HS Gear 4 */ + UFS_HS_G5 /* HS Gear 5 */ }; =20 enum ufs_unipro_ver { --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86D98C43334 for ; Wed, 15 Jun 2022 03:52:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352366AbiFODwW (ORCPT ); Tue, 14 Jun 2022 23:52:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243935AbiFODvz (ORCPT ); Tue, 14 Jun 2022 23:51:55 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D13B5005C; Tue, 14 Jun 2022 20:51:54 -0700 (PDT) X-UUID: c18f29a48f05423c99837394ee980326-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:7571b997-be80-4f2f-9ea4-59d6b3acca00,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:cf988548-4c92-421c-ad91-b806c0f58b2a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: c18f29a48f05423c99837394ee980326-20220615 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 912029533; Wed, 15 Jun 2022 11:51:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 15 Jun 2022 11:51:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:47 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 04/10] scsi: ufs-mediatek: Fix the timing of configuring device regulators Date: Wed, 15 Jun 2022 11:51:40 +0800 Message-ID: <20220615035146.20964-5-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Po-Wen Kao Currently the LPM configurations of device regulators may not work since VCC is not disabled yet while ufs_mtk_vreg_set_lpm() is executed. Fix it by changing the timing of invoking ufs_mtk_vreg_set_lpm(). Reviewed-by: Stanley Chu Signed-off-by: Po-Wen Kao Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 58 ++++++++++++++++++++++++++++++--- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 2931fd21e38a..817d957512a3 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1082,7 +1082,6 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum = ufs_pm_op pm_op, * ufshcd_suspend() re-enabling regulators while vreg is still * in low-power mode. */ - ufs_mtk_vreg_set_lpm(hba, true); err =3D ufs_mtk_mphy_power_on(hba, false); if (err) goto fail; @@ -1106,12 +1105,13 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum= ufs_pm_op pm_op) { int err; =20 + if (hba->ufshcd_state !=3D UFSHCD_STATE_OPERATIONAL) + ufs_mtk_vreg_set_lpm(hba, false); + err =3D ufs_mtk_mphy_power_on(hba, true); if (err) goto fail; =20 - ufs_mtk_vreg_set_lpm(hba, false); - if (ufshcd_is_link_hibern8(hba)) { err =3D ufs_mtk_link_set_hpm(hba); if (err) @@ -1276,9 +1276,57 @@ static int ufs_mtk_remove(struct platform_device *pd= ev) return 0; } =20 +int ufs_mtk_system_suspend(struct device *dev) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + int ret; + + ret =3D ufshcd_system_suspend(dev); + if (ret) + return ret; + + ufs_mtk_vreg_set_lpm(hba, true); + + return 0; +} + +int ufs_mtk_system_resume(struct device *dev) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + + ufs_mtk_vreg_set_lpm(hba, false); + + return ufshcd_system_resume(dev); +} + +int ufs_mtk_runtime_suspend(struct device *dev) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + int ret =3D 0; + + ret =3D ufshcd_runtime_suspend(dev); + if (ret) + return ret; + + ufs_mtk_vreg_set_lpm(hba, true); + + return 0; +} + +int ufs_mtk_runtime_resume(struct device *dev) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + + ufs_mtk_vreg_set_lpm(hba, false); + + return ufshcd_runtime_resume(dev); +} + static const struct dev_pm_ops ufs_mtk_pm_ops =3D { - SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) - SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(ufs_mtk_system_suspend, + ufs_mtk_system_resume) + SET_RUNTIME_PM_OPS(ufs_mtk_runtime_suspend, + ufs_mtk_runtime_resume, NULL) .prepare =3D ufshcd_suspend_prepare, .complete =3D ufshcd_resume_complete, }; --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 624ADC43334 for ; Wed, 15 Jun 2022 03:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351239AbiFODwK (ORCPT ); Tue, 14 Jun 2022 23:52:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242989AbiFODvz (ORCPT ); Tue, 14 Jun 2022 23:51:55 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B2F750053; Tue, 14 Jun 2022 20:51:54 -0700 (PDT) X-UUID: e2042728323d447489e38b32e5576eeb-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:fb538b12-5519-4d3b-b11b-8b298200fef3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:b14ad71,CLOUDID:4f3b42f6-e099-41ba-a32c-13b8bfe63214,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: e2042728323d447489e38b32e5576eeb-20220615 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1872199788; Wed, 15 Jun 2022 11:51:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 15 Jun 2022 11:51:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:47 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 05/10] scsi: ufs-mediatek: Prevent device regulators setting as LPM incorrectly Date: Wed, 15 Jun 2022 11:51:41 +0800 Message-ID: <20220615035146.20964-6-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Po-Wen Kao Device regulatrs are allowed to enter low-power mode if neither device is not in active mode, nor VCC does not keep on. Simply fix this by adding conditions before LPM decision. Reviewed-by: Stanley Chu Signed-off-by: Po-Wen Kao Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 817d957512a3..03762ecaaaf8 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1034,10 +1034,18 @@ static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hb= a, bool lpm) if (!hba->vreg_info.vccq2 || !hba->vreg_info.vcc) return; =20 - if (lpm && !hba->vreg_info.vcc->enabled) + /* Bypass LPM when device is still active */ + if (lpm && ufshcd_is_ufs_dev_active(hba)) + return; + + /* Bypass LPM if VCC is enabled */ + if (lpm && hba->vreg_info.vcc->enabled) + return; + + if (lpm) regulator_set_mode(hba->vreg_info.vccq2->reg, REGULATOR_MODE_IDLE); - else if (!lpm) + else regulator_set_mode(hba->vreg_info.vccq2->reg, REGULATOR_MODE_NORMAL); } --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C7C3C433EF for ; Wed, 15 Jun 2022 03:52:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352949AbiFODwv (ORCPT ); Tue, 14 Jun 2022 23:52:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244518AbiFODv4 (ORCPT ); Tue, 14 Jun 2022 23:51:56 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FA1E5005E; Tue, 14 Jun 2022 20:51:55 -0700 (PDT) X-UUID: 6da093a912f34a91b69678f47be0baf4-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:b5310148-119a-4f24-84b7-7ec94e8d2fe6,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:b14ad71,CLOUDID:503b42f6-e099-41ba-a32c-13b8bfe63214,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 6da093a912f34a91b69678f47be0baf4-20220615 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1469923884; Wed, 15 Jun 2022 11:51:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:47 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 06/10] scsi: ufs-mediatek: Support low-power mode for VCCQ Date: Wed, 15 Jun 2022 11:51:42 +0800 Message-ID: <20220615035146.20964-7-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Peter Wang Also allow VCCQ to enter low-power mode, and meanwhile remove the restriction of VCC because VCCQ/VCCQ2 can be changed to low-power mode even if VCC keeps on while the device is not in active power mode. Reviewed-by: Stanley Chu Signed-off-by: Peter Wang Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 03762ecaaaf8..65a2a4185ef6 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1031,7 +1031,13 @@ static int ufs_mtk_link_set_lpm(struct ufs_hba *hba) =20 static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) { - if (!hba->vreg_info.vccq2 || !hba->vreg_info.vcc) + struct ufs_vreg *vccqx =3D NULL; + + if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2) + return; + + /* Skip if VCC is assumed always-on */ + if (!hba->vreg_info.vcc) return; =20 /* Bypass LPM when device is still active */ @@ -1042,12 +1048,13 @@ static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hb= a, bool lpm) if (lpm && hba->vreg_info.vcc->enabled) return; =20 - if (lpm) - regulator_set_mode(hba->vreg_info.vccq2->reg, - REGULATOR_MODE_IDLE); + if (hba->vreg_info.vccq) + vccqx =3D hba->vreg_info.vccq; else - regulator_set_mode(hba->vreg_info.vccq2->reg, - REGULATOR_MODE_NORMAL); + vccqx =3D hba->vreg_info.vccq2; + + regulator_set_mode(vccqx->reg, + lpm ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL); } =20 static void ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba) --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0033C43334 for ; Wed, 15 Jun 2022 03:52:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352724AbiFODwo (ORCPT ); Tue, 14 Jun 2022 23:52:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346094AbiFODwB (ORCPT ); Tue, 14 Jun 2022 23:52:01 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CA7850444; Tue, 14 Jun 2022 20:51:57 -0700 (PDT) X-UUID: 032664d8cb7e4d92a20e014f866915f9-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:8bf3ac1c-06a2-439f-a118-574bf3bd0704,OB:30,L OB:30,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:90 X-CID-INFO: VERSION:1.1.6,REQID:8bf3ac1c-06a2-439f-a118-574bf3bd0704,OB:30,LOB :30,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:90 X-CID-META: VersionHash:b14ad71,CLOUDID:08998548-4c92-421c-ad91-b806c0f58b2a,C OID:91aab2dd5763,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 032664d8cb7e4d92a20e014f866915f9-20220615 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 958148378; Wed, 15 Jun 2022 11:51:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:48 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 07/10] scsi: ufs-mediatek: Support flexible parameters for smc calls Date: Wed, 15 Jun 2022 11:51:43 +0800 Message-ID: <20220615035146.20964-8-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide flexible number of parameters for UFS SMC calls to be easily used for future SMC usages. This is a preparation patch for the next patch. Signed-off-by: Alice Chao Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 16 -------------- drivers/ufs/host/ufs-mediatek.h | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 65a2a4185ef6..9c5d1213c290 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -30,22 +30,6 @@ #define CREATE_TRACE_POINTS #include "ufs-mediatek-trace.h" =20 -#define ufs_mtk_smc(cmd, val, res) \ - arm_smccc_smc(MTK_SIP_UFS_CONTROL, \ - cmd, val, 0, 0, 0, 0, 0, &(res)) - -#define ufs_mtk_va09_pwr_ctrl(res, on) \ - ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, on, res) - -#define ufs_mtk_crypto_ctrl(res, enable) \ - ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, enable, res) - -#define ufs_mtk_ref_clk_notify(on, res) \ - ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res) - -#define ufs_mtk_device_reset_ctrl(high, res) \ - ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res) - static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] =3D { { .wmanufacturerid =3D UFS_VENDOR_MICRON, .model =3D UFS_ANY_MODEL, diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 7e1913769671..bf6ca96cafb6 100755 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -143,4 +143,43 @@ struct ufs_mtk_host { u32 ip_ver; }; =20 +/* + * SMC call wrapper function + */ +struct ufs_mtk_smc_arg { + unsigned long cmd; + struct arm_smccc_res *res; + unsigned long v1; + unsigned long v2; + unsigned long v3; + unsigned long v4; + unsigned long v5; + unsigned long v6; + unsigned long v7; +}; + +static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) +{ + arm_smccc_smc(MTK_SIP_UFS_CONTROL, + s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); +} + +#define ufs_mtk_smc(...) \ + _ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__}) + +/* + * SMC call interface + */ +#define ufs_mtk_va09_pwr_ctrl(res, on) \ + ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on) + +#define ufs_mtk_crypto_ctrl(res, enable) \ + ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable) + +#define ufs_mtk_ref_clk_notify(on, res) \ + ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on) + +#define ufs_mtk_device_reset_ctrl(high, res) \ + ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high) + #endif /* !_UFS_MEDIATEK_H */ --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A0A9C43334 for ; Wed, 15 Jun 2022 03:52:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352483AbiFODw2 (ORCPT ); Tue, 14 Jun 2022 23:52:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346065AbiFODwB (ORCPT ); Tue, 14 Jun 2022 23:52:01 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E1A250072; Tue, 14 Jun 2022 20:51:56 -0700 (PDT) X-UUID: 6fc14475d1854d8a9fdcc2d021dd096e-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:8a1f4f1d-f19a-4455-96da-e52e35236fab,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:90 X-CID-INFO: VERSION:1.1.6,REQID:8a1f4f1d-f19a-4455-96da-e52e35236fab,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:90 X-CID-META: VersionHash:b14ad71,CLOUDID:d0988548-4c92-421c-ad91-b806c0f58b2a,C OID:4a4ece901a66,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 6fc14475d1854d8a9fdcc2d021dd096e-20220615 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 390776483; Wed, 15 Jun 2022 11:51:50 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:48 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 08/10] scsi: ufs-mediatek: Support low-power mode for parents of VCCQx Date: Wed, 15 Jun 2022 11:51:44 +0800 Message-ID: <20220615035146.20964-9-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide the facility to configure parents of VCCQx power rails as low-power or full-power mode in MediaTek UFS platforms. Signed-off-by: Alice Chao Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 46 +++++++++++++++++++++++---------- drivers/ufs/host/ufs-mediatek.h | 4 +++ 2 files changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 9c5d1213c290..e756aba45acd 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1013,10 +1013,30 @@ static int ufs_mtk_link_set_lpm(struct ufs_hba *hba) return 0; } =20 -static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm) +static void ufs_mtk_vccqx_set_lpm(struct ufs_hba *hba, bool lpm) { struct ufs_vreg *vccqx =3D NULL; =20 + if (hba->vreg_info.vccq) + vccqx =3D hba->vreg_info.vccq; + else + vccqx =3D hba->vreg_info.vccq2; + + regulator_set_mode(vccqx->reg, + lpm ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL); +} + +static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm) +{ + struct arm_smccc_res res; + + ufs_mtk_device_pwr_ctrl(!lpm, + (unsigned long)hba->dev_info.wspecversion, + res); +} + +static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm) +{ if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2) return; =20 @@ -1032,13 +1052,13 @@ static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hb= a, bool lpm) if (lpm && hba->vreg_info.vcc->enabled) return; =20 - if (hba->vreg_info.vccq) - vccqx =3D hba->vreg_info.vccq; - else - vccqx =3D hba->vreg_info.vccq2; - - regulator_set_mode(vccqx->reg, - lpm ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL); + if (lpm) { + ufs_mtk_vccqx_set_lpm(hba, lpm); + ufs_mtk_vsx_set_lpm(hba, lpm); + } else { + ufs_mtk_vsx_set_lpm(hba, lpm); + ufs_mtk_vccqx_set_lpm(hba, lpm); + } } =20 static void ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba) @@ -1105,7 +1125,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum u= fs_pm_op pm_op) int err; =20 if (hba->ufshcd_state !=3D UFSHCD_STATE_OPERATIONAL) - ufs_mtk_vreg_set_lpm(hba, false); + ufs_mtk_dev_vreg_set_lpm(hba, false); =20 err =3D ufs_mtk_mphy_power_on(hba, true); if (err) @@ -1284,7 +1304,7 @@ int ufs_mtk_system_suspend(struct device *dev) if (ret) return ret; =20 - ufs_mtk_vreg_set_lpm(hba, true); + ufs_mtk_dev_vreg_set_lpm(hba, true); =20 return 0; } @@ -1293,7 +1313,7 @@ int ufs_mtk_system_resume(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); =20 - ufs_mtk_vreg_set_lpm(hba, false); + ufs_mtk_dev_vreg_set_lpm(hba, false); =20 return ufshcd_system_resume(dev); } @@ -1307,7 +1327,7 @@ int ufs_mtk_runtime_suspend(struct device *dev) if (ret) return ret; =20 - ufs_mtk_vreg_set_lpm(hba, true); + ufs_mtk_dev_vreg_set_lpm(hba, true); =20 return 0; } @@ -1316,7 +1336,7 @@ int ufs_mtk_runtime_resume(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); =20 - ufs_mtk_vreg_set_lpm(hba, false); + ufs_mtk_dev_vreg_set_lpm(hba, false); =20 return ufshcd_runtime_resume(dev); } diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index bf6ca96cafb6..5c6101ac518f 100755 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -83,6 +83,7 @@ enum { #define UFS_MTK_SIP_DEVICE_RESET BIT(1) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) +#define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7) =20 /* * VS_DEBUGCLOCKENABLE @@ -182,4 +183,7 @@ static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_reset_ctrl(high, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high) =20 +#define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \ + ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver) + #endif /* !_UFS_MEDIATEK_H */ --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD1BC433EF for ; Wed, 15 Jun 2022 03:52:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352859AbiFODwr (ORCPT ); Tue, 14 Jun 2022 23:52:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244658AbiFODv7 (ORCPT ); Tue, 14 Jun 2022 23:51:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 010065006D; Tue, 14 Jun 2022 20:51:55 -0700 (PDT) X-UUID: e0973e7c3c5047c6b21b980d395990f9-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:301d5296-3dbb-442a-b87d-d1ab1c74e7c0,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:cd3b42f6-e099-41ba-a32c-13b8bfe63214,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: e0973e7c3c5047c6b21b980d395990f9-20220615 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1242386970; Wed, 15 Jun 2022 11:51:50 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:48 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 09/10] scsi: ufs: Export regulator functions Date: Wed, 15 Jun 2022 11:51:45 +0800 Message-ID: <20220615035146.20964-10-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Export below regulator functions to allow vendors to customize regulator configuration in their own platforms. int ufshcd_populate_vreg(struct device *dev, const char *name, struct ufs_vreg **out_vreg); int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); Signed-off-by: Stanley Chu --- drivers/ufs/core/ufshcd.c | 3 ++- drivers/ufs/host/ufshcd-pltfrm.c | 5 +++-- drivers/ufs/host/ufshcd-pltfrm.h | 2 ++ include/ufs/ufshcd.h | 2 ++ 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 0d16739c67bb..8131a75e41e5 100755 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8408,7 +8408,7 @@ static int ufshcd_setup_hba_vreg(struct ufs_hba *hba,= bool on) return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); } =20 -static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) +int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) { int ret =3D 0; =20 @@ -8424,6 +8424,7 @@ static int ufshcd_get_vreg(struct device *dev, struct= ufs_vreg *vreg) out: return ret; } +EXPORT_SYMBOL_GPL(ufshcd_get_vreg); =20 static int ufshcd_init_vreg(struct ufs_hba *hba) { diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-plt= frm.c index e7332cc65b1f..2dd9c660531b 100755 --- a/drivers/ufs/host/ufshcd-pltfrm.c +++ b/drivers/ufs/host/ufshcd-pltfrm.c @@ -109,8 +109,8 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba) } =20 #define MAX_PROP_SIZE 32 -static int ufshcd_populate_vreg(struct device *dev, const char *name, - struct ufs_vreg **out_vreg) +int ufshcd_populate_vreg(struct device *dev, const char *name, + struct ufs_vreg **out_vreg) { char prop_name[MAX_PROP_SIZE]; struct ufs_vreg *vreg =3D NULL; @@ -145,6 +145,7 @@ static int ufshcd_populate_vreg(struct device *dev, con= st char *name, *out_vreg =3D vreg; return 0; } +EXPORT_SYMBOL_GPL(ufshcd_populate_vreg); =20 /** * ufshcd_parse_regulator_info - get regulator info from device tree diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-plt= frm.h index 43c2e412bd99..5130c9471dc2 100755 --- a/drivers/ufs/host/ufshcd-pltfrm.h +++ b/drivers/ufs/host/ufshcd-pltfrm.h @@ -32,5 +32,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev= _param); int ufshcd_pltfrm_init(struct platform_device *pdev, const struct ufs_hba_variant_ops *vops); void ufshcd_pltfrm_shutdown(struct platform_device *pdev); +int ufshcd_populate_vreg(struct device *dev, const char *name, + struct ufs_vreg **out_vreg); =20 #endif /* UFSHCD_PLTFRM_H_ */ diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index aa778418703f..18eb253cfd91 100755 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1187,6 +1187,8 @@ void ufshcd_map_desc_id_to_length(struct ufs_hba *hba= , enum desc_idn desc_id, =20 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); =20 +int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); + int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); =20 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, --=20 2.18.0 From nobody Mon Apr 27 08:41:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36A0CCCA473 for ; Wed, 15 Jun 2022 03:52:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352644AbiFODwi (ORCPT ); Tue, 14 Jun 2022 23:52:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346111AbiFODwB (ORCPT ); Tue, 14 Jun 2022 23:52:01 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78B985002E; Tue, 14 Jun 2022 20:51:58 -0700 (PDT) X-UUID: 823a7cd24eba443c81cc0c95e053d7bc-20220615 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:62344b9c-a37d-44fb-ae46-6e79443d713e,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.6,REQID:62344b9c-a37d-44fb-ae46-6e79443d713e,OB:0,LOB: 0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:b14ad71,CLOUDID:09998548-4c92-421c-ad91-b806c0f58b2a,C OID:0863c9100277,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 823a7cd24eba443c81cc0c95e053d7bc-20220615 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2136744953; Wed, 15 Jun 2022 11:51:50 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 15 Jun 2022 11:51:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jun 2022 11:51:48 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v4 10/10] scsi: ufs-mediatek: Support multiple VCC sources Date: Wed, 15 Jun 2022 11:51:46 +0800 Message-ID: <20220615035146.20964-11-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220615035146.20964-1-stanley.chu@mediatek.com> References: <20220615035146.20964-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support multiple VCC source in MediaTek UFS platforms. Two options are provided and distinguished by specific device tree attributes as below examples, [Option 1: By numbering] mediatek,ufs-vcc-by-num; vcc-opt1-supply =3D <&mt6373_vbuck4_ufs>; vcc-opt2-supply =3D <&mt6363_vemc>; [Option 2: By UFS version] mediatek,ufs-vcc-by-ver; vcc-ufs3-supply =3D <&mt6373_vbuck4_ufs>; Signed-off-by: Alice Chao Signed-off-by: Peter Wang Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 46 +++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-mediatek.h | 14 ++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index e756aba45acd..df6f77aacdc3 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -669,6 +669,50 @@ static u32 ufs_mtk_get_ufs_hci_version(struct ufs_hba = *hba) return hba->ufs_version; } =20 +#define MAX_VCC_NAME 30 +static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba) +{ + struct ufs_vreg_info *info =3D &hba->vreg_info; + struct device_node *np =3D hba->dev->of_node; + struct device *dev =3D hba->dev; + char vcc_name[MAX_VCC_NAME]; + struct arm_smccc_res res; + int err =3D 0; + int ver; + + if (hba->vreg_info.vcc) + return 0; + + if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) { + ufs_mtk_get_vcc_num(res); + if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX) + snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%u", res.a1); + else + return -ENODEV; + } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) { + ver =3D (hba->dev_info.wspecversion & 0xF00) >> 8; + snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver); + } else { + return 0; + } + + err =3D ufshcd_populate_vreg(dev, vcc_name, &info->vcc); + if (err) + return err; + + err =3D ufshcd_get_vreg(dev, info->vcc); + if (err) + return err; + + err =3D regulator_enable(info->vcc->reg); + if (!err) { + info->vcc->enabled =3D true; + dev_info(dev, "%s: %s enabled\n", __func__, vcc_name); + } + + return err; +} + /** * ufs_mtk_init - find other essential mmio bases * @hba: host controller instance @@ -1180,6 +1224,8 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *h= ba) ufs_mtk_setup_ref_clk_wait_us(hba, REFCLK_DEFAULT_WAIT_US); =20 + ufs_mtk_vreg_fix_vcc(hba); + return 0; } =20 diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 5c6101ac518f..49a2137fb251 100755 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -83,6 +83,7 @@ enum { #define UFS_MTK_SIP_DEVICE_RESET BIT(1) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) +#define UFS_MTK_SIP_GET_VCC_NUM BIT(6) #define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7) =20 /* @@ -144,6 +145,16 @@ struct ufs_mtk_host { u32 ip_ver; }; =20 +/* + * Multi-VCC by Numbering + */ +enum ufs_mtk_vcc_num { + UFS_VCC_NONE =3D 0, + UFS_VCC_1, + UFS_VCC_2, + UFS_VCC_MAX +}; + /* * SMC call wrapper function */ @@ -183,6 +194,9 @@ static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_reset_ctrl(high, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high) =20 +#define ufs_mtk_get_vcc_num(res) \ + ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res)) + #define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver) =20 --=20 2.18.0