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Tue, 14 Jun 2022 10:27:14 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim X-Priority: 3 X-Content-Kind-Code: NORMAL In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220614012713epcms2p810386a5137fbcf6aefc41fe086badc0b@epcms2p8> Date: Tue, 14 Jun 2022 10:27:13 +0900 X-CMS-MailID: 20220614012713epcms2p810386a5137fbcf6aefc41fe086badc0b Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; 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ARTPEC-8 is the SoC platform of Axis Communications and PCIe controller is designed based on Design-Ware PCIe controller. Signed-off-by: Wangseok Lee --- v2->v3 : - modify version history to fit the linux commit rule - remove 'Device Tree Bindings' on title - remove the interrupt-names, phy-names entries - remove '_clk' suffix - add the compatible entries on required - change node name to soc from artpec8 on examples v1->v2 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries --- .../bindings/pci/axis,artpec8-pcie-ep.yaml | 109 +++++++++++++++++= ++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 120 +++++++++++++++++= ++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie= -ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie= .yaml diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yam= l b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml new file mode 100644 index 0000000..d802bba --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson + +description: |+ + This PCIe end-point controller is based on the Synopsys DesignWare PCIe = IP + and thus inherits all the common properties defined in snps,dw-pcie-ep.y= aml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: axis,artpec8-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI2) registers. + - description: PCIe address space region. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: addr_space + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + phys: + maxItems: 1 + + num-lanes: + const: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - num-lanes + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie_ep: pcie-ep@17200000 { + compatible =3D "axis,artpec8-pcie-ep"; + reg =3D <0x0 0x17200000 0x0 0x1000>, + <0x0 0x17201000 0x0 0x1000>, + <0x2 0x00000000 0x6 0x00000000>; + reg-names =3D "dbi", "dbi2", "addr_space"; + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-names =3D "intr"; + clocks =3D <&clock_cmu_fsys 39>, + <&clock_cmu_fsys 38>, + <&clock_cmu_fsys 37>, + <&clock_cmu_fsys 36>; + clock-names =3D "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg =3D <&syscon_fsys>; + samsung,syscon-phandle =3D <&pmu_system_controller>; + samsung,syscon-bus-s-fsys =3D <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys =3D <&syscon_bus_p_fsys>; + phys =3D <&pcie_phy>; + phy-names =3D "pcie_phy"; + num-lanes =3D <2>; + bus-range =3D <0x00 0xff>; + num-ib-windows =3D <16>; + num-ob-windows =3D <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b= /Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml new file mode 100644 index 0000000..dbbe1fd --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Artpec-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson + +description: |+ + This PCIe host controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: axis,artpec8-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + ranges: + maxItems: 2 + + num-lanes: + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + phys: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - device_type + - ranges + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie: pcie@17200000 { + compatible =3D "axis,artpec8-pcie"; + reg =3D <0x0 0x17200000 0x0 0x1000>, + <0x0 0x16ca0000 0x0 0x2000>, + <0x7 0x0001e000 0x0 0x2000>; + reg-names =3D "dbi", "elbi", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges =3D ; + num-lanes =3D <2>; + bus-range =3D <0x00 0xff>; + interrupts =3D ; + interrupt-names =3D "intr"; + #interrupt-cells =3D <1>; + clocks =3D <&cmu_fsys 39>, + <&cmu_fsys 38>, + <&cmu_fsys 37>, + <&cmu_fsys 36>; + clock-names =3D "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg =3D <&syscon_fsys>; + samsung,syscon-phandle =3D <&pmu_system_controller>; + samsung,syscon-bus-s-fsys =3D <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys =3D <&syscon_bus_p_fsys>; + phys =3D <&pcie_phy>; + phy-names =3D "pcie_phy"; + }; + }; +... --=20 2.9.5 From nobody Mon Apr 27 11:49:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF53AC43334 for ; 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d=samsung.com; s=mail20170921; t=1655170158; bh=09bej0yfRoQFZyioMYdykSTk5UJaGQ7QfX7QtDcHlkk=; h=Subject:Reply-To:From:To:CC:In-Reply-To:Date:References:From; b=Ho+obmDvuNH12LJzeUU7ToK0AZF0p27Qe5bUwnEZkJkVBsbrLvBcc3/hF4GnoiPad nke9zJOhIt3SjwCbyAUX2XXVs58chcvPdfCTFfFOJb+Q+iTxV0/d7zfbBA+9yaI8UR sUUJKj5YRjbx+RD9kWnwu1u0L6cUu0CoiNcUo7D8= Received: from epsnrtp4.localdomain (unknown [182.195.42.165]) by epcas2p2.samsung.com (KnoxPortal) with ESMTP id 20220614012917epcas2p215740c411f8508dec7d56477839e97b6~4WH0lMH4C0253902539epcas2p22; Tue, 14 Jun 2022 01:29:17 +0000 (GMT) Received: from epsmges2p4.samsung.com (unknown [182.195.36.101]) by epsnrtp4.localdomain (Postfix) with ESMTP id 4LMW7K0F9Rz4x9Q1; Tue, 14 Jun 2022 01:29:17 +0000 (GMT) X-AuditID: b6c32a48-495ff700000025de-c4-62a7e46cf5f7 Received: from epcas2p3.samsung.com ( [182.195.41.55]) by epsmges2p4.samsung.com (Symantec Messaging Gateway) with SMTP id 36.6C.09694.C64E7A26; Tue, 14 Jun 2022 10:29:16 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim X-Priority: 3 X-Content-Kind-Code: NORMAL In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220614012916epcms2p5cf8d55e7420dea10bb4a05d91aaf99dd@epcms2p5> Date: Tue, 14 Jun 2022 10:29:16 +0900 X-CMS-MailID: 20220614012916epcms2p5cf8d55e7420dea10bb4a05d91aaf99dd Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; 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ARTPEC-8 is the SoC platform of Axis Communications and PCIe phy is designed based on SAMSUNG PHY. Signed-off-by: Wangseok Lee --- v2->v3 : -modify version history to fit the linux commit rule -remove 'Device Tree Bindings' on title -remove clock-names entries -change node name to soc from artpec8 on excamples v1->v2 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries --- .../bindings/phy/axis,artpec8-pcie-phy.yaml | 73 ++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie= -phy.yaml diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.ya= ml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml new file mode 100644 index 0000000..316b774 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe PHY + +maintainers: + - Jesper Nilsson + +properties: + compatible: + const: axis,artpec8-pcie-phy + + reg: + items: + - description: PHY registers. + - description: PHY coding sublayer registers. + + reg-names: + items: + - const: phy + - const: pcs + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PCIe PHY reference clock + + num-lanes: + const: 2 + + lcpll-ref-clk: + const: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - samsung,fsys-sysreg + - num-lanes + - lcpll-ref-clk + +additionalProperties: true + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie_phy: pcie-phy@16c80000 { + compatible =3D "axis,artpec8-pcie-phy"; + reg =3D <0x0 0x16c80000 0x0 0x2000>, + <0x0 0x16c90000 0x0 0x1000>; + reg-names =3D "phy", "pcs"; + #phy-cells =3D <0>; + clocks =3D <&clock_cmu_fsys 53>; + clock-names =3D "ref"; + samsung,fsys-sysreg =3D <&syscon_fsys>; + num-lanes =3D <2>; + lcpll-ref-clk =3D <1>; + }; + }; +... --=20 2.9.5 From nobody Mon Apr 27 11:49:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 327C2CCA47B for ; Tue, 14 Jun 2022 01:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240436AbiFNBaz (ORCPT ); Mon, 13 Jun 2022 21:30:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230099AbiFNBaw (ORCPT ); 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Tue, 14 Jun 2022 01:30:44 +0000 (GMT) Received: from epsmges2p1.samsung.com (unknown [182.195.36.70]) by epsnrtp2.localdomain (Postfix) with ESMTP id 4LMW8z4Bk9z4x9QD; Tue, 14 Jun 2022 01:30:43 +0000 (GMT) X-AuditID: b6c32a45-a79ff70000002755-66-62a7e4c28b86 Received: from epcas2p3.samsung.com ( [182.195.41.55]) by epsmges2p1.samsung.com (Symantec Messaging Gateway) with SMTP id 35.BC.10069.2C4E7A26; Tue, 14 Jun 2022 10:30:42 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim X-Priority: 3 X-Content-Kind-Code: NORMAL In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220614013042epcms2p36f88b7eb7f879fefb2f3fbd4548ad705@epcms2p3> Date: Tue, 14 Jun 2022 10:30:42 +0900 X-CMS-MailID: 20220614013042epcms2p36f88b7eb7f879fefb2f3fbd4548ad705 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL X-CPGSPASS: Y X-CPGSPASS: Y CMS-TYPE: 102P X-Brightmail-Tracker: H4sIAAAAAAAAA12Te0xTZxjG8/X0ciApO9zGlzqBHYYBMmjLgH4aYWQy0pQxuszEhAXwCCeU UNqup3VuZIMwEWTqEDTTzkEXDJcKgt2UAhsNpYITRZhOQJi7WCIuJUyIS7cOtpYWXfbfL0/e 93nf57vgWMgPXAFeptLRWhWlJLmB7Cuj8ZJEm6PjgMjZHI/O1yjQI1s8arVPctDQmQ4WOnv6 BoYe2gwYWj0ci6YWj3HRI8N9Lqo+5uYgu/MxhqzjXSx0e/AcF91sGeeiRtMfbOR0L/HQZFsZ qv3WzkMDC9cw9Nflv1mZYdLulm4gnbkolxrNeqnZdJQrddz5jCX96nyV9MTXJiAdn+1nSdfM kfKA/PLdCpoqobXRtKpYXVKmKk0nc94u2lOUmiYSJ4p3IgkZraIq6HQy6w15YnaZ0hOKjD5I KfUeSU4xDCnM2K1V63V0tELN6NJJWlOi1Eg0SQxVwehVpUkqWrdLLBIlp3oK95creuwDHE3n dXBo1W3lVYPvOkEDCMAhkQJ/a6rDGkAgHkJYAHQtHGY3ABznE8Fw3RLqrQklsqHTOcbzcghB Qkt3C+bThXCm8xOOl7lEItxoe8T1chixxoEz3wR7PTHCCKDVPewfxodn6hbZPt4G+zsub+oB xJvwy6tNLJ8eB13txzEfh8O5C8u8LV4Za/X7hMHa+zf9NcHw5z+H/LoAGh02jo8roXXd7fes BvDTn2hvLuhZ2jLzilfmE7nQ3ePaLGETsfBE46p/tSw455rdtMGIKNi/fA7ztmJEPOwdFPpc YqD9HnsrVPUlN+//jBFBsH50/aluaXH4l9kBW7oGsEYQY3h2zob/zDI8m2UEmAk8T2uYilKa SdaIn15usbrCDDbfd8LrFtC8/HuSDbBwYAMQx8gwfvN0+4EQfgn1/ge0Vl2k1StpxgZSPSlP YoLwYrXng6h0ReKUnaKUtDSxJDlVJCEj+LKSPiqEKKV0dDlNa2jtVh8LDxBUsyaHcX3ODvRO 2ROBPfYJhb1WOWQcF17NcCWuZlXGrtbszXg3YmJfXkLTY4E9RVZxaB+zh3skbmIlip3zYKiw p/CW0fbRlUz79sXC+iPmU7crhTV9VW2m0VlXzMW1ETDxQlFBRNQvXVPkfPal5UjHwTEoN9S/ Bz/PXcorSDj567a4VpVT6fyw4UfZ6RH+sGww/vrd2uICmWZhYuljM2e+6mHCS/jcfAcRmA2C iiPF+Rcqd30fBHLGeJmmidAuq0ku7A3eP33r5X/Otk8dP7qhGH7r7sYXe59byS1dEr04InP3 Gm7kOaa7ayT59+6g8O2vUlqhLJus62M6kppV1x4UWEk2o6DECZiWof4FDeppsGgEAAA= DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7 References: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications. This is based on arm64 and support GEN4 & 2lane. This PCIe controller is based on DesignWare Hardware core and uses DesignWa re core functions to implement the driver. "pcie-artpec6. c" supports artpec6 and artpec7 H/W. artpec8 can not be expanded because H/W configuration is completely differe nt from artpec6/7. phy and sub controller are different. Signed-off-by: Wangseok Lee Signed-off-by: Jaeho Cho --- v2->v3 : -add 'COMPILE_TEST' and improvement help on kconfig -reorder obj on makefile -use clk_bulk_api -remove unnecessary comment -redefine the ELBI register to distinguish between offset and bit definition -improvement order local variable of function -remove unnecessary local return variable v1->v2 : improvement review comment of Krzysztof on driver code. -debug messages for probe or other functions. -Inconsistent coding style (different indentation in structure members). -Inconsistent code (artpec8_pcie_get_subsystem_resources() gets device from pdev and from pci so you have two same pointers; or artpec8_pcie_get_ep_mem_resources() stores dev as local variable but uses instead pdev->dev). -Not using devm_platform_ioremap_resource(). -Printing messages in interrupt handlers. -Several local/static structures or array are not const. --- drivers/pci/controller/dwc/Kconfig | 31 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec8.c | 797 ++++++++++++++++++++++++++= ++++ 3 files changed, 829 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-artpec8.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index 62ce3ab..2b16637 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -222,6 +222,37 @@ config PCIE_ARTPEC6_EP Enables support for the PCIe controller in the ARTPEC-6 SoC to work in endpoint mode. This uses the DesignWare core. =20 +config PCIE_ARTPEC8 + bool "Axis ARTPEC-8 PCIe controller" + +config PCIE_ARTPEC8_HOST + bool "Axis ARTPEC-8 PCIe controller Host Mode" + depends on ARCH_ARTPEC || COMPILE_TEST + depends on PCI_MSI_IRQ_DOMAIN + depends on PCI_ENDPOINT + select PCI_EPF_TEST + select PCIE_DW_HOST + select PCIE_ARTPEC8 + help + Say 'Y' here to enable support for the PCIe controller in the + ARTPEC-8 SoC to work in host mode. + This PCIe controller is based on DesignWare hardware core and + uses DesignWare core functions to implement the driver. + +config PCIE_ARTPEC8_EP + bool "Axis ARTPEC-8 PCIe controller Endpoint Mode" + depends on ARCH_ARTPEC || COMPILE_TEST + depends on PCI_ENDPOINT + depends on PCI_ENDPOINT_CONFIGFS + select PCI_EPF_TEST + select PCIE_DW_EP + select PCIE_ARTPEC8 + help + Say 'Y' here to enable support for the PCIe controller in the + ARTPEC-8 SoC to work in endpoint mode. + This PCIe controller is based on DesignWare hardware core and + uses DesignWare core functions to implement the driver. + config PCIE_ROCKCHIP_DW_HOST bool "Rockchip DesignWare PCIe controller" select PCIE_DW diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 8ba7b67..95f5877 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PCIE_QCOM) +=3D pcie-qcom.o obj-$(CONFIG_PCIE_QCOM_EP) +=3D pcie-qcom-ep.o obj-$(CONFIG_PCIE_ARMADA_8K) +=3D pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) +=3D pcie-artpec6.o +obj-$(CONFIG_PCIE_ARTPEC8) +=3D pcie-artpec8.o obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) +=3D pcie-dw-rockchip.o obj-$(CONFIG_PCIE_INTEL_GW) +=3D pcie-intel-gw.o obj-$(CONFIG_PCIE_KEEMBAY) +=3D pcie-keembay.o diff --git a/drivers/pci/controller/dwc/pcie-artpec8.c b/drivers/pci/contro= ller/dwc/pcie-artpec8.c new file mode 100644 index 0000000..996fcfc --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-artpec8.c @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe controller driver for Axis ARTPEC-8 SoC + * + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Jaeho Cho + * This file is based on driver/pci/controller/dwc/pci-exynos.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_artpec8_pcie(x) dev_get_drvdata((x)->dev) + +/* Gen3 Control Register */ +#define PCIE_GEN3_RELATED_OFF 0x890 +#define PCIE_GEN3_EQUALIZATION_DISABLE (0x1 << 16) +#define PCIE_GEN3_EQ_PHASE_2_3 (0x1 << 9) +#define PCIE_GEN3_RXEQ_PH01_EN (0x1 << 12) +#define PCIE_GEN3_RXEQ_RGRDLESS_RXTS (0x1 << 13) + +#define FAST_LINK_MODE (7) + +/* PCIe ELBI registers */ +#define PCIE_IRQ0_STS 0x000 +#define PCIE_IRQ1_STS 0x004 +#define PCIE_IRQ2_STS 0x008 +#define IRQ2_STS_IRQ_MSI_ST BIT(20) +#define PCIE_IRQ5_STS 0x00C +#define PCIE_IRQ0_EN 0x010 +#define PCIE_IRQ1_EN 0x014 +#define PCIE_IRQ2_EN 0x018 +#define IRQ2_EN_IRQ_MSI BIT(20) +#define PCIE_IRQ5_EN 0x01C +#define PCIE_APP_LTSSM_ENABLE 0x054 +#define APP_LTSSM_ENABLE_EN_BIT BIT(0) +#define PCIE_ELBI_CXPL_DEBUG_00_31 0x2C8 +#define PCIE_ELBI_CXPL_DEBUG_32_63 0x2CC +#define PCIE_ARTPEC8_DEVICE_TYPE 0x080 +#define DEVICE_TYPE_EP 0x0 +#define DEVICE_TYPE_LEG_EP BIT(0) +#define DEVICE_TYPE_RC BIT(2) +#define LTSSM_STATE_MASK 0x3F +#define LTSSM_STATE_L0 0x11 + +/* FSYS glue logic system registers */ +#define FSYS_PCIE_CON 0x424 +#define PCIE_PERSTN BIT(5) +#define FSYS_PCIE_DBI_ADDR_CON 0x428 +#define FSYS_PCIE_DBI_ADDR_OVR_CDM 0x00 +#define FSYS_PCIE_DBI_ADDR_OVR_SHADOW 0x12 +#define FSYS_PCIE_DBI_ADDR_OVR_ATU 0x36 + +/* PMU SYSCON Offsets */ +#define PMU_SYSCON_PCIE_ISOLATION 0x3200 + +/* BUS P/S SYSCON Offsets */ +#define BUS_SYSCON_BUS_PATH_ENABLE 0x0 + +struct artpec8_pcie { + struct dw_pcie *pci; + const struct artpec8_pcie_pdata *pdata; + void __iomem *elbi_base; + struct regmap *sysreg; + struct regmap *pmu_syscon; + struct regmap *bus_s_syscon; + struct regmap *bus_p_syscon; + enum dw_pcie_device_mode mode; + int link_id; + struct phy *phy; +}; + +struct artpec8_pcie_res_ops { + int (*get_mem_resources)(struct platform_device *pdev, + struct artpec8_pcie *artpec8_ctrl); + int (*get_clk_resources)(struct platform_device *pdev); + int (*init_clk_resources)(void); + void (*deinit_clk_resources)(void); +}; + +struct artpec8_pcie_pdata { + const struct dw_pcie_ops *dwc_ops; + const struct dw_pcie_host_ops *host_ops; + const struct artpec8_pcie_res_ops *res_ops; + enum dw_pcie_device_mode mode; +}; + +enum artpec8_pcie_isolation { + PCIE_CLEAR_ISOLATION =3D 0, + PCIE_SET_ISOLATION =3D 1 +}; + +enum artpec8_pcie_reg_bit { + PCIE_REG_BIT_LOW =3D 0, + PCIE_REG_BIT_HIGH =3D 1 +}; + +static const int artpec8_pcie_dbi_addr_con[] =3D { + FSYS_PCIE_DBI_ADDR_CON +}; + +static struct clk_bulk_data artpec8_pcie_clks[] =3D { + { .id =3D "pipe" }, + { .id =3D "dbi" }, + { .id =3D "mstr" }, + { .id =3D "slv" }, +}; + +static u32 artpec8_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + u32 val; + bool is_atu =3D false; + + if (base =3D=3D pci->atu_base) { + is_atu =3D true; + base =3D pci->dbi_base; + regmap_write(artpec8_ctrl->sysreg, + artpec8_pcie_dbi_addr_con[artpec8_ctrl->link_id], + FSYS_PCIE_DBI_ADDR_OVR_ATU); + } + + dw_pcie_read(base + reg, size, &val); + + if (is_atu) + regmap_write(artpec8_ctrl->sysreg, + artpec8_pcie_dbi_addr_con[artpec8_ctrl->link_id], + FSYS_PCIE_DBI_ADDR_OVR_CDM); + + return val; +} + +static void artpec8_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + bool is_atu =3D false; + + if (base =3D=3D pci->atu_base) { + is_atu =3D true; + base =3D pci->dbi_base; + regmap_write(artpec8_ctrl->sysreg, + artpec8_pcie_dbi_addr_con[artpec8_ctrl->link_id], + FSYS_PCIE_DBI_ADDR_OVR_ATU); + } + + dw_pcie_write(base + reg, size, val); + + if (is_atu) + regmap_write(artpec8_ctrl->sysreg, + artpec8_pcie_dbi_addr_con[artpec8_ctrl->link_id], + FSYS_PCIE_DBI_ADDR_OVR_CDM); +} + +static void artpec8_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *bas= e, + u32 reg, size_t size, u32 val) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + + regmap_write(artpec8_ctrl->sysreg, + artpec8_pcie_dbi_addr_con[artpec8_ctrl->link_id], + FSYS_PCIE_DBI_ADDR_OVR_SHADOW); + + dw_pcie_write(base + reg, size, val); + + regmap_write(artpec8_ctrl->sysreg, + artpec8_pcie_dbi_addr_con[artpec8_ctrl->link_id], + FSYS_PCIE_DBI_ADDR_OVR_CDM); +} + +static int artpec8_pcie_get_subsystem_resources(struct platform_device *pd= ev, + struct artpec8_pcie *artpec8_ctrl) +{ + struct device *dev =3D &pdev->dev; + + /* External Local Bus interface(ELBI) Register */ + artpec8_ctrl->elbi_base =3D + devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(artpec8_ctrl->elbi_base)) { + dev_err(dev, "failed to map elbi_base\n"); + return PTR_ERR(artpec8_ctrl->elbi_base); + } + + artpec8_ctrl->sysreg =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,fsys-sysreg"); + if (IS_ERR(artpec8_ctrl->sysreg)) { + dev_err(dev, "fsys sysreg regmap lookup failed.\n"); + return PTR_ERR(artpec8_ctrl->sysreg); + } + + artpec8_ctrl->pmu_syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,syscon-phandle"); + if (IS_ERR(artpec8_ctrl->pmu_syscon)) { + dev_err(dev, "pmu syscon regmap lookup failed.\n"); + return PTR_ERR(artpec8_ctrl->pmu_syscon); + } + + artpec8_ctrl->bus_s_syscon =3D + syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,syscon-bus-s-fsys"); + if (IS_ERR(artpec8_ctrl->bus_s_syscon)) { + dev_err(dev, "bus_s_syscon regmap lookup failed.\n"); + return PTR_ERR(artpec8_ctrl->bus_s_syscon); + } + + artpec8_ctrl->bus_p_syscon =3D + syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,syscon-bus-p-fsys"); + if (IS_ERR(artpec8_ctrl->bus_p_syscon)) { + dev_err(dev, "bus_p_syscon regmap lookup failed.\n"); + return PTR_ERR(artpec8_ctrl->bus_p_syscon); + } + + return 0; +} + +static int artpec8_pcie_get_rc_mem_resources(struct platform_device *pdev, + struct artpec8_pcie *artpec8_ctrl) +{ + struct dw_pcie *pci =3D artpec8_ctrl->pci; + + /* Data Bus Interface(DBI) Register */ + pci->dbi_base =3D devm_platform_ioremap_resource_byname(pdev, "dbi"); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + return 0; +} + +static int artpec8_pcie_get_ep_mem_resources(struct platform_device *pdev, + struct artpec8_pcie *artpec8_ctrl) +{ + struct dw_pcie *pci =3D artpec8_ctrl->pci; + struct device *dev =3D &pdev->dev; + struct dw_pcie_ep *ep =3D &pci->ep; + struct resource *res; + + pci->dbi_base =3D devm_platform_ioremap_resource_byname(pdev, "dbi"); + if (IS_ERR(pci->dbi_base)) { + dev_err(dev, "failed to map ep_dbics\n"); + return -ENOMEM; + } + + pci->dbi_base2 =3D devm_platform_ioremap_resource_byname(pdev, "dbi2"); + if (IS_ERR(pci->dbi_base2)) { + dev_err(dev, "failed to map ep_dbics2\n"); + return -ENOMEM; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + ep->phys_base =3D res->start; + ep->addr_size =3D resource_size(res); + + return 0; +} + +static int artpec8_pcie_get_clk_resources(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(artpec8_pcie_clks), + artpec8_pcie_clks); + if (ret) + return ret; + + return 0; +} + +static int artpec8_pcie_init_clk_resources(void) +{ + int ret; + + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(artpec8_pcie_clks), + artpec8_pcie_clks); + if (ret) + return ret; + + return 0; +} + +static void artpec8_pcie_deinit_clk_resources(void) +{ + clk_bulk_disable_unprepare(ARRAY_SIZE(artpec8_pcie_clks), + artpec8_pcie_clks); +} + +static const struct artpec8_pcie_res_ops artpec8_pcie_rc_res_ops =3D { + .get_mem_resources =3D artpec8_pcie_get_rc_mem_resources, + .get_clk_resources =3D artpec8_pcie_get_clk_resources, + .init_clk_resources =3D artpec8_pcie_init_clk_resources, + .deinit_clk_resources =3D artpec8_pcie_deinit_clk_resources, +}; + +static const struct artpec8_pcie_res_ops artpec8_pcie_ep_res_ops =3D { + .get_mem_resources =3D artpec8_pcie_get_ep_mem_resources, + .get_clk_resources =3D artpec8_pcie_get_clk_resources, + .init_clk_resources =3D artpec8_pcie_init_clk_resources, + .deinit_clk_resources =3D artpec8_pcie_deinit_clk_resources, +}; + +static int artpec8_pcie_config_phy_power_isolation(struct dw_pcie *pci, + enum artpec8_pcie_reg_bit val) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + + return regmap_write(artpec8_ctrl->pmu_syscon, PMU_SYSCON_PCIE_ISOLATION, + val); + +} + +static int artpec8_pcie_config_bus_enable(struct dw_pcie *pci, + enum artpec8_pcie_reg_bit val) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + int ret; + + ret =3D regmap_write(artpec8_ctrl->bus_p_syscon, + BUS_SYSCON_BUS_PATH_ENABLE, val); + if (ret) + return ret; + + return regmap_write(artpec8_ctrl->bus_s_syscon, + BUS_SYSCON_BUS_PATH_ENABLE, val); +} + +static int artpec8_pcie_config_isolation(struct dw_pcie *pci, + enum artpec8_pcie_isolation val) +{ + int ret; + /* reg_val[0] : for phy power isolation */ + /* reg_val[1] : for bus enable */ + enum artpec8_pcie_reg_bit reg_val[2]; + + switch (val) { + case PCIE_CLEAR_ISOLATION: + reg_val[0] =3D PCIE_REG_BIT_LOW; + reg_val[1] =3D PCIE_REG_BIT_HIGH; + break; + case PCIE_SET_ISOLATION: + reg_val[0] =3D PCIE_REG_BIT_HIGH; + reg_val[1] =3D PCIE_REG_BIT_LOW; + break; + default: + return -EINVAL; + } + + ret =3D artpec8_pcie_config_phy_power_isolation(pci, reg_val[0]); + if (ret) + return ret; + + return artpec8_pcie_config_bus_enable(pci, reg_val[1]); +} + +static int artpec8_pcie_config_perstn(struct dw_pcie *pci, + enum artpec8_pcie_reg_bit val) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + unsigned int bits; + + if (val =3D=3D PCIE_REG_BIT_HIGH) + bits =3D PCIE_PERSTN; + else + bits =3D 0; + + return regmap_update_bits(artpec8_ctrl->sysreg, FSYS_PCIE_CON, + PCIE_PERSTN, bits); +} + +static void artpec8_pcie_stop_link(struct dw_pcie *pci) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + u32 val; + + val =3D readl(artpec8_ctrl->elbi_base + PCIE_APP_LTSSM_ENABLE); + + val &=3D ~APP_LTSSM_ENABLE_EN_BIT; + writel(val, artpec8_ctrl->elbi_base + PCIE_APP_LTSSM_ENABLE); +} + +static int artpec8_pcie_start_link(struct dw_pcie *pci) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + /* Equalization disable */ + val =3D artpec8_pcie_read_dbi(pci, pci->dbi_base, PCIE_GEN3_RELATED_OFF, + 4); + artpec8_pcie_write_dbi(pci, pci->dbi_base, PCIE_GEN3_RELATED_OFF, 4, + val | PCIE_GEN3_EQUALIZATION_DISABLE); + + dw_pcie_dbi_ro_wr_dis(pci); + + /* assert LTSSM enable */ + val =3D readl(artpec8_ctrl->elbi_base + PCIE_APP_LTSSM_ENABLE); + + val |=3D APP_LTSSM_ENABLE_EN_BIT; + writel(val, artpec8_ctrl->elbi_base + PCIE_APP_LTSSM_ENABLE); + + return 0; +} + +static irqreturn_t artpec8_pcie_msi_irq_handler(int irq, void *arg) +{ + struct artpec8_pcie *artpec8_ctrl =3D arg; + struct dw_pcie *pci =3D artpec8_ctrl->pci; + struct pcie_port *pp =3D &pci->pp; + u32 val; + + val =3D readl(artpec8_ctrl->elbi_base + PCIE_IRQ2_STS); + + if ((val & IRQ2_STS_IRQ_MSI_ST) =3D=3D IRQ2_STS_IRQ_MSI_ST) { + val &=3D IRQ2_STS_IRQ_MSI_ST; + writel(val, artpec8_ctrl->elbi_base + PCIE_IRQ2_STS); + dw_handle_msi_irq(pp); + } + + return IRQ_HANDLED; +} + +static void artpec8_pcie_msi_init(struct artpec8_pcie *artpec8_ctrl) +{ + u32 val; + + /* enable MSI interrupt */ + val =3D readl(artpec8_ctrl->elbi_base + PCIE_IRQ2_EN); + val |=3D IRQ2_EN_IRQ_MSI; + writel(val, artpec8_ctrl->elbi_base + PCIE_IRQ2_EN); +} + +static void artpec8_pcie_enable_interrupts(struct artpec8_pcie *artpec8_ct= rl) +{ + if (IS_ENABLED(CONFIG_PCI_MSI)) + artpec8_pcie_msi_init(artpec8_ctrl); +} + +static int artpec8_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devf= n, + int where, int size, u32 *val) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(bus->sysdata); + + if (PCI_SLOT(devfn)) { + PCI_SET_ERROR_RESPONSE(val); + return PCIBIOS_DEVICE_NOT_FOUND; + } + + *val =3D dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; +} + +static int artpec8_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devf= n, + int where, int size, u32 val) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(bus->sysdata); + + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops artpec8_pci_ops =3D { + .read =3D artpec8_pcie_rd_own_conf, + .write =3D artpec8_pcie_wr_own_conf, +}; + +static int artpec8_pcie_link_up(struct dw_pcie *pci) +{ + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + u32 val; + + val =3D readl(artpec8_ctrl->elbi_base + PCIE_ELBI_CXPL_DEBUG_00_31); + + return (val & LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_L0; +} + +static int artpec8_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct artpec8_pcie *artpec8_ctrl =3D to_artpec8_pcie(pci); + + pp->bridge->ops =3D &artpec8_pci_ops; + + dw_pcie_writel_dbi(pci, PCIE_GEN3_RELATED_OFF, + (PCIE_GEN3_EQ_PHASE_2_3 | + PCIE_GEN3_RXEQ_PH01_EN | + PCIE_GEN3_RXEQ_RGRDLESS_RXTS)); + + artpec8_pcie_enable_interrupts(artpec8_ctrl); + + return 0; +} + +static const struct dw_pcie_host_ops artpec8_pcie_host_ops =3D { + .host_init =3D artpec8_pcie_host_init, +}; + +static u8 artpec8_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + u32 val; + + val =3D dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + pci->atu_base =3D pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + + if (val =3D=3D 0xffffffff) + return 1; + + return 0; +} + +static void artpec8_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + enum pci_barno bar; + /* + * Currently PCIe EP core is not setting iatu_unroll_enabled + * so let's handle it here. We need to find proper place to + * initialize this so that it can be used for other EP + * controllers as well. + */ + pci->iatu_unroll_enabled =3D artpec8_pcie_iatu_unroll_enabled(pci); + + for (bar =3D BAR_0; bar <=3D BAR_5; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int artpec8_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, u16 interrupt_num) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return -EINVAL; + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static const struct pci_epc_features artpec8_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, +}; + +static const struct pci_epc_features* +artpec8_pcie_ep_get_features(struct dw_pcie_ep *ep) +{ + return &artpec8_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops artpec8_dw_pcie_ep_ops =3D { + .ep_init =3D artpec8_pcie_ep_init, + .raise_irq =3D artpec8_pcie_raise_irq, + .get_features =3D artpec8_pcie_ep_get_features, +}; + +static int __init artpec8_add_pcie_ep(struct artpec8_pcie *artpec8_ctrl, + struct platform_device *pdev) +{ + struct dw_pcie *pci =3D artpec8_ctrl->pci; + struct dw_pcie_ep *ep =3D &pci->ep; + int ret; + + ep->ops =3D &artpec8_dw_pcie_ep_ops; + + dw_pcie_writel_dbi(pci, PCIE_GEN3_RELATED_OFF, + (PCIE_GEN3_EQ_PHASE_2_3 | + PCIE_GEN3_RXEQ_PH01_EN | + PCIE_GEN3_RXEQ_RGRDLESS_RXTS)); + + ret =3D dw_pcie_ep_init(ep); + if (ret) + return ret; + + return 0; +} + +static int __init artpec8_add_pcie_port(struct artpec8_pcie *artpec8_ctrl, + struct platform_device *pdev) +{ + struct dw_pcie *pci =3D artpec8_ctrl->pci; + struct pcie_port *pp =3D &pci->pp; + struct device *dev =3D &pdev->dev; + int irq; + int irq_flags; + int ret; + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + irq =3D platform_get_irq_byname(pdev, "intr"); + if (!irq) + return -ENODEV; + + irq_flags =3D IRQF_SHARED | IRQF_NO_THREAD; + + ret =3D devm_request_irq(dev, irq, artpec8_pcie_msi_irq_handler, + irq_flags, "artpec8-pcie", artpec8_ctrl); + if (ret) + return ret; + } + + /* Prevent core from messing with the IRQ, since it's muxed */ + pp->msi_irq =3D -ENODEV; + + return dw_pcie_host_init(pp); +} + +static const struct dw_pcie_ops artpec8_dw_pcie_ops =3D { + .read_dbi =3D artpec8_pcie_read_dbi, + .write_dbi =3D artpec8_pcie_write_dbi, + .write_dbi2 =3D artpec8_pcie_write_dbi2, + .start_link =3D artpec8_pcie_start_link, + .stop_link =3D artpec8_pcie_stop_link, + .link_up =3D artpec8_pcie_link_up, +}; + +static int artpec8_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct artpec8_pcie *artpec8_ctrl; + struct dw_pcie *pci; + const struct artpec8_pcie_pdata *pdata; + enum dw_pcie_device_mode mode; + struct pcie_port *pp; + struct device_node *np =3D dev->of_node; + int ret; + + artpec8_ctrl =3D devm_kzalloc(dev, sizeof(*artpec8_ctrl), GFP_KERNEL); + if (!artpec8_ctrl) + return -ENOMEM; + + pci =3D devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pdata =3D of_device_get_match_data(dev); + + if (!pdata) + return -ENODEV; + + mode =3D (enum dw_pcie_device_mode)pdata->mode; + + artpec8_ctrl->pci =3D pci; + artpec8_ctrl->pdata =3D pdata; + artpec8_ctrl->mode =3D mode; + + pci->dev =3D dev; + pci->ops =3D pdata->dwc_ops; + pci->dbi_base2 =3D NULL; + pci->dbi_base =3D NULL; + pp =3D &pci->pp; + pp->ops =3D artpec8_ctrl->pdata->host_ops; + + if (mode =3D=3D DW_PCIE_RC_TYPE) + artpec8_ctrl->link_id =3D of_alias_get_id(np, "pcierc"); + else + artpec8_ctrl->link_id =3D of_alias_get_id(np, "pcieep"); + + ret =3D artpec8_pcie_get_subsystem_resources(pdev, artpec8_ctrl); + if (ret) + return ret; + + if (pdata->res_ops && pdata->res_ops->get_mem_resources) { + ret =3D pdata->res_ops->get_mem_resources(pdev, artpec8_ctrl); + if (ret) + return ret; + } + + if (pdata->res_ops && pdata->res_ops->get_clk_resources) { + ret =3D pdata->res_ops->get_clk_resources(pdev); + if (ret) + return ret; + + ret =3D pdata->res_ops->init_clk_resources(); + if (ret) + return ret; + } + + platform_set_drvdata(pdev, artpec8_ctrl); + + ret =3D artpec8_pcie_config_isolation(pci, PCIE_CLEAR_ISOLATION); + if (ret) + return ret; + + ret =3D artpec8_pcie_config_perstn(pci, PCIE_REG_BIT_HIGH); + if (ret) + return ret; + + artpec8_ctrl->phy =3D devm_of_phy_get(dev, np, NULL); + if (IS_ERR(artpec8_ctrl->phy)) + return PTR_ERR(artpec8_ctrl->phy); + + phy_init(artpec8_ctrl->phy); + phy_reset(artpec8_ctrl->phy); + + switch (mode) { + case DW_PCIE_RC_TYPE: + writel(DEVICE_TYPE_RC, artpec8_ctrl->elbi_base + + PCIE_ARTPEC8_DEVICE_TYPE); + ret =3D artpec8_add_pcie_port(artpec8_ctrl, pdev); + if (ret < 0) + goto fail_probe; + break; + case DW_PCIE_EP_TYPE: + writel(DEVICE_TYPE_EP, artpec8_ctrl->elbi_base + + PCIE_ARTPEC8_DEVICE_TYPE); + + ret =3D artpec8_add_pcie_ep(artpec8_ctrl, pdev); + if (ret < 0) + goto fail_probe; + break; + default: + ret =3D -EINVAL; + goto fail_probe; + } + + return 0; + +fail_probe: + phy_exit(artpec8_ctrl->phy); + if (pdata->res_ops && pdata->res_ops->deinit_clk_resources) + pdata->res_ops->deinit_clk_resources(); + + return ret; +} + +static int __exit artpec8_pcie_remove(struct platform_device *pdev) +{ + struct artpec8_pcie *artpec8_ctrl =3D platform_get_drvdata(pdev); + const struct artpec8_pcie_pdata *pdata =3D artpec8_ctrl->pdata; + + if (pdata->res_ops && pdata->res_ops->deinit_clk_resources) + pdata->res_ops->deinit_clk_resources(); + + return 0; +} + +static const struct artpec8_pcie_pdata artpec8_pcie_rc_pdata =3D { + .dwc_ops =3D &artpec8_dw_pcie_ops, + .host_ops =3D &artpec8_pcie_host_ops, + .res_ops =3D &artpec8_pcie_rc_res_ops, + .mode =3D DW_PCIE_RC_TYPE, +}; + +static const struct artpec8_pcie_pdata artpec8_pcie_ep_pdata =3D { + .dwc_ops =3D &artpec8_dw_pcie_ops, + .host_ops =3D &artpec8_pcie_host_ops, + .res_ops =3D &artpec8_pcie_ep_res_ops, + .mode =3D DW_PCIE_EP_TYPE, +}; + +static const struct of_device_id artpec8_pcie_of_match[] =3D { + { + .compatible =3D "axis,artpec8-pcie", + .data =3D &artpec8_pcie_rc_pdata, + }, + { + .compatible =3D "axis,artpec8-pcie-ep", + .data =3D &artpec8_pcie_ep_pdata, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, artpec8_pcie_of_match); + +static struct platform_driver artpec8_pcie_driver =3D { + .probe =3D artpec8_pcie_probe, + .remove =3D __exit_p(artpec8_pcie_remove), + .driver =3D { + .name =3D "artpec8-pcie", + .of_match_table =3D artpec8_pcie_of_match, + }, +}; + +module_platform_driver(artpec8_pcie_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jaeho Cho "); --=20 2.9.5 From nobody Mon Apr 27 11:49:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD86CCA47B for ; Tue, 14 Jun 2022 01:34:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244438AbiFNBe4 (ORCPT ); Mon, 13 Jun 2022 21:34:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230299AbiFNBew (ORCPT ); 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Tue, 14 Jun 2022 01:34:47 +0000 (GMT) Received: from epsmges2p1.samsung.com (unknown [182.195.36.90]) by epsnrtp2.localdomain (Postfix) with ESMTP id 4LMWFf6Fyxz4x9Q6; Tue, 14 Jun 2022 01:34:46 +0000 (GMT) X-AuditID: b6c32a45-a79ff70000002755-9a-62a7e5b66353 Received: from epcas2p4.samsung.com ( [182.195.41.56]) by epsmges2p1.samsung.com (Symantec Messaging Gateway) with SMTP id 48.30.10069.6B5E7A26; Tue, 14 Jun 2022 10:34:46 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim X-Priority: 3 X-Content-Kind-Code: NORMAL In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220614013446epcms2p8c88ea65da49447f72fef6536c7f73fb6@epcms2p8> Date: Tue, 14 Jun 2022 10:34:46 +0900 X-CMS-MailID: 20220614013446epcms2p8c88ea65da49447f72fef6536c7f73fb6 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL X-CPGSPASS: Y X-CPGSPASS: Y CMS-TYPE: 102P X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCJsWRmVeSWpSXmKPExsWy7bCmhe62p8uTDJ7e0LNY0pRh8fKQpsX8 I+dYLXbPWM5kMXPqGWaL54dmMVt8alG1uPC0h83i5ax7bBYNPb9ZLY68+chssf/4SiaLy7vm sFmcnXeczWLCqm8sFm9+v2C3OLc406J17xF2i513TjBb/Nr6h8lBxGPNvDWMHtfXBXgs2FTq sWlVJ5vHkyvTmTw2L6n36NuyitHj+I3tTB6fN8kFcEZl22SkJqakFimk5iXnp2TmpdsqeQfH O8ebmhkY6hpaWpgrKeQl5qbaKrn4BOi6ZeYAPaWkUJaYUwoUCkgsLlbSt7Mpyi8tSVXIyC8u sVVKLUjJKTAv0CtOzC0uzUvXy0stsTI0MDAyBSpMyM7ov/2creDBGcaKJe9rGhi/rWHsYuTk kBAwkdg98wpbFyMXh5DADkaJZcc2s3cxcnDwCghK/N0hDFIjLGApsf/RO2YQW0hASWLHmnnM EHF9iesrullBbDYBXYl/i1+ygdgiAp9ZJa7vEQSZySywgFFi/+99UMt4JWa0P2WBsKUlti/f ChbnFPCTWHh0EhNEXEPix7JeZghbVOLm6rfsMPb7Y/Oh5ohItN47C1UjKPHg526ouJTEgieH WCHsaon9f39DzWxglOi/nwrylwTQ0TuuG4OEeQV8Ja4cvA02hkVAVeLhzflQrS4S858+Bosz C8hLbH87hxmklVlAU2L9Ln2IKcoSR26xwDzVsPE3OzqbWYBPouPwX7j4jnlPoI5Rk5i3cifz BEblWYhwnoVk1yyEXQsYmVcxiqUWFOempxYbFRjC4zY5P3cTIzh5a7nuYJz89oPeIUYmDsZD jBIczEoivJMvLksS4k1JrKxKLcqPLyrNSS0+xGgK9OVEZinR5Hxg/sgriTc0sTQwMTMzNDcy NTBXEuf1StmQKCSQnliSmp2aWpBaBNPHxMEp1cDUxT1Z4NoWeaNdrV43VnAuKj1a/szkhK3i P4sODUGb243+yTbNL28mT+c4JX5z6wFeD+0FGlMlq/ilC6/01FwsdI5ysZFI/lxTy8bD///o RaPbZyq9OHNSl+U6mKt1q7NeNJSKyct7e8LkxglbNjP9TcFaKbMOHDR5KHh+7azpwU+F2pxM QhZtkG5bnL5s0oQGVe+0I0W71eUatkzf+jcr40LF1HSX1u1OGYv2uB7qVnbe7Pf4qO2mUxk6 MwR8iifyqfW+4VEMcpdc9iX3hH+T4O2aZ08Odnvwn7zVdjm6+s6tZ4v4l4YuNY9YsEv21rRX VuueiYX1LtjCt1Oaz4t//Xazpqsvl2xJn9l9w0KJpTgj0VCLuag4EQAfeYKpZwQAAA== DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7 References: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications. This is based on arm64 and support GEN4 & 2lane. This driver provides PHY interface for ARTPEC-8 SoC PCIe controller, based on Samsung PCIe PHY IP. Signed-off-by: Wangseok Lee Signed-off-by: Jaeho Cho --- v2->v3 : -remove unnecessary indentation -redefine local struct to statis const -add static const to struct that requires static const definition -remove wrappers on writel and readl v1->v2 : -change folder name of phy driver to axis from artpec --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/axis/Kconfig | 9 + drivers/phy/axis/Makefile | 2 + drivers/phy/axis/phy-artpec8-pcie.c | 776 ++++++++++++++++++++++++++++++++= ++++ 5 files changed, 789 insertions(+) create mode 100644 drivers/phy/axis/Kconfig create mode 100644 drivers/phy/axis/Makefile create mode 100644 drivers/phy/axis/phy-artpec8-pcie.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 300b0f2..92b8232 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -73,6 +73,7 @@ config PHY_CAN_TRANSCEIVER =20 source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" +source "drivers/phy/axis/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/freescale/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 01e9eff..808c055e 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) +=3D phy-pistachio-usb.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-y +=3D allwinner/ \ amlogic/ \ + axis/ \ broadcom/ \ cadence/ \ freescale/ \ diff --git a/drivers/phy/axis/Kconfig b/drivers/phy/axis/Kconfig new file mode 100644 index 0000000..7198b93 --- /dev/null +++ b/drivers/phy/axis/Kconfig @@ -0,0 +1,9 @@ +config PHY_ARTPEC8_PCIE + bool "ARTPEC-8 PCIe PHY driver" + depends on OF && (ARCH_ARTPEC8 || COMPILE_TEST) + select GENERIC_PHY + help + Enable PCIe PHY support for ARTPEC-8 SoC. + This driver provides PHY interface for ARTPEC-8 SoC + PCIe controller. + This is based on Samsung PCIe PHY IP. diff --git a/drivers/phy/axis/Makefile b/drivers/phy/axis/Makefile new file mode 100644 index 0000000..45d853c --- /dev/null +++ b/drivers/phy/axis/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_ARTPEC8_PCIE) +=3D phy-artpec8-pcie.o diff --git a/drivers/phy/axis/phy-artpec8-pcie.c b/drivers/phy/axis/phy-art= pec8-pcie.c new file mode 100644 index 0000000..d21867b --- /dev/null +++ b/drivers/phy/axis/phy-artpec8-pcie.c @@ -0,0 +1,776 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PHY provider for ARTPEC-8 PCIe controller + * + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Jaeho Cho + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ARTPEC-8 PCIe PHY registers */ +/* CMN registers */ +#define PCIE_PHY_CMN_REG004 0x10 +#define PCIE_PHY_CMN_REG00B 0x2C +#define PCIE_PHY_CMN_REG016 0x58 +#define PCIE_PHY_CMN_REG01C 0x70 +#define PCIE_PHY_CMN_REG021 0x84 +#define PCIE_PHY_CMN_REG024 0x90 +#define PCIE_PHY_CMN_REG025 0x94 +#define PCIE_PHY_CMN_REG0E6 0x398 +#define PCIE_PHY_CMN_REG0E7 0x39C +#define PCIE_PHY_CMN_REG0E8 0x3A0 +#define PCIE_PHY_CMN_REG0E9 0x3A4 +#define PCIE_PHY_CMN_REG0EA 0x3A8 +#define PCIE_PHY_CMN_REG0EB 0x3AC +#define PCIE_PHY_CMN_REG0EC 0x3B0 +#define PCIE_PHY_CMN_REG0EE 0x3B8 +#define PCIE_PHY_CMN_REG0EF 0x3BC +#define PCIE_PHY_CMN_REG0F1 0x3C4 +#define PCIE_PHY_CMN_REG0F3 0x3CC +#define PCIE_PHY_CMN_REG0F4 0x3D0 + +#define PCIE_PHY_CMN_REG101 0x404 +#define OV_I_CMN_RSTN BIT(4) +#define OV_I_INIT_RSTN BIT(6) + +#define PCIE_PHY_CMN_REG131 0x4C4 +#define PCIE_PHY_CMN_REG17B 0x5EC +#define PCIE_PHY_CMN_REG17D 0x5F4 +#define PCIE_PHY_CMN_REG190 0x640 +#define PCIE_PHY_CMN_REG191 0x644 +#define PCIE_PHY_CMN_REG192 0x648 +#define PCIE_PHY_CMN_REG1C7 0x71C +#define PCIE_PHY_CMN_REG1DF 0x77C +#define PCIE_PHY_CMN_REG1E0 0x780 + +#define PCIE_PHY_CMN_REG0B1 0x2C4 +#define ANA_ROPLL_REF_DIG_CLK_SEL BIT(2) + +/* External clock */ +#define PCIE_PHY_CMN_REG14D 0x534 +#define PCIE_AUX_RX_MODE_EXTEND BIT(7) + +#define PCIE_PHY_CMN_REG0D9 0x364 +#define ANA_AUX_EXT_REF_CLK_SEL BIT(4) + +#define PCIE_PHY_CMN_REG10F 0x43C +#define AUX_PLL_EN_EXTEND BIT(4) + +#define PCIE_PHY_CMN_REG11E 0x478 +#define AUX2_PLL_EN_EXTEND BIT(3) + +#define PCIE_PHY_CMN_REG0D4 0x350 +#define OV_S_ANA_AUX_EN BIT(3) +#define OV_I_ANA_AUX_EN BIT(2) + +/* LANE registers */ +#define PCIE_PHY_TRSV_REG22D 0x8B4 +#define PCIE_PHY_TRSV_REG23E 0x8F8 +#define PCIE_PHY_TRSV_REG2A5 0xA94 +#define PCIE_PHY_TRSV_REG3E3 0xF8C +#define PCIE_PHY_TRSV_REG3ED 0xFB4 +#define PCIE_PHY_TRSV_REG20B 0x82C +#define PCIE_PHY_TRSV_REG20C 0x830 +#define PCIE_PHY_TRSV_REG234 0x8D0 +#define PCIE_PHY_TRSV_REG235 0x8D4 +#define PCIE_PHY_TRSV_REG237 0x8DC +#define PCIE_PHY_TRSV_REG239 0x8E4 +#define PCIE_PHY_TRSV_REG23A 0x8E8 +#define PCIE_PHY_TRSV_REG23B 0x8EC +#define PCIE_PHY_TRSV_REG24B 0x92C +#define PCIE_PHY_TRSV_REG25D 0x974 +#define PCIE_PHY_TRSV_REG262 0x988 +#define PCIE_PHY_TRSV_REG271 0x9C4 +#define PCIE_PHY_TRSV_REG272 0x9C8 +#define PCIE_PHY_TRSV_REG27C 0x9F0 +#define PCIE_PHY_TRSV_REG27D 0x9F4 +#define PCIE_PHY_TRSV_REG27E 0x9F8 +#define PCIE_PHY_TRSV_REG284 0xA10 +#define PCIE_PHY_TRSV_REG289 0xA24 +#define PCIE_PHY_TRSV_REG28A 0xA28 +#define PCIE_PHY_TRSV_REG28B 0xA2C +#define PCIE_PHY_TRSV_REG28C 0xA30 +#define PCIE_PHY_TRSV_REG28E 0xA38 +#define PCIE_PHY_TRSV_REG28F 0xA3C +#define PCIE_PHY_TRSV_REG290 0xA40 +#define PCIE_PHY_TRSV_REG291 0xA44 +#define PCIE_PHY_TRSV_REG292 0xA48 +#define PCIE_PHY_TRSV_REG294 0xA50 +#define PCIE_PHY_TRSV_REG295 0xA54 +#define PCIE_PHY_TRSV_REG296 0xA58 +#define PCIE_PHY_TRSV_REG297 0xA5C +#define PCIE_PHY_TRSV_REG298 0xA60 +#define PCIE_PHY_TRSV_REG29B 0xA6C +#define PCIE_PHY_TRSV_REG29C 0xA70 +#define PCIE_PHY_TRSV_REG29D 0xA74 +#define PCIE_PHY_TRSV_REG29E 0xA78 +#define PCIE_PHY_TRSV_REG2AA 0xAA8 +#define PCIE_PHY_TRSV_REG2AE 0xAB8 +#define PCIE_PHY_TRSV_REG2C2 0xB08 +#define PCIE_PHY_TRSV_REG2C6 0xB18 +#define PCIE_PHY_TRSV_REG2C7 0xB1C +#define PCIE_PHY_TRSV_REG2CB 0xB2C +#define PCIE_PHY_TRSV_REG2CC 0xB30 +#define PCIE_PHY_TRSV_REG2CD 0xB34 +#define PCIE_PHY_TRSV_REG2CE 0xB38 +#define PCIE_PHY_TRSV_REG2D0 0xB40 +#define PCIE_PHY_TRSV_REG2CF 0xB3C +#define PCIE_PHY_TRSV_REG2E0 0xB80 +#define PCIE_PHY_TRSV_REG2E9 0xBA4 +#define PCIE_PHY_TRSV_REG2EA 0xBA8 +#define PCIE_PHY_TRSV_REG2EB 0xBAC +#define PCIE_PHY_TRSV_REG315 0xC54 +#define PCIE_PHY_TRSV_REG317 0xC5C +#define PCIE_PHY_TRSV_REG319 0xC64 +#define PCIE_PHY_TRSV_REG364 0xD90 +#define PCIE_PHY_TRSV_REG36C 0xDB0 +#define PCIE_PHY_TRSV_REG36D 0xDB4 +#define PCIE_PHY_TRSV_REG37E 0xDF8 +#define PCIE_PHY_TRSV_REG37F 0xDFC +#define PCIE_PHY_TRSV_REG38F 0xE3C +#define PCIE_PHY_TRSV_REG391 0xE44 +#define PCIE_PHY_TRSV_REG39C 0xE70 +#define PCIE_PHY_TRSV_REG3A8 0xEA0 +#define PCIE_PHY_TRSV_REG3E0 0xF80 +#define PCIE_PHY_TRSV_REG3E1 0xF84 +#define PCIE_PHY_TRSV_REG3E7 0xF9C +#define PCIE_PHY_TRSV_REG3E9 0xFA4 +#define PCIE_PHY_TRSV_REG3EA 0xFA8 +#define PCIE_PHY_TRSV_REG3EE 0xFB8 +#define PCIE_PHY_TRSV_REG3EF 0xFBC +#define PCIE_PHY_TRSV_REG3F0 0xFC0 + +#define PCIE_PHY_TRSV_REG2C0 0xB00 +#define LN_EQ_CTRL_RX_DATA_HOLD BIT(5) + +/* RX Preset registers */ +#define PCIE_PHY_CMN_REG17E 0x5F8 +#define PCIE_PHY_CMN_REG180 0x600 +#define PCIE_PHY_CMN_REG181 0x604 +#define PCIE_PHY_CMN_REG182 0x608 +#define PCIE_PHY_CMN_REG183 0x60C +#define PCIE_PHY_CMN_REG184 0x610 +#define PCIE_PHY_CMN_REG185 0x614 +#define PCIE_PHY_CMN_REG186 0x618 +#define PCIE_PHY_CMN_REG187 0x61C + + +/* ARTPEC-8 PCIe PCS registers */ +#define PCIE_PCS_OUT_VEC_4 0x154 +#define B1_DYNAMIC BIT(3) + +/* ARTPEC-8 SYS REG registers */ +#define FSYS_PCIE_CON 0x424 +#define PCIE_PHY_LCPLL_REFCLK_SEL 0x3 +#define PCIE_PHY_ROPLL_REFCLK_SEL (0x3UL << 2) +#define ROPLL_REFCLK_NOT_AVAILABLE (0x2UL << 2) +#define PCIE_PHY_LN0_REFCLK_PAD_EN BIT(10) +#define PCIE_PHY_LN1_REFCLK_PAD_EN BIT(11) +#define PCIE_PHY_PWR_OFF BIT(7) + +/* ARTPEC-8 Sub Controller registers */ +#define SFR_INIT_RSTN 0x1404 +#define SFR_CMN_RSTN 0x1408 + +#define PCIE_PHY_LN0_REG_START 0x800 +#define PCIE_PHY_LN0_REG_END 0xFCC +#define OFFSET_PER_LANE 0x800 + +enum artpec8_pcie_phy_num_lanes { + LANE0 =3D 0, + LANE1, + LANE_MAX +}; + +struct artpec8_pcie_phy_data { + const struct phy_ops *ops; +}; + +struct artpec8_pcie_phy { + const struct artpec8_pcie_phy_data *drv_data; + void __iomem *phy_base; + void __iomem *pcs_base; + void __iomem *elbi_base; + struct clk *soc_pll_clk; + struct regmap *sysreg; + u32 lcpll_ref_clk; + const char *mode; + u32 num_lanes; +}; + +enum artpec8_pcie_ref_clk { + REF_CLK_FROM_XO =3D 0, + REF_CLK_FROM_IO, + REF_CLK_RESERVED, + REF_CLK_FROM_SOC_PLL, + REF_CLK_MAX +}; + +struct artpec8_pcie_phy_tune_reg { + u32 offset; + u32 val; +}; + +/* ARTPEC-8 PCIe Gen4 x2 PHY CMN register settings */ +static const struct artpec8_pcie_phy_tune_reg cmn_regs[] =3D { + {PCIE_PHY_CMN_REG004, 0x65}, + {PCIE_PHY_CMN_REG00B, 0x18}, + {PCIE_PHY_CMN_REG016, 0x0E}, + {PCIE_PHY_CMN_REG01C, 0x4F}, + {PCIE_PHY_CMN_REG021, 0x01}, + {PCIE_PHY_CMN_REG024, 0x58}, + {PCIE_PHY_CMN_REG025, 0x98}, + {PCIE_PHY_CMN_REG0E6, 0x00}, + {PCIE_PHY_CMN_REG0E7, 0x00}, + {PCIE_PHY_CMN_REG0E8, 0x3F}, + {PCIE_PHY_CMN_REG0E9, 0x3F}, + {PCIE_PHY_CMN_REG0EA, 0xFF}, + {PCIE_PHY_CMN_REG0EB, 0xFF}, + {PCIE_PHY_CMN_REG0EC, 0x42}, + {PCIE_PHY_CMN_REG0EE, 0x3F}, + {PCIE_PHY_CMN_REG0EF, 0x7F}, + {PCIE_PHY_CMN_REG0F1, 0x02}, + {PCIE_PHY_CMN_REG0F3, 0xFF}, + {PCIE_PHY_CMN_REG0F4, 0xFF}, + {PCIE_PHY_CMN_REG131, 0x01}, + {PCIE_PHY_CMN_REG17B, 0xC0}, + {PCIE_PHY_CMN_REG17D, 0xAF}, + {PCIE_PHY_CMN_REG190, 0x27}, + {PCIE_PHY_CMN_REG191, 0x0F}, + {PCIE_PHY_CMN_REG192, 0x3F}, + {PCIE_PHY_CMN_REG1C7, 0x05}, + {PCIE_PHY_CMN_REG1DF, 0x28}, + {PCIE_PHY_CMN_REG1E0, 0x28}, +}; + +/* ARTPEC-8 PCIe Gen4 x2 PHY lane register settings */ +static const struct artpec8_pcie_phy_tune_reg lane_regs[] =3D { + {PCIE_PHY_TRSV_REG22D, 0x00}, + {PCIE_PHY_TRSV_REG23E, 0x00}, + {PCIE_PHY_TRSV_REG2A5, 0x73}, + {PCIE_PHY_TRSV_REG3E3, 0x7B}, + {PCIE_PHY_TRSV_REG3ED, 0x4B}, + {PCIE_PHY_TRSV_REG20B, 0x02}, + {PCIE_PHY_TRSV_REG20C, 0xEA}, + {PCIE_PHY_TRSV_REG234, 0x7A}, + {PCIE_PHY_TRSV_REG235, 0x1C}, + {PCIE_PHY_TRSV_REG237, 0x10}, + {PCIE_PHY_TRSV_REG239, 0x68}, + {PCIE_PHY_TRSV_REG23A, 0xC0}, + {PCIE_PHY_TRSV_REG23B, 0x0B}, + {PCIE_PHY_TRSV_REG24B, 0x00}, + {PCIE_PHY_TRSV_REG25D, 0x07}, + {PCIE_PHY_TRSV_REG262, 0x07}, + {PCIE_PHY_TRSV_REG271, 0x23}, + {PCIE_PHY_TRSV_REG272, 0x5E}, + {PCIE_PHY_TRSV_REG27C, 0x8C}, + {PCIE_PHY_TRSV_REG27D, 0x5B}, + {PCIE_PHY_TRSV_REG27E, 0x2C}, + {PCIE_PHY_TRSV_REG284, 0x33}, + {PCIE_PHY_TRSV_REG289, 0xD4}, + {PCIE_PHY_TRSV_REG28A, 0xCC}, + {PCIE_PHY_TRSV_REG28B, 0xD9}, + {PCIE_PHY_TRSV_REG28C, 0xDC}, + {PCIE_PHY_TRSV_REG28E, 0xC6}, + {PCIE_PHY_TRSV_REG28F, 0x90}, + {PCIE_PHY_TRSV_REG290, 0x4D}, + {PCIE_PHY_TRSV_REG291, 0x19}, + {PCIE_PHY_TRSV_REG292, 0x1C}, + {PCIE_PHY_TRSV_REG294, 0x05}, + {PCIE_PHY_TRSV_REG295, 0x10}, + {PCIE_PHY_TRSV_REG296, 0x0C}, + {PCIE_PHY_TRSV_REG297, 0x19}, + {PCIE_PHY_TRSV_REG298, 0x04}, + {PCIE_PHY_TRSV_REG29B, 0x03}, + {PCIE_PHY_TRSV_REG29C, 0x1B}, + {PCIE_PHY_TRSV_REG29D, 0x1B}, + {PCIE_PHY_TRSV_REG29E, 0x1F}, + {PCIE_PHY_TRSV_REG2AA, 0x00}, + {PCIE_PHY_TRSV_REG2AE, 0x1F}, + {PCIE_PHY_TRSV_REG2C2, 0x25}, + {PCIE_PHY_TRSV_REG2C6, 0x10}, + {PCIE_PHY_TRSV_REG2C7, 0x06}, + {PCIE_PHY_TRSV_REG2CB, 0x10}, + {PCIE_PHY_TRSV_REG2CC, 0x06}, + {PCIE_PHY_TRSV_REG2CD, 0x20}, + {PCIE_PHY_TRSV_REG2CE, 0x27}, + {PCIE_PHY_TRSV_REG2D0, 0x10}, + {PCIE_PHY_TRSV_REG2CF, 0x0A}, + {PCIE_PHY_TRSV_REG2E0, 0x01}, + {PCIE_PHY_TRSV_REG2E9, 0x11}, + {PCIE_PHY_TRSV_REG2EA, 0x05}, + {PCIE_PHY_TRSV_REG2EB, 0x4C}, + {PCIE_PHY_TRSV_REG315, 0x18}, + {PCIE_PHY_TRSV_REG317, 0x86}, + {PCIE_PHY_TRSV_REG319, 0x8E}, + {PCIE_PHY_TRSV_REG364, 0x00}, + {PCIE_PHY_TRSV_REG36C, 0x03}, + {PCIE_PHY_TRSV_REG36D, 0x04}, + {PCIE_PHY_TRSV_REG37E, 0x06}, + {PCIE_PHY_TRSV_REG37F, 0x04}, + {PCIE_PHY_TRSV_REG38F, 0x40}, + {PCIE_PHY_TRSV_REG391, 0x8B}, + {PCIE_PHY_TRSV_REG39C, 0xFF}, + {PCIE_PHY_TRSV_REG3A8, 0x02}, + {PCIE_PHY_TRSV_REG3E0, 0x93}, + {PCIE_PHY_TRSV_REG3E1, 0x79}, + {PCIE_PHY_TRSV_REG3E7, 0xF5}, + {PCIE_PHY_TRSV_REG3E9, 0x75}, + {PCIE_PHY_TRSV_REG3EA, 0x0D}, + {PCIE_PHY_TRSV_REG3EE, 0xE2}, + {PCIE_PHY_TRSV_REG3EF, 0x6F}, + {PCIE_PHY_TRSV_REG3F0, 0x3D} +}; + +static const struct artpec8_pcie_phy_tune_reg rx_preset_regs[] =3D { + /* 0 */ + {PCIE_PHY_CMN_REG17E, 0x00}, + {PCIE_PHY_CMN_REG180, 0x23}, + {PCIE_PHY_CMN_REG181, 0x44}, + {PCIE_PHY_CMN_REG182, 0x61}, + {PCIE_PHY_CMN_REG183, 0x55}, + {PCIE_PHY_CMN_REG184, 0x14}, + {PCIE_PHY_CMN_REG185, 0x23}, + {PCIE_PHY_CMN_REG186, 0x1A}, + {PCIE_PHY_CMN_REG187, 0x04}, + {PCIE_PHY_CMN_REG17E, 0x04}, + {PCIE_PHY_CMN_REG17E, 0x00}, + /* 1 */ + {PCIE_PHY_CMN_REG17E, 0x08}, + {PCIE_PHY_CMN_REG181, 0x42}, + {PCIE_PHY_CMN_REG17E, 0x0C}, + {PCIE_PHY_CMN_REG17E, 0x08}, + /* 2 */ + {PCIE_PHY_CMN_REG17E, 0x10}, + {PCIE_PHY_CMN_REG181, 0x40}, + {PCIE_PHY_CMN_REG17E, 0x14}, + {PCIE_PHY_CMN_REG17E, 0x10}, + /* 3 */ + {PCIE_PHY_CMN_REG17E, 0x18}, + {PCIE_PHY_CMN_REG181, 0x45}, + {PCIE_PHY_CMN_REG17E, 0x1C}, + {PCIE_PHY_CMN_REG17E, 0x18}, + /* 4 */ + {PCIE_PHY_CMN_REG17E, 0x20}, + {PCIE_PHY_CMN_REG181, 0x46}, + {PCIE_PHY_CMN_REG17E, 0x24}, + {PCIE_PHY_CMN_REG17E, 0x20}, + /* 5 */ + {PCIE_PHY_CMN_REG17E, 0x28}, + {PCIE_PHY_CMN_REG181, 0x48}, + {PCIE_PHY_CMN_REG17E, 0x2C}, + {PCIE_PHY_CMN_REG17E, 0x28}, + /* 6 */ + {PCIE_PHY_CMN_REG17E, 0x30}, + {PCIE_PHY_CMN_REG181, 0x4A}, + {PCIE_PHY_CMN_REG17E, 0x34}, + {PCIE_PHY_CMN_REG17E, 0x30}, + /* 7 */ + {PCIE_PHY_CMN_REG17E, 0x38}, + {PCIE_PHY_CMN_REG181, 0x4C}, + {PCIE_PHY_CMN_REG17E, 0x3C}, + {PCIE_PHY_CMN_REG17E, 0x38}, + /* 8 */ + {PCIE_PHY_CMN_REG17E, 0x40}, + {PCIE_PHY_CMN_REG180, 0x20}, + {PCIE_PHY_CMN_REG181, 0x20}, + {PCIE_PHY_CMN_REG182, 0x01}, + {PCIE_PHY_CMN_REG17E, 0x44}, + {PCIE_PHY_CMN_REG17E, 0x40}, + /* 9 */ + {PCIE_PHY_CMN_REG17E, 0x48}, + {PCIE_PHY_CMN_REG180, 0x20}, + {PCIE_PHY_CMN_REG181, 0x21}, + {PCIE_PHY_CMN_REG182, 0x01}, + {PCIE_PHY_CMN_REG17E, 0x4C}, + {PCIE_PHY_CMN_REG17E, 0x48}, + /* 10 */ + {PCIE_PHY_CMN_REG17E, 0x50}, + {PCIE_PHY_CMN_REG180, 0x24}, + {PCIE_PHY_CMN_REG181, 0x80}, + {PCIE_PHY_CMN_REG182, 0x41}, + {PCIE_PHY_CMN_REG183, 0xAF}, + {PCIE_PHY_CMN_REG184, 0x26}, + {PCIE_PHY_CMN_REG185, 0x34}, + {PCIE_PHY_CMN_REG186, 0x24}, + {PCIE_PHY_CMN_REG187, 0x06}, + {PCIE_PHY_CMN_REG17E, 0x54}, + {PCIE_PHY_CMN_REG17E, 0x50}, + /* 11 */ + {PCIE_PHY_CMN_REG17E, 0x58}, + {PCIE_PHY_CMN_REG181, 0x81}, + {PCIE_PHY_CMN_REG17E, 0x5C}, + {PCIE_PHY_CMN_REG17E, 0x58}, + /* 12 */ + {PCIE_PHY_CMN_REG17E, 0x60}, + {PCIE_PHY_CMN_REG181, 0x82}, + {PCIE_PHY_CMN_REG17E, 0x64}, + {PCIE_PHY_CMN_REG17E, 0x60}, + /* 13 */ + {PCIE_PHY_CMN_REG17E, 0x68}, + {PCIE_PHY_CMN_REG181, 0x83}, + {PCIE_PHY_CMN_REG17E, 0x6C}, + {PCIE_PHY_CMN_REG17E, 0x68}, + /* 14 */ + {PCIE_PHY_CMN_REG17E, 0x70}, + {PCIE_PHY_CMN_REG181, 0x84}, + {PCIE_PHY_CMN_REG17E, 0x74}, + {PCIE_PHY_CMN_REG17E, 0x70}, + /* 15 */ + {PCIE_PHY_CMN_REG17E, 0x78}, + {PCIE_PHY_CMN_REG180, 0x24}, + {PCIE_PHY_CMN_REG181, 0x85}, + {PCIE_PHY_CMN_REG182, 0x80}, + {PCIE_PHY_CMN_REG183, 0x7F}, + {PCIE_PHY_CMN_REG184, 0x2D}, + {PCIE_PHY_CMN_REG185, 0x34}, + {PCIE_PHY_CMN_REG186, 0x24}, + {PCIE_PHY_CMN_REG187, 0x05}, + {PCIE_PHY_CMN_REG17E, 0x7C}, + {PCIE_PHY_CMN_REG17E, 0x78}, + /* 16 */ + {PCIE_PHY_CMN_REG17E, 0x80}, + {PCIE_PHY_CMN_REG181, 0x86}, + {PCIE_PHY_CMN_REG17E, 0x84}, + {PCIE_PHY_CMN_REG17E, 0x80}, + /* 17 */ + {PCIE_PHY_CMN_REG17E, 0x88}, + {PCIE_PHY_CMN_REG181, 0x87}, + {PCIE_PHY_CMN_REG17E, 0x8C}, + {PCIE_PHY_CMN_REG17E, 0x88}, + /* 18 */ + {PCIE_PHY_CMN_REG17E, 0x90}, + {PCIE_PHY_CMN_REG181, 0x88}, + {PCIE_PHY_CMN_REG17E, 0x94}, + {PCIE_PHY_CMN_REG17E, 0x90}, + /* 19 */ + {PCIE_PHY_CMN_REG17E, 0x98}, + {PCIE_PHY_CMN_REG181, 0x89}, + {PCIE_PHY_CMN_REG17E, 0x9C}, + {PCIE_PHY_CMN_REG17E, 0x98}, +}; + +static void artpec8_pcie_phy_reg_update(void __iomem *base, u32 mask, + u32 update, u32 reg) +{ + u32 val; + + val =3D readl(base + reg); + val &=3D ~(mask); + val |=3D update; + writel(val, base + reg); +}; + +static void artpec8_pcie_enable_ref_clk_from_xo(struct artpec8_pcie_phy + *pciephy) +{ + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_LCPLL_REFCLK_SEL, + REF_CLK_FROM_XO); + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_ROPLL_REFCLK_SEL, + ROPLL_REFCLK_NOT_AVAILABLE); +}; + +static void artpec8_pcie_enable_ref_clk_from_io(struct artpec8_pcie_phy + *pciephy) +{ + artpec8_pcie_phy_reg_update(pciephy->phy_base, + PCIE_AUX_RX_MODE_EXTEND, 0, + PCIE_PHY_CMN_REG14D); + artpec8_pcie_phy_reg_update(pciephy->phy_base, + ANA_AUX_EXT_REF_CLK_SEL, 0, + PCIE_PHY_CMN_REG0D9); + artpec8_pcie_phy_reg_update(pciephy->phy_base, + AUX_PLL_EN_EXTEND, 0, + PCIE_PHY_CMN_REG10F); + artpec8_pcie_phy_reg_update(pciephy->phy_base, + AUX2_PLL_EN_EXTEND, 0, + PCIE_PHY_CMN_REG11E); + artpec8_pcie_phy_reg_update(pciephy->phy_base, + OV_S_ANA_AUX_EN, OV_S_ANA_AUX_EN, + PCIE_PHY_CMN_REG0D4); + artpec8_pcie_phy_reg_update(pciephy->phy_base, + OV_I_ANA_AUX_EN, OV_I_ANA_AUX_EN, + PCIE_PHY_CMN_REG0D4); + + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_LCPLL_REFCLK_SEL, + REF_CLK_FROM_IO); + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_ROPLL_REFCLK_SEL, + ROPLL_REFCLK_NOT_AVAILABLE); + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_LN0_REFCLK_PAD_EN, + PCIE_PHY_LN0_REFCLK_PAD_EN); + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_LN1_REFCLK_PAD_EN, + PCIE_PHY_LN1_REFCLK_PAD_EN); +} + +static void artpec8_pcie_enable_ref_clk_from_soc_pll(struct artpec8_pcie_p= hy + *pciephy) +{ + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_LCPLL_REFCLK_SEL, + REF_CLK_FROM_SOC_PLL); + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_ROPLL_REFCLK_SEL, + ROPLL_REFCLK_NOT_AVAILABLE); +} + +static void artpec8_pcie_lane_control(struct phy *phy, u32 lane0_reg, u32 = mask, + u32 val) +{ + struct artpec8_pcie_phy *pciephy =3D phy_get_drvdata(phy); + u32 lanex_reg =3D lane0_reg; + int i; + + if (lane0_reg < PCIE_PHY_LN0_REG_START || + lane0_reg > PCIE_PHY_LN0_REG_END) { + return; + } + + for (i =3D 0; i < pciephy->num_lanes; i++) { + lanex_reg +=3D OFFSET_PER_LANE * i; + artpec8_pcie_phy_reg_update(pciephy->phy_base, mask, val, + lanex_reg); + } +} + +static void artpec8_pcie_phy_tune(struct artpec8_pcie_phy *pciephy) +{ + int i, count; + + /* init cmn registers */ + count =3D ARRAY_SIZE(cmn_regs); + for (i =3D 0; i < count; i++) + writel(cmn_regs[i].val, pciephy->phy_base + cmn_regs[i].offset); + + /* init lane registers */ + count =3D ARRAY_SIZE(lane_regs); + for (i =3D 0; i < count; i++) { + writel(lane_regs[i].val, pciephy->phy_base + lane_regs[i].offset); + writel(lane_regs[i].val, pciephy->phy_base + lane_regs[i].offset + + OFFSET_PER_LANE); + } + + /* rx preset registers */ + count =3D ARRAY_SIZE(rx_preset_regs); + for (i =3D 0; i < count; i++) + writel(rx_preset_regs[i].val, pciephy->phy_base + rx_preset_regs[i].offs= et); +} + +static int artpec8_pcie_phy_init(struct phy *phy) +{ + struct artpec8_pcie_phy *pciephy =3D phy_get_drvdata(phy); + + /* reset init_rstn and cmn_rstn */ + artpec8_pcie_phy_reg_update(pciephy->phy_base, + OV_I_CMN_RSTN | OV_I_INIT_RSTN, 0, PCIE_PHY_CMN_REG101); + + /* reference clock selection */ + switch (pciephy->lcpll_ref_clk) { + case REF_CLK_FROM_XO: + artpec8_pcie_enable_ref_clk_from_xo(pciephy); + break; + case REF_CLK_FROM_IO: + artpec8_pcie_enable_ref_clk_from_io(pciephy); + break; + case REF_CLK_FROM_SOC_PLL: + artpec8_pcie_enable_ref_clk_from_soc_pll(pciephy); + break; + default: + break; + } + + /* release i_init_rstn */ + artpec8_pcie_phy_reg_update(pciephy->phy_base, OV_I_INIT_RSTN, + OV_I_INIT_RSTN, PCIE_PHY_CMN_REG101); + + /* phy initial settings */ + artpec8_pcie_phy_tune(pciephy); + + /* pll_en should be set to off when PM_STATE is P1.CPM */ + if (!strncmp(pciephy->mode, "pcie_ep", strlen("pcie_ep"))) { + artpec8_pcie_phy_reg_update(pciephy->pcs_base, B1_DYNAMIC, + B1_DYNAMIC, PCIE_PCS_OUT_VEC_4); + } + + /* disable lane eq ctrl rx data hold */ + artpec8_pcie_lane_control(phy, PCIE_PHY_TRSV_REG2C0, + LN_EQ_CTRL_RX_DATA_HOLD, 0); + + return 0; +} + +static int artpec8_pcie_phy_exit(struct phy *phy) +{ + return 0; +} + +static int artpec8_pcie_phy_reset(struct phy *phy) +{ + struct artpec8_pcie_phy *pciephy =3D phy_get_drvdata(phy); + + artpec8_pcie_phy_reg_update(pciephy->phy_base, OV_I_CMN_RSTN, + 0, PCIE_PHY_CMN_REG101); + udelay(10); + artpec8_pcie_phy_reg_update(pciephy->phy_base, OV_I_CMN_RSTN, + OV_I_CMN_RSTN, PCIE_PHY_CMN_REG101); + + return 0; +} + +static int artpec8_pcie_phy_power_on(struct phy *phy) +{ + struct artpec8_pcie_phy *pciephy =3D phy_get_drvdata(phy); + + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_PWR_OFF, 0); + + return 0; +} + +static int artpec8_pcie_phy_power_off(struct phy *phy) +{ + struct artpec8_pcie_phy *pciephy =3D phy_get_drvdata(phy); + + regmap_update_bits(pciephy->sysreg, FSYS_PCIE_CON, + PCIE_PHY_PWR_OFF, PCIE_PHY_PWR_OFF); + + return 0; +} + +static int artpec8_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct artpec8_pcie_phy *artpec8_phy; + struct phy *generic_phy; + struct phy_provider *phy_provider; + const struct artpec8_pcie_phy_data *drv_data; + + drv_data =3D of_device_get_match_data(dev); + if (!drv_data) + return -ENODEV; + + artpec8_phy =3D devm_kzalloc(dev, sizeof(*artpec8_phy), GFP_KERNEL); + if (!artpec8_phy) + return -ENOMEM; + + /* reference clock */ + if (of_property_read_u32(dev->of_node, "lcpll-ref-clk", + &artpec8_phy->lcpll_ref_clk)) { + return -EINVAL; + } + /* PLL SOC reference clock */ + if (artpec8_phy->lcpll_ref_clk =3D=3D REF_CLK_FROM_SOC_PLL) { + artpec8_phy->soc_pll_clk =3D devm_clk_get(dev, "ref_clk"); + if (IS_ERR(artpec8_phy->soc_pll_clk)) + return -EINVAL; + clk_prepare_enable(artpec8_phy->soc_pll_clk); + } + + /* link mode */ + if (of_property_read_string(dev->of_node, "mode", &artpec8_phy->mode)) + return -EINVAL; + + /* number of lanes */ + if (of_property_read_u32(dev->of_node, "num-lanes", + &artpec8_phy->num_lanes)) + return -EINVAL; + + if (artpec8_phy->num_lanes > LANE_MAX) + return -EINVAL; + + /* PHY base register */ + artpec8_phy->phy_base =3D devm_platform_ioremap_resource_byname(pdev, "ph= y"); + if (IS_ERR(artpec8_phy->phy_base)) + return PTR_ERR(artpec8_phy->phy_base); + + /* PCS base register */ + artpec8_phy->pcs_base =3D devm_platform_ioremap_resource_byname(pdev, "pc= s"); + if (IS_ERR(artpec8_phy->pcs_base)) + return PTR_ERR(artpec8_phy->pcs_base); + + /* sysreg regmap handle, need to change using smc */ + artpec8_phy->sysreg =3D + syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,fsys-sysreg"); + if (IS_ERR(artpec8_phy->sysreg)) + return PTR_ERR(artpec8_phy->sysreg); + + artpec8_phy->drv_data =3D drv_data; + + generic_phy =3D devm_phy_create(dev, dev->of_node, drv_data->ops); + if (IS_ERR(generic_phy)) + return PTR_ERR(generic_phy); + + phy_set_drvdata(generic_phy, artpec8_phy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + return 0; +} + +static int __exit artpec8_pcie_remove(struct platform_device *pdev) +{ + struct artpec8_pcie_phy *artpec8_phy =3D platform_get_drvdata(pdev); + + if (artpec8_phy->soc_pll_clk) + clk_disable_unprepare(artpec8_phy->soc_pll_clk); + + return 0; +} + +static const struct phy_ops artpec8_phy_ops =3D { + .init =3D artpec8_pcie_phy_init, + .exit =3D artpec8_pcie_phy_exit, + .reset =3D artpec8_pcie_phy_reset, + .power_on =3D artpec8_pcie_phy_power_on, + .power_off =3D artpec8_pcie_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct artpec8_pcie_phy_data artpec8_pcie_phy_data =3D { + .ops =3D &artpec8_phy_ops, +}; + +static const struct of_device_id artpec8_pcie_phy_match[] =3D { + { + .compatible =3D "axis,artpec8-pcie-phy", + .data =3D &artpec8_pcie_phy_data, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, artpec8_pcie_phy_match); + +static struct platform_driver artpec8_pcie_phy_driver =3D { + .probe =3D artpec8_pcie_phy_probe, + .remove =3D __exit_p(artpec8_pcie_phy_remove), + .driver =3D { + .of_match_table =3D artpec8_pcie_phy_match, + .name =3D "artpec8_pcie_phy", + } +}; + +module_platform_driver(artpec8_pcie_phy_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jaeho Cho "); --=20 2.9.5 From nobody Mon Apr 27 11:49:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8A9FC43334 for ; Tue, 14 Jun 2022 01:37:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348628AbiFNBhG (ORCPT ); Mon, 13 Jun 2022 21:37:06 -0400 Received: from lindbergh.monkeyblade.net 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b=Vjjx2N65kgRDYZY7Sp7dLCTBcfIHE+HxMbLG2WRiOhywO9ILdIKEZVJ0sCeLQbDDB Wd1wUmbFe+pNaK54Ti0byFI59+6NOUnufrJRfY0O8SAn8l29ZZve6+r8Qmcy/hhrHi YUS0FdzkqYhZbwh9t+b74aToy58/NIRvd6cpLnsk= Received: from epsnrtp2.localdomain (unknown [182.195.42.163]) by epcas2p2.samsung.com (KnoxPortal) with ESMTP id 20220614013656epcas2p2256307430c211ec0bd8ea70dcb1445dd~4WOgFFOWx0196001960epcas2p2m; Tue, 14 Jun 2022 01:36:56 +0000 (GMT) Received: from epsmges2p2.samsung.com (unknown [182.195.36.99]) by epsnrtp2.localdomain (Postfix) with ESMTP id 4LMWJ72XPhz4x9Q1; Tue, 14 Jun 2022 01:36:55 +0000 (GMT) X-AuditID: b6c32a46-f8bff70000002624-07-62a7e637a250 Received: from epcas2p3.samsung.com ( [182.195.41.55]) by epsmges2p2.samsung.com (Symantec Messaging Gateway) with SMTP id 9D.B7.09764.736E7A26; Tue, 14 Jun 2022 10:36:55 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v3 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: Wangseok Lee , "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim X-Priority: 3 X-Content-Kind-Code: NORMAL In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220614013654epcms2p6b8f11dd03c42b1dfcd908ed3e59c13d8@epcms2p6> Date: Tue, 14 Jun 2022 10:36:54 +0900 X-CMS-MailID: 20220614013654epcms2p6b8f11dd03c42b1dfcd908ed3e59c13d8 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: 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Add Jesper Nilsson and Lars Persson as maintainer for these files. ARTPEC-8 is the SoC platform of Axis Communications and PCIe PHY is designe d based on Samsung PHY. Signed-off-by: Wangseok Lee --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 475e2836..5ad377f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1876,12 +1876,14 @@ M: Jesper Nilsson M: Lars Persson L: linux-arm-kernel@axis.com S: Maintained +F: Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt F: arch/arm/boot/dts/artpec6* F: arch/arm/mach-artpec F: drivers/clk/axis F: drivers/crypto/axis F: drivers/mmc/host/usdhi6rol0.c +F: drivers/phy/artpec/phy-artpec* F: drivers/pinctrl/pinctrl-artpec* =20 ARM/ASPEED I2C DRIVER --=20 2.9.5