From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14B54CCA47F for ; Mon, 13 Jun 2022 20:48:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245232AbiFMUro (ORCPT ); Mon, 13 Jun 2022 16:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350060AbiFMUqA (ORCPT ); Mon, 13 Jun 2022 16:46:00 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7D471AD for ; Mon, 13 Jun 2022 12:57:23 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id e11so6666805pfj.5 for ; Mon, 13 Jun 2022 12:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JHEBqvjkXFtcJ+qUBNW7+1Xm1a5ZEnXcUDy9oMekAWQ=; b=XcS6UQmDf+C8m9YKYGOusnFCVffgrQStj//J+T4vtRpb8VgAsfxoTf7T3GaDso06eH X95kIF4IKwG/8S1JhVbbu1qsZ3G9zyJTb/zdPBrNw3e3u+BsafMvCjumd1H2HqBLF6sR vo5PIEn0Ap5GtqoJ/NomU+CELebXQIrQn0n2C4cFLCMrUu5MjFj33yt1uLkiNNMLY0Sz WG4+Pal6iFcZuCcYFuVLCJ4D8uGDiCXrROR+P1liCdgg0xVZthTk9ga0rBKF1byxNBQp mHgbrxODTBw7F49GcKmx80eRrSHJkNeSYWxOGbrGIt2oP4Xw3sss5OM9tn9bXFGZTI+y w3lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JHEBqvjkXFtcJ+qUBNW7+1Xm1a5ZEnXcUDy9oMekAWQ=; b=7CgOr448QIH3ZCpmmB0EjcSCRiCewUEbag3Ndav0gTMa7bP0wetzib0XSsBq1xNj9E aj9z6QxLFxgAze5bPwOAEe8Q2jVVIgjtzHpbcIRpIqoM2CJX/7LmqUSw4MZolRLcD4Kp HSd1l26ZNrcga97javdOq3jo7vFn+IuJcdL+ynw8kXI9T+fyfLwfq1FwnZ3uBpaLYZxU sOgAQN7BVQxozNkhGNvNhOl97/rZ0QxXNRLphP2KZ5zZR1d/kr6QmuRswqYMeuac7+6C TaPVofZU37YrcE/0t3BlW+82NxBPW+8/esNMW8nd1E4ef19Tzt6TzsR8yQHGHN2EXt8P dPjg== X-Gm-Message-State: AOAM53248GOZs6l5IY+E6thmIEpTmW7f8uTs36QO+jdbwRNxgvIaW6q2 mx5DlI7ZMyAh1yrvtJMQFpoQ1g== X-Google-Smtp-Source: ABdhPJxL8blns0CtPDB1nVU68TFXxXGjE2/ANBGPsJZvdFrheK2PZLnGISiJk46IluCp/UaTXYGycg== X-Received: by 2002:a63:5723:0:b0:3fd:d8b4:c19f with SMTP id l35-20020a635723000000b003fdd8b4c19fmr1081427pgb.137.1655150242909; Mon, 13 Jun 2022 12:57:22 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:22 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 01/15] dt-bindings: arm: add AMD Pensando boards Date: Mon, 13 Jun 2022 12:56:44 -0700 Message-Id: <20220613195658.5607-2-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Document the compatible for AMD Pensando Elba SoC boards. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Docu= mentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..9f3dea681d24 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms Device Tree Bindings + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BFDBCCA481 for ; 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Mon, 13 Jun 2022 12:57:25 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC binding Date: Mon, 13 Jun 2022 12:56:45 -0700 Message-Id: <20220613195658.5607-3-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Docume= ntation/devicetree/bindings/mmc/cdns,sdhci.yaml index 4207fed62dfe..35bc4cf6f214 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -13,10 +13,24 @@ maintainers: allOf: - $ref: mmc-controller.yaml =20 + - if: + properties: + compatible: + enum: + - amd,pensando-elba-sd4hc + then: + properties: + reg: + items: + - description: Cadence host controller registers + - description: Byte-lane control register + minItems: 2 + properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 673BDC433EF for ; Mon, 13 Jun 2022 20:48:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345150AbiFMUr5 (ORCPT ); Mon, 13 Jun 2022 16:47:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350763AbiFMUqK (ORCPT ); Mon, 13 Jun 2022 16:46:10 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4FD1FCD for ; Mon, 13 Jun 2022 12:57:28 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id 184so6469706pga.12 for ; Mon, 13 Jun 2022 12:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M1UYg7GTMwR8QvyF4WdR5Vji0u2SBVcigVMf7Zaauyw=; b=EFASMhPxpi6FpSPPbhA4uIbL4jXzSRVgwCZf55APSkj+/eWAdAy8zvth5EBe2WERCi cDGiWOtOniXXOIBMYlZXBGOhh09bhJWtLzz03ZX+6JmHSdzd1T/MlQGnem73/WOdTT+v ALYzBwhbtHI9GDakDwasxjMQV3KLjZzE1f84EBn9oYaedpyFKb09rruVziY96M9e3Arg tkfD2u8e1HkkbaSXwA1Atuva5Im7G6tJYq72sqiTRNzjOCe8UDRnawXFQ3uInBmpEoLZ /49q91RgMJfoxOeMozLo4SpDinJna4mxoqvs687H+ikEiUHR2xU1+PXsepQJO79Pdd/s XM6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M1UYg7GTMwR8QvyF4WdR5Vji0u2SBVcigVMf7Zaauyw=; b=GOuRX9lb4JiO5kv9rEhXLd1Iqe8yDfeNscsa+bStKDRTMAxuMZiH1cWEvNE4orgFvn DgxwxVOZco/9+P14ZRF8x55Tdect2DXnFvV5XfW7o915F830a4+XQyAnlB9qSuyBV7l+ QjCA3UXTmNjSeZuzSCE2p/+yZNZW7cksJgtsfbcJ/QnIB6hwKiRxBOY/FVLm6sQfDJWf VSFqy1Sua68VmQZ97eFzhiaibFwRdWHIbT+DO5C9KuWbuGQNRRL+I+fDOaYHvJarmu1u U76DZMngDsGZQgUkgYVVmT3EZggxPWpgdFGcTNPquc5hf1g9gjrUCQ8HyISGRZP+gwwW wkbQ== X-Gm-Message-State: AOAM533/goCDjJQCn2YzOJNOZOq3M/qgrMc5IzSlej6spuVClfP62OR0 YHXoavMfgNG5smJkBKX8tJOU9g== X-Google-Smtp-Source: ABdhPJxZ2q40smO9yqIlwfspIo8/tXk9SfFuRqNdL0nhnFvTOu8EKTI+j14CKPw8n+7CXVPu4OrTgA== X-Received: by 2002:a63:b55:0:b0:3fd:a384:bd10 with SMTP id a21-20020a630b55000000b003fda384bd10mr1102840pgl.534.1655150248432; Mon, 13 Jun 2022 12:57:28 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:28 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 03/15] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC Date: Mon, 13 Jun 2022 12:56:46 -0700 Message-Id: <20220613195658.5607-4-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 0a537fa3a641..9268a4882bfd 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,23 @@ allOf: required: - power-domains =20 + - if: + properties: + compatible: + enum: + - amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81C82CCA47B for ; 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Mon, 13 Jun 2022 12:57:30 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Date: Mon, 13 Jun 2022 12:56:47 -0700 Message-Id: <20220613195658.5607-5-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/D= ocumentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..2a55b947cffc 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -73,6 +73,8 @@ properties: - renesas,r9a06g032-spi # RZ/N1D - renesas,r9a06g033-spi # RZ/N1S - const: renesas,rzn1-spi # RZ/N1 + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi =20 reg: minItems: 1 --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60D69C43334 for ; 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Mon, 13 Jun 2022 12:57:32 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 05/15] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Date: Mon, 13 Jun 2022 12:56:48 -0700 Message-Id: <20220613195658.5607-6-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add the AMD Pensando Elba SoC system registers compatible. Signed-off-by: Brad Larson Acked-by: Rob Herring --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index fb784045013f..2267f8828e9e 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - amd,pensando-elba-syscon - brcm,cru-clkset - freecom,fsg-cs2-system-controller - hisilicon,dsa-subctrl --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 783CDC43334 for ; Mon, 13 Jun 2022 20:47:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350869AbiFMUrE (ORCPT ); Mon, 13 Jun 2022 16:47:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350859AbiFMUqP (ORCPT ); Mon, 13 Jun 2022 16:46:15 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEAF563E8 for ; Mon, 13 Jun 2022 12:57:35 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id cx11so6586264pjb.1 for ; Mon, 13 Jun 2022 12:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CxeTCAcTP8AUI8T+Y1RRaiE90Utk4Y2UEreNjJtF518=; b=K/v2jO5IdTe/h76LE2Jxy/tvRZn9AmCccVf1AkXLWlMIzbkmxYm/ZwgFbNO6+3O/Kt 4V9MpxjJroIQakw44BkG+KTieiewz5bO7dRHXDEYbW2tFWdQITQLEFjkVgAgZ++w3zb3 yQ+q0XcGD9QYgULfH+JLrJSAajGFvEvYoFa98mhY72p+MamwyB57K4GpYYQK7hqwOIWw GxxplsF/k6yXLLYJLUdbfWE7FYArvAyiFDSlvX3GjiDAqFHAQUD9anUbzfRM7jJ3VuHK rRt50hbqOH9hhJjNwcJWT8Nait8EO2Mt3MiqE6MXiqHbK1X2Lj1c0ICx66Z5Xo82ZRC5 ysjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CxeTCAcTP8AUI8T+Y1RRaiE90Utk4Y2UEreNjJtF518=; b=pAaxASm0Qo5hKUeG/sSZPgtGR/pbcLvTJB67VahTuG/9/5EpBBHx0VjR6QZDpsMn9m Q2nFuwmJK3LZfQemEs1hwVHRMLLu8CcHHMDjbHxuFuYf4Lw4zWxBm2VXOV4ibofrhqjA gO8iu/Eugd7vCruo0GexwR9ekIdQeTBYN6C3fI9QFUIVKYXCdulc/57R6jYZ88qGVgmx 6uRBuY7x8x5MW+IBRFer8+EBMiXyvTo+8IVQ5KWzb626Xs/9vDOzHqQ/OSJq4EVfhzq6 Ely1X7oKqiqUqWYjzKWBw5J14ef+hXFTpOFXAwcs9876CDHkOE9MzNmqoDiGu4Y8xW3A h51A== X-Gm-Message-State: AJIora8Hq2xSvpg+ER0DzTM2y6P7fokwGF4wmTipmFTIW9P8aA04naFt 0P7Bcy5u+1gRW12FGhNci4cWNg== X-Google-Smtp-Source: AGRyM1uaxRjzT8MWjnK6bWvdvwkw+v6UKaPUZDECQDILWdwJMIHOst5z4ufQem0zzfJHU5KaXms+Sw== X-Received: by 2002:a17:902:a613:b0:168:a216:f3ff with SMTP id u19-20020a170902a61300b00168a216f3ffmr584840plq.21.1655150254961; Mon, 13 Jun 2022 12:57:34 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:34 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 06/15] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Mon, 13 Jun 2022 12:56:49 -0700 Message-Id: <20220613195658.5607-7-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add support for the AMD Pensando Elba SoC System Resource chip using the SPI interface. The Elba SR is a Multi-function Device supporting device register access using CS0, smbus interface for FRU and board peripherals using CS1, dual Lattice I2C masters for transceiver management using CS2, and CS3 for flash access. Signed-off-by: Brad Larson --- .../bindings/mfd/amd,pensando-elbasr.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elba= sr.yaml diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml= b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml new file mode 100644 index 000000000000..13356800b1cf --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/amd,pensando-elbasr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Resource Controller bindings + +description: | + AMD Pensando Elba SoC Resource Controller bindings attached to a SPI bus. + +maintainers: + - Brad Larson + +properties: + compatible: + items: + - enum: + - amd,pensando-elbasr + - const: simple-mfd + + spi-max-frequency: + description: Maximum SPI frequency of the device in Hz. + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - spi-max-frequency + +patternProperties: + '^reset-controller@[a-f0-9]+$': + $ref: ../reset/amd,pensando-elbasr-reset.yaml + +additionalProperties: false + +examples: + - | + #include + #include + + spi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + num-cs =3D <4>; + + spi@0 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + spi-max-frequency =3D <12000000>; + + rstc: reset-controller@0 { + compatible =3D "amd,pensando-elbasr-reset"; + reg =3D <0>; + #reset-cells =3D <1>; + }; + }; + + spi@1 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <1>; + spi-max-frequency =3D <12000000>; + }; + + spi@2 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <2>; + spi-max-frequency =3D <12000000>; + interrupt-parent =3D <&porta>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + }; + + spi@3 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <3>; + spi-max-frequency =3D <12000000>; + }; + }; + +... --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09573CCA47B for ; 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Mon, 13 Jun 2022 12:57:36 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 07/15] dt-bindings: reset: amd,pensando-elbasr-reset: Add AMD Pensando SR Reset Controller bindings Date: Mon, 13 Jun 2022 12:56:50 -0700 Message-Id: <20220613195658.5607-8-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Document bindings for AMD Pensando Elba SR Reset Controller Signed-off-by: Brad Larson --- .../reset/amd,pensando-elbasr-reset.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/amd,pensando-el= basr-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-re= set.yaml b/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-rese= t.yaml new file mode 100644 index 000000000000..03bb86ebcfd3 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/amd,pensando-elbasr-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Reset Controller Device Tree Bindings + +maintainers: + - Brad Larson + +description: | + AMD Pensando Elba SoC reset controller driver which supports a resource + controller connected to the Elba SoC over a SPI bus. The Elba reset + controller must be defined as a child node of the Elba SPI bus + chip-select 0 node. + + See also: + - dt-bindings/reset/amd,pensando-elba-reset.h + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: amd,pensando-elbasr-reset + + reg: + const: 0 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + spi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + num-cs =3D <4>; + + spi@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + rstc: reset-controller@0 { + compatible =3D "amd,pensando-elbasr-reset"; + reg =3D <0>; + #reset-cells =3D <1>; + }; + }; + }; + +... --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9D8ECCA481 for ; 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Mon, 13 Jun 2022 12:57:38 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 08/15] MAINTAINERS: Add entry for AMD PENSANDO Date: Mon, 13 Jun 2022 12:56:51 -0700 Message-Id: <20220613195658.5607-9-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 91e9cd30326d..09828169c7c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1777,6 +1777,16 @@ N: allwinner N: sun[x456789]i N: sun50i =20 +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/mfd/pensando* +F: drivers/reset/reset-elbasr.c +F: include/dt-bindings/reset/amd,pensando* + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E9CBCCA47F for ; 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Mon, 13 Jun 2022 12:57:41 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 09/15] arm64: Add config for AMD Pensando SoC platforms Date: Mon, 13 Jun 2022 12:56:52 -0700 Message-Id: <20220613195658.5607-10-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 4e6d635a1731..c650a89d8452 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -202,6 +202,18 @@ config ARCH_MXC This enables support for the ARMv8 based SoCs in the NXP i.MX family. =20 +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 318FDCCA47D for ; Mon, 13 Jun 2022 20:47:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351198AbiFMUrN (ORCPT ); Mon, 13 Jun 2022 16:47:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241546AbiFMUqc (ORCPT ); Mon, 13 Jun 2022 16:46:32 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A176DF66 for ; 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Mon, 13 Jun 2022 12:57:43 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:43 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 10/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Mon, 13 Jun 2022 12:56:53 -0700 Message-Id: <20220613195658.5607-11-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 103 ++++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++ 6 files changed, 618 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Mak= efile index 68103a8b0ef5..9bba020fa880 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SEATTLE) +=3D amd-overdrive-rev-b0.dtb amd-overdrive-rev= -b1.dtb +dtb-$(CONFIG_ARCH_PENSANDO) +=3D elba-asic.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts= /amd/elba-16core.dtsi new file mode 100644 index 000000000000..274dd80de1a4 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022 AMD Pensando + */ + +/ { + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { cpu =3D <&cpu0>; }; + core1 { cpu =3D <&cpu1>; }; + core2 { cpu =3D <&cpu2>; }; + core3 { cpu =3D <&cpu3>; }; + }; + + cluster1 { + core0 { cpu =3D <&cpu4>; }; + core1 { cpu =3D <&cpu5>; }; + core2 { cpu =3D <&cpu6>; }; + core3 { cpu =3D <&cpu7>; }; + }; + + cluster2 { + core0 { cpu =3D <&cpu8>; }; + core1 { cpu =3D <&cpu9>; }; + core2 { cpu =3D <&cpu10>; }; + core3 { cpu =3D <&cpu11>; }; + }; + + cluster3 { + core0 { cpu =3D <&cpu12>; }; + core1 { cpu =3D <&cpu13>; }; + core2 { cpu =3D <&cpu14>; }; + core3 { cpu =3D <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x0>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x1>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x2>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x3>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x100>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x101>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x102>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x103>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x200>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu9: cpu@201 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x201>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu10: cpu@202 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x202>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu11: cpu@203 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x203>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + l2_2: l2-cache2 { + compatible =3D "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x300>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu13: cpu@301 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x301>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu14: cpu@302 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x302>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu15: cpu@303 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x303>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + l2_3: l2-cache3 { + compatible =3D "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boo= t/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..155d35b8459f --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022, AMD Pensando + */ + +#include + +&ahb_clk { + clock-frequency =3D <400000000>; +}; + +&emmc_clk { + clock-frequency =3D <200000000>; +}; + +&flash_clk { + clock-frequency =3D <400000000>; +}; + +&ref_clk { + clock-frequency =3D <156250000>; +}; + +&qspi { + status =3D "okay"; + flash0: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + spi-rx-bus-width =3D <2>; + m25p,fast-read; + cdns,read-delay =3D <0>; + cdns,tshsl-ns =3D <0>; + cdns,tsd2d-ns =3D <0>; + cdns,tchsh-ns =3D <0>; + cdns,tslch-ns =3D <0>; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-hw-reset; + reset-names =3D "hw"; + resets =3D <&rstc EMMC_HW_RESET>; + status =3D "okay"; +}; + +&wdt0 { + status =3D "okay"; +}; + +&i2c0 { + clock-frequency =3D <100000>; + status =3D "okay"; + rtc@51 { + compatible =3D "nxp,pcf85263"; + reg =3D <0x51>; + }; +}; + +&spi0 { + num-cs =3D <4>; + cs-gpios =3D <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status =3D "okay"; + spi@0 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + spi-max-frequency =3D <12000000>; + + rstc: reset-controller@0 { + compatible =3D "amd,pensando-elbasr-reset"; + reg =3D <0>; + #reset-cells =3D <1>; + }; + }; + + spi@1 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <1>; + spi-max-frequency =3D <12000000>; + }; + + spi@2 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <2>; + spi-max-frequency =3D <12000000>; + interrupt-parent =3D <&porta>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + }; + + spi@3 { + compatible =3D "amd,pensando-elbasr", "simple-mfd"; + reg =3D <3>; + spi-max-frequency =3D <12000000>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/am= d/elba-asic.dts new file mode 100644 index 000000000000..bb64fd042b63 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright (c) 2020-2022 AMD Pensando + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model =3D "AMD Pensando Elba Board"; + compatible =3D "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 =3D &uart0; + spi0 =3D &spi0; + spi1 =3D &qspi; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boo= t/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..2599d1b22026 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022 AMD Pensando + */ + +&flash0 { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + partition@0 { + label =3D "flash"; + reg =3D <0x10000 0xfff0000>; + }; + + partition@f0000 { + label =3D "golduenv"; + reg =3D <0xf0000 0x10000>; + }; + + partition@100000 { + label =3D "boot0"; + reg =3D <0x100000 0x80000>; + }; + + partition@180000 { + label =3D "golduboot"; + reg =3D <0x180000 0x200000>; + }; + + partition@380000 { + label =3D "brdcfg0"; + reg =3D <0x380000 0x10000>; + }; + + partition@390000 { + label =3D "brdcfg1"; + reg =3D <0x390000 0x10000>; + }; + + partition@400000 { + label =3D "goldfw"; + reg =3D <0x400000 0x3c00000>; + }; + + partition@4010000 { + label =3D "fwmap"; + reg =3D <0x4010000 0x20000>; + }; + + partition@4030000 { + label =3D "fwsel"; + reg =3D <0x4030000 0x20000>; + }; + + partition@4090000 { + label =3D "bootlog"; + reg =3D <0x4090000 0x20000>; + }; + + partition@40b0000 { + label =3D "panicbuf"; + reg =3D <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label =3D "uservars"; + reg =3D <0x40d0000 0x20000>; + }; + + partition@4200000 { + label =3D "uboota"; + reg =3D <0x4200000 0x400000>; + }; + + partition@4600000 { + label =3D "ubootb"; + reg =3D <0x4600000 0x400000>; + }; + + partition@4a00000 { + label =3D "mainfwa"; + reg =3D <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label =3D "mainfwb"; + reg =3D <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label =3D "diaguboot"; + reg =3D <0x6a00000 0x400000>; + }; + + partition@8000000 { + label =3D "diagfw"; + reg =3D <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label =3D "ubootenv"; + reg =3D <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/el= ba.dtsi new file mode 100644 index 000000000000..9739641261c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022, AMD Pensando + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model =3D "Elba ASIC Board"; + compatible =3D "amd,pensando-elba"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + emmc_clk: oscillator2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + flash_clk: oscillator3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + ref_clk: oscillator4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c0: i2c@400 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x400 0x0 0x100>; + clocks =3D <&ahb_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-sda-hold-time-ns =3D <480>; + snps,sda-timeout-ms =3D <750>; + interrupts =3D ; + status =3D "disabled"; + }; + + wdt0: watchdog@1400 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x1400 0x0 0x100>; + clocks =3D <&ahb_clk>; + interrupts =3D ; + status =3D "disabled"; + }; + + qspi: spi@2400 { + compatible =3D "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg =3D <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&flash_clk>; + cdns,fifo-depth =3D <1024>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x7fff0000>; + status =3D "disabled"; + }; + + spi0: spi@2800 { + compatible =3D "amd,pensando-elba-spi"; + reg =3D <0x0 0x2800 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&ahb_clk>; + interrupts =3D ; + num-cs =3D <2>; + status =3D "disabled"; + }; + + gpio0: gpio@4000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x4000 0x0 0x78>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + porta: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <8>; + interrupts =3D ; + interrupt-controller; + interrupt-parent =3D <&gic>; + #interrupt-cells =3D <2>; + }; + + portb: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <8>; + }; + }; + + uart0: serial@4800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x4800 0x0 0x100>; + clocks =3D <&ref_clk>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + }; + + gic: interrupt-controller@800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + ranges; + interrupt-controller; + interrupts =3D ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells =3D <1>; + socionext,synquacer-pre-its =3D + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible =3D "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg =3D <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks =3D <&emmc_clk>; + interrupts =3D ; + cdns,phy-input-delay-sd-highspeed =3D <0x4>; + cdns,phy-input-delay-legacy =3D <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 =3D <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 =3D <0x16>; + mmc-ddr-1_8v; + status =3D "disabled"; + }; + + syscon: syscon@307c0000 { + compatible =3D "amd,pensando-elba-syscon", "syscon"; + reg =3D <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48A45CCA483 for ; Mon, 13 Jun 2022 20:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244339AbiFMUrh (ORCPT ); Mon, 13 Jun 2022 16:47:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242348AbiFMUqd (ORCPT ); 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Mon, 13 Jun 2022 12:57:45 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 11/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Mon, 13 Jun 2022 12:56:54 -0700 Message-Id: <20220613195658.5607-12-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 72b1a5a2298c..ebb77ea8e6ba 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -39,6 +39,7 @@ #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(4) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -87,6 +88,7 @@ struct cqspi_st { bool use_dma_read; u32 pd_dev_id; bool wr_completion; + bool apb_ahb_hazard; }; =20 struct cqspi_driver_platdata { @@ -952,6 +954,13 @@ static int cqspi_indirect_write_execute(struct cqspi_f= lash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); =20 + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + (void)readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; =20 @@ -1667,6 +1676,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->use_dma_read =3D true; if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) cqspi->wr_completion =3D false; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard =3D true; =20 if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1789,6 +1800,10 @@ static const struct cqspi_driver_platdata versal_osp= i =3D { .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 +static const struct cqspi_driver_platdata pen_cdns_qspi =3D { + .quirks =3D CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -1814,6 +1829,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "intel,socfpga-qspi", .data =3D &socfpga_qspi, }, + { + .compatible =3D "amd,pensando-elba-qspi", + .data =3D &pen_cdns_qspi, + }, { /* end of table */ } }; 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Mon, 13 Jun 2022 12:57:48 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:47 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 12/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Mon, 13 Jun 2022 12:56:55 -0700 Message-Id: <20220613195658.5607-13-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson --- drivers/spi/spi-dw-mmio.c | 66 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 5101c4c6017b..6b7a557759bd 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,24 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; =20 +struct dw_spi_elba { + struct regmap *syscon; +}; + +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_SHIFT(cs) (2 * (cs)) +#define ELBA_SPICS_MASK(cs) (0x3 << ELBA_SPICS_SHIFT(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | 0x1) << ELBA_SPICS_SHIFT(cs)) + /* * The Designware SPI controller (referred to as master in the documentati= on) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -238,6 +256,53 @@ static int dw_spi_canaan_k210_init(struct platform_dev= ice *pdev, return 0; } =20 +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, i= nt enable) +{ + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws =3D spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio =3D container_of(dws, struct dw_spi_mmio, dws= ); + struct dw_spi_elba *dwselba =3D dwsmmio->priv; + u8 cs; + + cs =3D spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(dwselba, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select =3D 0; + dw_spi_set_cs(spi, enable); + spi->chip_select =3D cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct dw_spi_elba *dwselba; + struct regmap *regmap; + + regmap =3D syscon_regmap_lookup_by_compatible("amd,pensando-elba-syscon"); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + dwselba =3D devm_kzalloc(&pdev->dev, sizeof(*dwselba), GFP_KERNEL); + if (!dwselba) + return -ENOMEM; + dwselba->syscon =3D regmap; + + dwsmmio->priv =3D dwselba; + dwsmmio->dws.set_cs =3D dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +417,7 @@ static const struct of_device_id dw_spi_mmio_of_match[]= =3D { { .compatible =3D "intel,keembay-ssi", .data =3D dw_spi_keembay_init}, { .compatible =3D "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible =3D "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible =3D "amd,pensando-elba-spi", .data =3D dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBCBDCCA482 for ; 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Mon, 13 Jun 2022 12:57:49 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Mon, 13 Jun 2022 12:56:56 -0700 Message-Id: <20220613195658.5607-14-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Add priv_write_l() which is used on Elba platforms for byte-lane control. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors. Signed-off-by: Brad Larson --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 179 ++++++++++++++++++++++++++++--- 2 files changed, 166 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index d6144978e32d..d0a66a74532e 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -243,6 +243,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. =20 diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 6f2de54a5987..08253357535a 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #include "sdhci-pltfm.h" =20 @@ -66,7 +67,12 @@ struct sdhci_cdns_phy_param { =20 struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; + void (*priv_write_l)(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -76,6 +82,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; =20 +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] =3D { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -90,6 +101,15 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_c= fgs[] =3D { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; =20 +static inline void sdhci_cdns_priv_writel(struct sdhci_cdns_priv *priv, + u32 val, void __iomem *reg) +{ + if (unlikely(priv->priv_write_l)) + priv->priv_write_l(priv, val, reg); + else + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +124,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns= _priv *priv, =20 tmp =3D FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); =20 tmp |=3D SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; =20 tmp &=3D ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +211,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_= priv *priv, u32 mode) tmp =3D readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &=3D ~SDHCI_CDNS_HRS06_MODE; tmp |=3D FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + sdhci_cdns_priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } =20 static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +243,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *h= ost, unsigned int val) */ for (i =3D 0; i < 2; i++) { tmp |=3D SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -309,6 +329,89 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_= host *host, sdhci_set_uhs_signaling(host, timing); } =20 +/* + * The Pensando Elba SoC explicitly controls byte-lane enables on writes + * which includes writes to the HRS registers. + */ +static void elba_priv_write_l(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(0x78, priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_write_l(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + unsigned long flags; + u32 m =3D (reg & 0x3); + u32 msk =3D (0x3 << (m)); + + spin_lock_irqsave(&priv->wrlock, flags); + writel(msk << 3, priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + unsigned long flags; + u32 m =3D (reg & 0x3); + u32 msk =3D (0x1 << (m)); + + spin_lock_irqsave(&priv->wrlock, flags); + writel(msk << 3, priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops =3D { + .write_l =3D elba_write_l, + .write_w =3D elba_write_w, + .write_b =3D elba_write_b, + .set_clock =3D sdhci_set_clock, + .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host =3D platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |=3D (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + + iomem =3D platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + + /* Byte-lane control register */ + ioaddr =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr =3D ioaddr; + priv->priv_write_l =3D elba_priv_write_l; + spin_lock_init(&priv->wrlock); + writel(0x78, priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops =3D { .set_clock =3D sdhci_set_clock, .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, @@ -318,15 +421,27 @@ static const struct sdhci_ops sdhci_cdns_ops =3D { .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, }; =20 -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data =3D { - .ops =3D &sdhci_cdns_ops, - .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data =3D { + .pltfm_data =3D { + .ops =3D &sdhci_cdns_ops, + .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; =20 -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data =3D { - .ops =3D &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data =3D { + .init =3D elba_drv_init, + .pltfm_data =3D { + .ops =3D &sdhci_elba_ops, + }, }; =20 +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data =3D { + .pltfm_data =3D { + .ops =3D &sdhci_cdns_ops, + }, +}; + + static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -347,10 +462,26 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct m= mc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } =20 +static void sdhci_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + + dev_info(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 9us for good measure */ + udelay(9); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -369,10 +500,10 @@ static int sdhci_cdns_probe(struct platform_device *p= dev) =20 data =3D of_device_get_match_data(dev); if (!data) - data =3D &sdhci_cdns_pltfm_data; + data =3D &sdhci_cdns_drv_data; =20 nr_phy_params =3D sdhci_cdns_phy_param_count(dev->of_node); - host =3D sdhci_pltfm_init(pdev, data, + host =3D sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret =3D PTR_ERR(host); @@ -389,6 +520,11 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) host->ioaddr +=3D SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe =3D sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret =3D data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); =20 @@ -404,6 +540,17 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) if (ret) goto free; =20 + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw =3D devm_reset_control_get_optional_exclusive(dev, "hw"); + if (IS_ERR(priv->rst_hw)) { + ret =3D PTR_ERR(priv->rst_hw); + if (ret =3D=3D -ENOENT) + priv->rst_hw =3D NULL; + } else { + host->mmc_host_ops.card_hw_reset =3D sdhci_mmc_hw_reset; + } + } + ret =3D sdhci_add_host(host); if (ret) goto free; @@ -453,7 +600,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops =3D { static const struct of_device_id sdhci_cdns_match[] =3D { { .compatible =3D "socionext,uniphier-sd4hc", - .data =3D &sdhci_cdns_uniphier_pltfm_data, + .data =3D &sdhci_cdns_uniphier_drv_data, + }, + { + .compatible =3D "amd,pensando-elba-sd4hc", + .data =3D &sdhci_elba_drv_data }, { .compatible =3D "cdns,sd4hc" }, { /* sentinel */ } --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3A09CCA480 for ; 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Mon, 13 Jun 2022 12:57:51 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 14/15] mfd: pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Mon, 13 Jun 2022 12:56:57 -0700 Message-Id: <20220613195658.5607-15-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson Add support for the AMD Pensando Elba SoC System Resource chip using the SPI interface. The Elba SR is a Multi-function Device supporting device register access using CS0, smbus interface for FRU and board peripherals using CS1, dual Lattice I2C masters for transceiver management using CS2, and CS3 for flash access. Signed-off-by: Brad Larson --- drivers/mfd/Kconfig | 14 + drivers/mfd/Makefile | 1 + drivers/mfd/pensando-elbasr.c | 862 ++++++++++++++++++++++++++++ include/linux/mfd/pensando-elbasr.h | 78 +++ 4 files changed, 955 insertions(+) create mode 100644 drivers/mfd/pensando-elbasr.c create mode 100644 include/linux/mfd/pensando-elbasr.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3b59456f5545..c5e10d302586 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1050,6 +1050,20 @@ config UCB1400_CORE To compile this driver as a module, choose M here: the module will be called ucb1400_core. =20 +config MFD_PENSANDO_ELBASR + bool "AMD Pensando Elba System Resource chip" + depends on SPI_MASTER=3Dy + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + select REGMAP_SPI + select MFD_CORE + select MFD_SYSCON + help + Support for the AMD Pensando Elba SoC System Resource chip using the + SPI interface. This driver provides userspace access to four device + functions to include CS0 device registers, CS1 smbus interface for + FRU and board peripherals, CS2 dual Lattice I2C masters for + transceiver management, and CS3 flash for firmware update. + config MFD_PM8XXX tristate "Qualcomm PM8xxx PMIC chips driver" depends on (ARM || HEXAGON || COMPILE_TEST) diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 858cacf659d6..917b128abe5b 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -212,6 +212,7 @@ obj-$(CONFIG_MFD_INTEL_LPSS_PCI) +=3D intel-lpss-pci.o obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) +=3D intel-lpss-acpi.o obj-$(CONFIG_MFD_INTEL_PMC_BXT) +=3D intel_pmc_bxt.o obj-$(CONFIG_MFD_PALMAS) +=3D palmas.o +obj-$(CONFIG_MFD_PENSANDO_ELBASR) +=3D pensando-elbasr.o obj-$(CONFIG_MFD_VIPERBOARD) +=3D viperboard.o obj-$(CONFIG_MFD_NTXEC) +=3D ntxec.o obj-$(CONFIG_MFD_RC5T583) +=3D rc5t583.o rc5t583-irq.o diff --git a/drivers/mfd/pensando-elbasr.c b/drivers/mfd/pensando-elbasr.c new file mode 100644 index 000000000000..f689f68f5377 --- /dev/null +++ b/drivers/mfd/pensando-elbasr.c @@ -0,0 +1,862 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * AMD Pensando Elba System Resource MFD Driver + * + * Userspace interface and reset driver support for SPI connected + * Pensando Elba System Resource Chip. + * + * Adapted from spidev.c + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * Copyright (C) 2007 David Brownell (simplification, cleanup) + * Copyright (C) 2022 AMD Pensando + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ELBASR_SPI_CMD_REGRD 0x0b +#define ELBASR_SPI_CMD_REGWR 0x02 +#define ELBASR_MAX_DEVS 4 + +/* The main reason to have this class is to make mdev/udev create the + * /dev/pensrB.C character device nodes exposing our userspace API. + * It also simplifies memory management. The device nodes + * /dev/pensrB.C are common across Pensando boards. + */ +static struct class *elbasr_class; + +static dev_t elbasr_devt; +static DECLARE_BITMAP(minors, ELBASR_MAX_DEVS); +static unsigned int bufsiz =3D 4096; + +static LIST_HEAD(device_list); +static DEFINE_MUTEX(device_list_lock); + +static const struct mfd_cell pensando_elbasr_subdev_info[] =3D { + { + .name =3D "pensando_elbasr_reset", + .of_compatible =3D "amd,pensando-elbasr-reset", + }, +}; + +/* Bit masks for spi_device.mode management. Note that incorrect + * settings for some settings can cause *lots* of trouble for other + * devices on a shared bus: + * + * - CS_HIGH ... this device will be active when it shouldn't be + * - 3WIRE ... when active, it won't behave as it should + * - NO_CS ... there will be no explicit message boundaries; this + * is completely incompatible with the shared bus model + * - READY ... transfers may proceed when they shouldn't. + */ +#define SPI_MODE_MASK (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH \ + | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ + | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \ + | SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \ + | SPI_RX_QUAD | SPI_RX_OCTAL) + +static ssize_t +elbasr_spi_sync(struct elbasr_data *elbasr_spi, struct spi_message *messag= e) +{ + int status; + struct spi_device *spi; + + spin_lock_irq(&elbasr_spi->spi_lock); + spi =3D elbasr_spi->spi; + spin_unlock_irq(&elbasr_spi->spi_lock); + + if (spi =3D=3D NULL) + status =3D -ESHUTDOWN; + else + status =3D spi_sync(spi, message); + + if (status =3D=3D 0) + status =3D message->actual_length; + + return status; +} + +static inline ssize_t +elbasr_spi_sync_write(struct elbasr_data *elbasr, size_t len) +{ + struct spi_transfer t =3D { + .tx_buf =3D elbasr->tx_buffer, + .len =3D len, + .speed_hz =3D elbasr->speed_hz, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return elbasr_spi_sync(elbasr, &m); +} + +static inline ssize_t +elbasr_spi_sync_read(struct elbasr_data *elbasr, size_t len) +{ + struct spi_transfer t =3D { + .rx_buf =3D elbasr->rx_buffer, + .len =3D len, + .speed_hz =3D elbasr->speed_hz, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return elbasr_spi_sync(elbasr, &m); +} + +/* Read-only message with current device setup */ +static ssize_t +elbasr_spi_read(struct file *filp, char __user *buf, size_t count, loff_t = *f_pos) +{ + struct elbasr_data *elbasr; + ssize_t status; + + /* chipselect only toggles at start or end of operation */ + if (count > bufsiz) + return -EMSGSIZE; + + elbasr =3D filp->private_data; + + mutex_lock(&elbasr->buf_lock); + status =3D elbasr_spi_sync_read(elbasr, count); + if (status > 0) { + unsigned long missing; + + missing =3D copy_to_user(buf, elbasr->rx_buffer, status); + if (missing =3D=3D status) + status =3D -EFAULT; + else + status =3D status - missing; + } + mutex_unlock(&elbasr->buf_lock); + + return status; +} + +/* Write-only message with current device setup */ +static ssize_t +elbasr_spi_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct elbasr_data *elbasr; + ssize_t status; + unsigned long missing; + + /* chipselect only toggles at start or end of operation */ + if (count > bufsiz) + return -EMSGSIZE; + + elbasr =3D filp->private_data; + + mutex_lock(&elbasr->buf_lock); + missing =3D copy_from_user(elbasr->tx_buffer, buf, count); + if (missing =3D=3D 0) + status =3D elbasr_spi_sync_write(elbasr, count); + else + status =3D -EFAULT; + mutex_unlock(&elbasr->buf_lock); + + return status; +} + +static int elbasr_spi_message(struct elbasr_data *elbasr, + struct spi_ioc_transfer *u_xfers, + unsigned int n_xfers) +{ + struct spi_message msg; + struct spi_transfer *k_xfers; + struct spi_transfer *k_tmp; + struct spi_ioc_transfer *u_tmp; + unsigned int n, total, tx_total, rx_total; + u8 *tx_buf, *rx_buf; + int status =3D -EFAULT; + + spi_message_init(&msg); + k_xfers =3D kcalloc(n_xfers, sizeof(*k_tmp), GFP_KERNEL); + if (k_xfers =3D=3D NULL) + return -ENOMEM; + + /* Construct spi_message, copying any tx data to bounce buffer. + * We walk the array of user-provided transfers, using each one + * to initialize a kernel version of the same transfer. + */ + tx_buf =3D elbasr->tx_buffer; + rx_buf =3D elbasr->rx_buffer; + total =3D 0; + tx_total =3D 0; + rx_total =3D 0; + for (n =3D n_xfers, k_tmp =3D k_xfers, u_tmp =3D u_xfers; + n; + n--, k_tmp++, u_tmp++) { + /* Ensure that also following allocations from rx_buf/tx_buf will meet + * DMA alignment requirements. + */ + unsigned int len_aligned =3D ALIGN(u_tmp->len, + ARCH_KMALLOC_MINALIGN); + + k_tmp->len =3D u_tmp->len; + + total +=3D k_tmp->len; + /* Since the function returns the total length of transfers + * on success, restrict the total to positive int values to + * avoid the return value looking like an error. Also check + * each transfer length to avoid arithmetic overflow. + */ + if (total > INT_MAX || k_tmp->len > INT_MAX) { + status =3D -EMSGSIZE; + goto done; + } + + if (u_tmp->rx_buf) { + /* this transfer needs space in RX bounce buffer */ + rx_total +=3D len_aligned; + if (rx_total > bufsiz) { + status =3D -EMSGSIZE; + goto done; + } + k_tmp->rx_buf =3D rx_buf; + rx_buf +=3D len_aligned; + } + if (u_tmp->tx_buf) { + /* this transfer needs space in TX bounce buffer */ + tx_total +=3D len_aligned; + if (tx_total > bufsiz) { + status =3D -EMSGSIZE; + goto done; + } + k_tmp->tx_buf =3D tx_buf; + if (copy_from_user(tx_buf, (const u8 __user *) + (uintptr_t) u_tmp->tx_buf, + u_tmp->len)) + goto done; + tx_buf +=3D len_aligned; + } + + k_tmp->cs_change =3D !!u_tmp->cs_change; + k_tmp->tx_nbits =3D u_tmp->tx_nbits; + k_tmp->rx_nbits =3D u_tmp->rx_nbits; + k_tmp->bits_per_word =3D u_tmp->bits_per_word; + k_tmp->delay.value =3D u_tmp->delay_usecs; + k_tmp->delay.unit =3D SPI_DELAY_UNIT_USECS; + k_tmp->speed_hz =3D u_tmp->speed_hz; + k_tmp->word_delay.value =3D u_tmp->word_delay_usecs; + k_tmp->word_delay.unit =3D SPI_DELAY_UNIT_USECS; + if (!k_tmp->speed_hz) + k_tmp->speed_hz =3D elbasr->speed_hz; +#ifdef VERBOSE + dev_dbg(&elbasr->spi->dev, + " xfer len %u %s%s%s%dbits %u usec %u usec %uHz (%u)\n", + k_tmp->len, + k_tmp->rx_buf ? "rx " : "", + k_tmp->tx_buf ? "tx " : "", + k_tmp->cs_change ? "cs " : "", + k_tmp->bits_per_word ? : elbasr->spi->bits_per_word, + k_tmp->delay.value, + k_tmp->word_delay.value, + k_tmp->speed_hz ? : elbasr->spi->max_speed_hz); +#endif + spi_message_add_tail(k_tmp, &msg); + } + + status =3D elbasr_spi_sync(elbasr, &msg); + if (status < 0) + goto done; + + /* copy any rx data out of bounce buffer */ + for (n =3D n_xfers, k_tmp =3D k_xfers, u_tmp =3D u_xfers; + n; + n--, k_tmp++, u_tmp++) { + if (u_tmp->rx_buf) { + if (copy_to_user((u8 __user *) + (uintptr_t) u_tmp->rx_buf, k_tmp->rx_buf, + u_tmp->len)) { + status =3D -EFAULT; + goto done; + } + } + } + status =3D total; + +done: + kfree(k_xfers); + return status; +} + +static struct spi_ioc_transfer * +elbasr_spi_get_ioc_message(unsigned int cmd, + struct spi_ioc_transfer __user *u_ioc, + unsigned int *n_ioc) +{ + u32 tmp; + + /* Check type, command number and direction */ + if (_IOC_TYPE(cmd) !=3D SPI_IOC_MAGIC + || _IOC_NR(cmd) !=3D _IOC_NR(SPI_IOC_MESSAGE(0)) + || _IOC_DIR(cmd) !=3D _IOC_WRITE) + return ERR_PTR(-ENOTTY); + + tmp =3D _IOC_SIZE(cmd); + if ((tmp % sizeof(struct spi_ioc_transfer)) !=3D 0) + return ERR_PTR(-EINVAL); + *n_ioc =3D tmp / sizeof(struct spi_ioc_transfer); + if (*n_ioc =3D=3D 0) + return NULL; + + /* copy into scratch area */ + return memdup_user(u_ioc, tmp); +} + +static long +elbasr_spi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int retval =3D 0; + struct elbasr_data *elbasr; + struct spi_device *spi; + u32 tmp; + unsigned int n_ioc; + struct spi_ioc_transfer *ioc; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) !=3D SPI_IOC_MAGIC) + return -ENOTTY; + + /* guard against device removal before, or while, + * we issue this ioctl. + */ + elbasr =3D filp->private_data; + spin_lock_irq(&elbasr->spi_lock); + spi =3D spi_dev_get(elbasr->spi); + spin_unlock_irq(&elbasr->spi_lock); + + if (spi =3D=3D NULL) + return -ESHUTDOWN; + + /* use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&elbasr->buf_lock); + + switch (cmd) { + /* read requests */ + case SPI_IOC_RD_MODE: + retval =3D put_user(spi->mode & SPI_MODE_MASK, + (__u8 __user *)arg); + break; + case SPI_IOC_RD_MODE32: + retval =3D put_user(spi->mode & SPI_MODE_MASK, + (__u32 __user *)arg); + break; + case SPI_IOC_RD_LSB_FIRST: + retval =3D put_user((spi->mode & SPI_LSB_FIRST) ? 1 : 0, + (__u8 __user *)arg); + break; + case SPI_IOC_RD_BITS_PER_WORD: + retval =3D put_user(spi->bits_per_word, (__u8 __user *)arg); + break; + case SPI_IOC_RD_MAX_SPEED_HZ: + retval =3D put_user(elbasr->speed_hz, (__u32 __user *)arg); + break; + + /* write requests */ + case SPI_IOC_WR_MODE: + case SPI_IOC_WR_MODE32: + if (cmd =3D=3D SPI_IOC_WR_MODE) + retval =3D get_user(tmp, (u8 __user *)arg); + else + retval =3D get_user(tmp, (u32 __user *)arg); + if (retval =3D=3D 0) { + struct spi_controller *ctlr =3D spi->controller; + u32 save =3D spi->mode; + + if (tmp & ~SPI_MODE_MASK) { + retval =3D -EINVAL; + break; + } + + if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods && + ctlr->cs_gpiods[spi->chip_select]) + tmp |=3D SPI_CS_HIGH; + + tmp |=3D spi->mode & ~SPI_MODE_MASK; + spi->mode =3D (u16)tmp; + retval =3D spi_setup(spi); + if (retval < 0) + spi->mode =3D save; + else + dev_dbg(&spi->dev, "spi mode %x\n", tmp); + } + break; + case SPI_IOC_WR_LSB_FIRST: + retval =3D get_user(tmp, (__u8 __user *)arg); + if (retval =3D=3D 0) { + u32 save =3D spi->mode; + + if (tmp) + spi->mode |=3D SPI_LSB_FIRST; + else + spi->mode &=3D ~SPI_LSB_FIRST; + retval =3D spi_setup(spi); + if (retval < 0) + spi->mode =3D save; + else + dev_dbg(&spi->dev, "%csb first\n", + tmp ? 'l' : 'm'); + } + break; + case SPI_IOC_WR_BITS_PER_WORD: + retval =3D get_user(tmp, (__u8 __user *)arg); + if (retval =3D=3D 0) { + u8 save =3D spi->bits_per_word; + + spi->bits_per_word =3D tmp; + retval =3D spi_setup(spi); + if (retval < 0) + spi->bits_per_word =3D save; + else + dev_dbg(&spi->dev, "%d bits per word\n", tmp); + } + break; + case SPI_IOC_WR_MAX_SPEED_HZ: + retval =3D get_user(tmp, (__u32 __user *)arg); + if (retval =3D=3D 0) { + u32 save =3D spi->max_speed_hz; + + spi->max_speed_hz =3D tmp; + retval =3D spi_setup(spi); + if (retval =3D=3D 0) { + elbasr->speed_hz =3D tmp; + dev_dbg(&spi->dev, "%d Hz (max)\n", + elbasr->speed_hz); + } + spi->max_speed_hz =3D save; + } + break; + + default: + /* segmented and/or full-duplex I/O request */ + /* Check message and copy into scratch area */ + ioc =3D elbasr_spi_get_ioc_message(cmd, + (struct spi_ioc_transfer __user *)arg, &n_ioc); + if (IS_ERR(ioc)) { + retval =3D PTR_ERR(ioc); + break; + } + if (!ioc) + break; /* n_ioc is also 0 */ + + /* translate to spi_message, execute */ + retval =3D elbasr_spi_message(elbasr, ioc, n_ioc); + kfree(ioc); + break; + } + + mutex_unlock(&elbasr->buf_lock); + spi_dev_put(spi); + return retval; +} + +#ifdef CONFIG_COMPAT +static long +elbasr_spi_compat_ioc_message(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct spi_ioc_transfer __user *u_ioc; + int retval =3D 0; + struct elbasr_data *elbasr; + struct spi_device *spi; + unsigned int n_ioc, n; + struct spi_ioc_transfer *ioc; + + u_ioc =3D (struct spi_ioc_transfer __user *) compat_ptr(arg); + + /* guard against device removal before, or while, + * we issue this ioctl. + */ + elbasr =3D filp->private_data; + spin_lock_irq(&elbasr->spi_lock); + spi =3D spi_dev_get(elbasr->spi); + spin_unlock_irq(&elbasr->spi_lock); + + if (spi =3D=3D NULL) + return -ESHUTDOWN; + + /* SPI_IOC_MESSAGE needs the buffer locked "normally" */ + mutex_lock(&elbasr->buf_lock); + + /* Check message and copy into scratch area */ + ioc =3D elbasr_spi_get_ioc_message(cmd, u_ioc, &n_ioc); + if (IS_ERR(ioc)) { + retval =3D PTR_ERR(ioc); + goto done; + } + if (!ioc) + goto done; /* n_ioc is also 0 */ + + /* Convert buffer pointers */ + for (n =3D 0; n < n_ioc; n++) { + ioc[n].rx_buf =3D (uintptr_t) compat_ptr(ioc[n].rx_buf); + ioc[n].tx_buf =3D (uintptr_t) compat_ptr(ioc[n].tx_buf); + } + + /* translate to spi_message, execute */ + retval =3D elbasr_spi_message(elbasr, ioc, n_ioc); + kfree(ioc); + +done: + mutex_unlock(&elbasr->buf_lock); + spi_dev_put(spi); + return retval; +} + +static long +elbasr_spi_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long= arg) +{ + if (_IOC_TYPE(cmd) =3D=3D SPI_IOC_MAGIC + && _IOC_NR(cmd) =3D=3D _IOC_NR(SPI_IOC_MESSAGE(0)) + && _IOC_DIR(cmd) =3D=3D _IOC_WRITE) + return elbasr_spi_compat_ioc_message(filp, cmd, arg); + + return elbasr_spi_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); +} +#else +#define elbasr_spi_compat_ioctl NULL +#endif /* CONFIG_COMPAT */ + +static int elbasr_spi_open(struct inode *inode, struct file *filp) +{ + struct elbasr_data *elbasr; + int status =3D -ENXIO; + + mutex_lock(&device_list_lock); + + list_for_each_entry(elbasr, &device_list, device_entry) { + if (elbasr->devt =3D=3D inode->i_rdev) { + status =3D 0; + break; + } + } + + if (status) { + pr_debug("elbasr_spi: nothing for minor %d\n", iminor(inode)); + goto err_find_dev; + } + + if (!elbasr->tx_buffer) { + elbasr->tx_buffer =3D kmalloc(bufsiz, GFP_KERNEL); + if (!elbasr->tx_buffer) { + status =3D -ENOMEM; + goto err_find_dev; + } + } + + if (!elbasr->rx_buffer) { + elbasr->rx_buffer =3D kmalloc(bufsiz, GFP_KERNEL); + if (!elbasr->rx_buffer) { + status =3D -ENOMEM; + goto err_alloc_rx_buf; + } + } + + elbasr->users++; + filp->private_data =3D elbasr; + stream_open(inode, filp); + + mutex_unlock(&device_list_lock); + return 0; + +err_alloc_rx_buf: + kfree(elbasr->tx_buffer); + elbasr->tx_buffer =3D NULL; +err_find_dev: + mutex_unlock(&device_list_lock); + return status; +} + +static int elbasr_spi_release(struct inode *inode, struct file *filp) +{ + struct elbasr_data *elbasr; + int dofree; + + mutex_lock(&device_list_lock); + elbasr =3D filp->private_data; + filp->private_data =3D NULL; + + spin_lock_irq(&elbasr->spi_lock); + /* ... after we unbound from the underlying device? */ + dofree =3D (elbasr->spi =3D=3D NULL); + spin_unlock_irq(&elbasr->spi_lock); + + /* last close? */ + elbasr->users--; + if (!elbasr->users) { + + kfree(elbasr->tx_buffer); + elbasr->tx_buffer =3D NULL; + + kfree(elbasr->rx_buffer); + elbasr->rx_buffer =3D NULL; + + if (dofree) + kfree(elbasr); + else + elbasr->speed_hz =3D elbasr->spi->max_speed_hz; + } +#ifdef CONFIG_SPI_SLAVE + if (!dofree) + spi_slave_abort(elbasr->spi); +#endif + mutex_unlock(&device_list_lock); + + return 0; +} + +static const struct file_operations elbasr_spi_fops =3D { + .owner =3D THIS_MODULE, + .write =3D elbasr_spi_write, + .read =3D elbasr_spi_read, + .unlocked_ioctl =3D elbasr_spi_ioctl, + .compat_ioctl =3D elbasr_spi_compat_ioctl, + .open =3D elbasr_spi_open, + .release =3D elbasr_spi_release, + .llseek =3D no_llseek, +}; + +static bool +elbasr_reg_readable(struct device *dev, unsigned int reg) +{ + return reg <=3D ELBASR_MAX_REG; +} + +static bool +elbasr_reg_writeable(struct device *dev, unsigned int reg) +{ + return reg <=3D ELBASR_MAX_REG; +} + +static int +elbasr_regs_read(void *ctx, u32 reg, u32 *val) +{ + struct elbasr_data *elbasr =3D dev_get_drvdata(ctx); + struct spi_message m; + struct spi_transfer t[2] =3D { { 0 } }; + int ret; + u8 txbuf[3]; + u8 rxbuf[1]; + + spi_message_init(&m); + + txbuf[0] =3D ELBASR_SPI_CMD_REGRD; + txbuf[1] =3D reg; + txbuf[2] =3D 0x0; + t[0].tx_buf =3D (u8 *)txbuf; + t[0].len =3D 3; + + rxbuf[0] =3D 0x0; + t[1].rx_buf =3D rxbuf; + t[1].len =3D 1; + + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + + ret =3D elbasr_spi_sync(elbasr, &m); + if (ret =3D=3D 4) { + // 3 Tx + 1 Rx =3D 4 + *val =3D rxbuf[0]; + return 0; + } + return -EIO; +} + +static int +elbasr_regs_write(void *ctx, u32 reg, u32 val) +{ + struct elbasr_data *elbasr =3D dev_get_drvdata(ctx); + struct spi_message m; + struct spi_transfer t[1] =3D { { 0 } }; + u8 txbuf[4]; + + spi_message_init(&m); + txbuf[0] =3D ELBASR_SPI_CMD_REGWR; + txbuf[1] =3D reg; + txbuf[2] =3D val; + txbuf[3] =3D 0; + + t[0].tx_buf =3D txbuf; + t[0].len =3D 4; + + spi_message_add_tail(&t[0], &m); + + return elbasr_spi_sync(elbasr, &m); +} + +static const struct regmap_config pensando_elbasr_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .cache_type =3D REGCACHE_NONE, + .readable_reg =3D elbasr_reg_readable, + .writeable_reg =3D elbasr_reg_writeable, + .reg_read =3D elbasr_regs_read, + .reg_write =3D elbasr_regs_write, + .max_register =3D ELBASR_MAX_REG +}; + +/* + * Setup Elba SPI access to System Resource Chip registers on CS0 + */ +static int +elbasr_regs_setup(struct spi_device *spi, struct elbasr_data *elbasr) +{ + int ret; + + spi->bits_per_word =3D 8; + spi_setup(spi); + elbasr->elbasr_regs =3D devm_regmap_init(&spi->dev, NULL, spi, + &pensando_elbasr_regmap_config); + if (IS_ERR(elbasr->elbasr_regs)) { + ret =3D PTR_ERR(elbasr->elbasr_regs); + dev_err(&spi->dev, "Failed to allocate register map: %d\n", ret); + return ret; + } + + ret =3D devm_mfd_add_devices(&spi->dev, PLATFORM_DEVID_NONE, + pensando_elbasr_subdev_info, + ARRAY_SIZE(pensando_elbasr_subdev_info), + NULL, 0, NULL); + if (ret) + dev_err(&spi->dev, "Failed to register sub-devices: %d\n", ret); + + return ret; +} + +static int elbasr_spi_probe(struct spi_device *spi) +{ + struct elbasr_data *elbasr; + unsigned long minor; + int status; + + if (spi->chip_select =3D=3D 0) { + status =3D alloc_chrdev_region(&elbasr_devt, 0, ELBASR_MAX_DEVS, + "elbasr"); + if (status < 0) + return status; + + elbasr_class =3D class_create(THIS_MODULE, "elbasr"); + if (IS_ERR(elbasr_class)) { + unregister_chrdev(MAJOR(elbasr_devt), "elbasr"); + return PTR_ERR(elbasr_class); + } + } + + /* Allocate driver data */ + elbasr =3D kzalloc(sizeof(*elbasr), GFP_KERNEL); + if (!elbasr) + return -ENOMEM; + + /* Initialize the driver data */ + elbasr->spi =3D spi; + elbasr->speed_hz =3D spi->max_speed_hz; + spin_lock_init(&elbasr->spi_lock); + mutex_init(&elbasr->buf_lock); + + INIT_LIST_HEAD(&elbasr->device_entry); + + mutex_lock(&device_list_lock); + minor =3D find_first_zero_bit(minors, ELBASR_MAX_DEVS); + if (minor < ELBASR_MAX_DEVS) { + struct device *dev; + + elbasr->devt =3D MKDEV(MAJOR(elbasr_devt), minor); + dev =3D device_create(elbasr_class, + &spi->dev, + elbasr->devt, + elbasr, + "pensr%d.%d", + spi->master->bus_num, + spi->chip_select); + + status =3D PTR_ERR_OR_ZERO(dev); + } else { + dev_dbg(&spi->dev, "no minor number available\n"); + status =3D -ENODEV; + goto minor_failed; + } + + set_bit(minor, minors); + list_add(&elbasr->device_entry, &device_list); + dev_dbg(&spi->dev, + "created device for major %d, minor %lu\n", + MAJOR(elbasr_devt), minor); + mutex_unlock(&device_list_lock); + + /* Create cdev */ + elbasr->cdev =3D cdev_alloc(); + if (!elbasr->cdev) { + dev_err(elbasr->dev, "allocation of cdev failed"); + status =3D -ENOMEM; + goto cdev_failed; + } + elbasr->cdev->owner =3D THIS_MODULE; + cdev_init(elbasr->cdev, &elbasr_spi_fops); + + status =3D cdev_add(elbasr->cdev, elbasr->devt, 1); + if (status) { + dev_err(elbasr->dev, "register of cdev failed"); + goto cdev_delete; + } + spi_set_drvdata(spi, elbasr); + + /* Add Elba reset driver sub-device */ + if (spi->chip_select =3D=3D 0) + elbasr_regs_setup(spi, elbasr); + + return 0; + +cdev_delete: + if (spi->chip_select =3D=3D 0) + cdev_del(elbasr->cdev); +cdev_failed: + if (spi->chip_select =3D=3D 0) + device_destroy(elbasr_class, elbasr->devt); +minor_failed: + kfree(elbasr); + + return status; +} + +static const struct of_device_id elbasr_spi_of_match[] =3D { + { .compatible =3D "amd,pensando-elbasr" }, + { /* sentinel */ }, +}; + +static struct spi_driver elbasr_spi_driver =3D { + .probe =3D elbasr_spi_probe, + .driver =3D { + .name =3D "elbasr", + .of_match_table =3D of_match_ptr(elbasr_spi_of_match), + }, +}; +builtin_driver(elbasr_spi_driver, spi_register_driver) diff --git a/include/linux/mfd/pensando-elbasr.h b/include/linux/mfd/pensan= do-elbasr.h new file mode 100644 index 000000000000..2b794218dca5 --- /dev/null +++ b/include/linux/mfd/pensando-elbasr.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2022 AMD Pensando + * + * Declarations for AMD Pensando Elba System Resource Chip + */ + +#ifndef __MFD_AMD_PENSANDO_ELBA_H +#define __MFD_AMD_PENSANDO_ELBA_H + +#include +#include + +#define ELBASR_REVISION_REG 0x00 +#define ELBASR_CTRL_REG 0x01 +#define ELBASR_QSFP_CTRL_REG 0x02 +#define ELBASR_INTERRUPT_ENABLE_REG 0x03 +#define ELBASR_INTERRUPT_STATUS_REG 0x04 +#define ELBASR_QSFP_LED_REG 0x05 +#define ELBASR_QSFP_LED_FREQUENCY_REG 0x0F +#define ELBASR_CTRL0_REG 0x10 +#define ELBASR_CTRL1_REG 0x11 +#define ELBASR_CTRL2_REG 0x12 +#define ELBASR_SYSTEM_LED_REG 0x15 +#define ELBASR_CORE_TEMP_REG 0x16 +#define ELBASR_HBM_TEMP_REG 0x17 +#define ELBASR_BOARD_TEMP_REG 0x18 +#define ELBASR_QSFP_PORT1_TEMP_REG 0x19 +#define ELBASR_QSFP_PORT2_TEMP_REG 0x1a +#define ELBASR_HBM_WARNING_TEMP_REG 0x1b +#define ELBASR_HBM_CRITICAL_TEMP_REG 0x1c +#define ELBASR_HBM_FATAL_TEMP_REG 0x1d +#define ELBASR_ROT_REG0_CNTL_REG 0x23 +#define ELBASR_PUF_ERROR_LIMITS_REG 0x29 +#define ELBASR_PUF_ERROR_COUNT_REG 0x2a +#define ELBASR_QSFP_PORT1_ALARM_TEMP_REG 0x34 +#define ELBASR_QSFP_PORT1_WARNING_TEMP_REG 0x35 +#define ELBASR_QSFP_PORT2_ALARM_TEMP_REG 0x36 +#define ELBASR_QSFP_PORT2_WARNING_TEMP_REG 0x37 +#define ELBASR_SYSTEM_HEALTH0_REG 0x38 +#define ELBASR_SYSTEM_HEALTH1_REG 0x39 +#define ELBASR_MAJOR_FW_VER_REG 0x3a +#define ELBASR_MINOR_FW_VER_REG 0x3b +#define ELBASR_MAINTANENCE_FW_VER_REG 0x3c +#define ELBASR_PIPELINE_FW_REG 0x3d +#define ELBASR_QSFP_PRESENT_REG 0x40 +#define ELBASR_OCP_SLOTID_REG 0x42 +#define ELBASR_OCP_SC_DATA0_REG 0x43 +#define ELBASR_OCP_SC_DATA1_REG 0x44 +#define ELBASR_ID 0x80 + +#define ELBASR_MAX_REG 0x80 +#define ELBASR_NR_RESETS 1 + +/* + * Pensando Elba System Resource MFD device private data structure + */ +struct elbasr_data { + dev_t devt; + int minor; + struct device *dev; + struct cdev *cdev; + struct spi_device *spi; + struct list_head device_entry; + spinlock_t spi_lock; + + /* TX/RX buffers are NULL unless this device is open (users > 0) */ + struct mutex buf_lock; + unsigned int users; + u8 *tx_buffer; + u8 *rx_buffer; + u32 speed_hz; + + /* System Resource Chip CS0 register access */ + struct regmap *elbasr_regs; +}; + +#endif /* __MFD_AMD_PENSANDO_ELBA_H */ --=20 2.17.1 From nobody Mon Apr 27 12:17:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBADFCCA47D for ; Mon, 13 Jun 2022 20:48:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349883AbiFMUsc (ORCPT ); Mon, 13 Jun 2022 16:48:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343763AbiFMUqi (ORCPT ); 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Mon, 13 Jun 2022 12:57:53 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 15/15] reset: elbasr: Add AMD Pensando Elba SR Reset Controller Date: Mon, 13 Jun 2022 12:56:58 -0700 Message-Id: <20220613195658.5607-16-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Brad Larson This patch adds the reset controller functionality for the AMD Pensando Elba System Resource Chip. Signed-off-by: Brad Larson --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-elbasr.c | 94 +++++++++++++++++++ .../reset/amd,pensando-elba-reset.h | 11 +++ 4 files changed, 115 insertions(+) create mode 100644 drivers/reset/reset-elbasr.c create mode 100644 include/dt-bindings/reset/amd,pensando-elba-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..13f5a8ca0f03 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,15 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. =20 +config RESET_ELBASR + tristate "Pensando Elba System Resource reset controller" + depends on MFD_PENSANDO_ELBASR || COMPILE_TEST + help + This option enables support for the external reset functions + on the Pensando Elba System Resource Chip. Reset control + of peripherals is accessed over SPI to the system resource + chip device registers using CS0. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..c0fe12b9950e 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_RESET_BCM6345) +=3D reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) +=3D reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) +=3D reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) +=3D reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_ELBASR) +=3D reset-elbasr.o obj-$(CONFIG_RESET_HSDK) +=3D reset-hsdk.o obj-$(CONFIG_RESET_IMX7) +=3D reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) +=3D reset-intel-gw.o diff --git a/drivers/reset/reset-elbasr.c b/drivers/reset/reset-elbasr.c new file mode 100644 index 000000000000..6e429cb11466 --- /dev/null +++ b/drivers/reset/reset-elbasr.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 AMD Pensando + */ + +#include +#include +#include +#include +#include +#include + +#include + +struct elbasr_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static inline struct elbasr_reset *to_elbasr_rst(struct reset_controller_d= ev *rc) +{ + return container_of(rc, struct elbasr_reset, rcdev); +} + +static inline int elbasr_reset_shift(unsigned long id) +{ + switch (id) { + case EMMC_HW_RESET: + return 6; + default: + return -EINVAL; + } +} + +static int elbasr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct elbasr_reset *elbar =3D to_elbasr_rst(rcdev); + u32 mask =3D 1 << elbasr_reset_shift(id); + + return regmap_update_bits(elbar->regmap, ELBASR_CTRL0_REG, mask, mask); +} + +static int elbasr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct elbasr_reset *elbar =3D to_elbasr_rst(rcdev); + u32 mask =3D 1 << elbasr_reset_shift(id); + + return regmap_update_bits(elbar->regmap, ELBASR_CTRL0_REG, mask, 0); +} + +static const struct reset_control_ops elbasr_reset_ops =3D { + .assert =3D elbasr_reset_assert, + .deassert =3D elbasr_reset_deassert, +}; + +static int elbasr_reset_probe(struct platform_device *pdev) +{ + struct elbasr_data *elbasr =3D dev_get_drvdata(pdev->dev.parent); + struct elbasr_reset *elbar; + int ret; + + elbar =3D devm_kzalloc(&pdev->dev, sizeof(struct elbasr_reset), + GFP_KERNEL); + if (!elbar) + return -ENOMEM; + + elbar->rcdev.owner =3D THIS_MODULE; + elbar->rcdev.nr_resets =3D ELBASR_NR_RESETS; + elbar->rcdev.ops =3D &elbasr_reset_ops; + elbar->rcdev.of_node =3D pdev->dev.of_node; + elbar->regmap =3D elbasr->elbasr_regs; + + platform_set_drvdata(pdev, elbar); + + ret =3D devm_reset_controller_register(&pdev->dev, &elbar->rcdev); + + return ret; +} + +static const struct of_device_id elba_reset_dt_match[] =3D { + { .compatible =3D "amd,pensando-elbasr-reset", }, + { /* sentinel */ }, +}; + +static struct platform_driver elbasr_reset_driver =3D { + .probe =3D elbasr_reset_probe, + .driver =3D { + .name =3D "pensando_elbasr_reset", + .of_match_table =3D elba_reset_dt_match, + }, +}; +builtin_platform_driver(elbasr_reset_driver); diff --git a/include/dt-bindings/reset/amd,pensando-elba-reset.h b/include/= dt-bindings/reset/amd,pensando-elba-reset.h new file mode 100644 index 000000000000..68d69a98e750 --- /dev/null +++ b/include/dt-bindings/reset/amd,pensando-elba-reset.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2022, AMD Pensando + */ + +#ifndef _DT_BINDINGS_RESET_AMD_PENSANDO_ELBA_RESET_H +#define _DT_BINDINGS_RESET_AMD_PENSANDO_ELBA_RESET_H + +#define EMMC_HW_RESET 0 + +#endif --=20 2.17.1