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Mon, 13 Jun 2022 05:48:02 -0700 Envelope-to: git@xilinx.com, gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, balbi@kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [10.140.6.18] (port=39406 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o0jU9-000A8B-DV; Mon, 13 Jun 2022 05:48:01 -0700 From: Piyush Mehta To: , , , , , , , CC: , , Piyush Mehta Subject: [PATCH 1/2] dt-bindings: usb: snps,dwc3: Add 'snps,enable_guctl1_resume_quirk' quirk Date: Mon, 13 Jun 2022 18:17:02 +0530 Message-ID: <20220613124703.4493-2-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613124703.4493-1-piyush.mehta@xilinx.com> References: <20220613124703.4493-1-piyush.mehta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 18d2fc54-9e87-4dea-2169-08da4d3af4db X-MS-TrafficTypeDiagnostic: DM6PR02MB5931:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2022 12:48:03.6383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18d2fc54-9e87-4dea-2169-08da4d3af4db X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT010.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5931 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new DT quirk to dwc3 core to resolved issue of CRC failed error. On the resume path, U3/U2 exit controller fails to send proper CRC checksum in CRC5 field. As result Transaction Error is generated. Enabling bit 10 of GUCTL1 will correct this problem. When this bit is set to '1', the UTMI/ULPI opmode will be changed to "normal" along with HS terminations after EOR. This option is to support certain legacy UTMI/ULPI PHYs. Signed-off-by: Piyush Mehta --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documen= tation/devicetree/bindings/usb/snps,dwc3.yaml index d41265ba8ce2..36fa87df57a9 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -234,6 +234,12 @@ properties: avoid -EPROTO errors with usbhid on some devices (Hikey 970). type: boolean =20 + snps,enable_guctl1_resume_quirk: + description: + Set if we enable quirk for fixing improper crc generation after resu= me + from suspend. + type: boolean + snps,is-utmi-l1-suspend: description: True when DWC3 asserts output signal utmi_l1_suspend_n, false when --=20 2.17.1 From nobody Sat May 2 12:39:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A287DC433EF for ; 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Mon, 13 Jun 2022 05:48:08 -0700 Envelope-to: git@xilinx.com, gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, balbi@kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [10.140.6.18] (port=39406 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o0jUF-000A8B-UT; Mon, 13 Jun 2022 05:48:08 -0700 From: Piyush Mehta To: , , , , , , , CC: , , Piyush Mehta Subject: [PATCH 2/2] usb: dwc3: core: Enable GUCTL1 bit 10 for fixing crc error after resume bug Date: Mon, 13 Jun 2022 18:17:03 +0530 Message-ID: <20220613124703.4493-3-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613124703.4493-1-piyush.mehta@xilinx.com> References: <20220613124703.4493-1-piyush.mehta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f14ed4ed-9c3a-408f-ceb1-08da4d3afcf0 X-MS-TrafficTypeDiagnostic: BN6PR02MB2625:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2022 12:48:17.2022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f14ed4ed-9c3a-408f-ceb1-08da4d3afcf0 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT027.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2625 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When configured in HOST mode, after issuing U3/L2 exit controller fails to send proper CRC checksum in CRC5 field. Because of this behavior Transaction Error is generated, resulting in reset and re-enumeration of usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this problem. When this bit is set to '1', the UTMI/ULPI opmode will be changed to "normal" along with HS terminations after EOR. This option is to support certain legacy UTMI/ULPI PHYs. Signed-off-by: Piyush Mehta --- drivers/usb/dwc3/core.c | 16 ++++++++++++++++ drivers/usb/dwc3/core.h | 6 ++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index e027c0420dc3..8afc025390d2 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1140,6 +1140,20 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } =20 + /* + * When configured in HOST mode, after issuing U3/L2 exit controller + * fails to send proper CRC checksum in CRC5 feild. Because of this + * behaviour Transaction Error is generated, resulting in reset and + * re-enumeration of usb device attached. Enabling bit 10 of GUCTL1 + * will correct this problem. This option is to support certain + * legacy ULPI PHYs. + */ + if (dwc->enable_guctl1_resume_quirk) { + reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL1); + reg |=3D DWC3_GUCTL1_RESUME_QUIRK; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL1); =20 @@ -1483,6 +1497,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) "snps,dis-del-phy-power-chg-quirk"); dwc->dis_tx_ipgap_linecheck_quirk =3D device_property_read_bool(dev, "snps,dis-tx-ipgap-linecheck-quirk"); + dwc->enable_guctl1_resume_quirk =3D device_property_read_bool(dev, + "snps,enable_guctl1_resume_quirk"); dwc->parkmode_disable_ss_quirk =3D device_property_read_bool(dev, "snps,parkmode-disable-ss-quirk"); =20 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 81c486b3941c..e386209f0e1b 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -397,6 +397,9 @@ #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 #define DWC3_GUCTL_REFCLKPER_SEL 22 =20 +/* Global User Control Register 1 */ +#define DWC3_GUCTL1_RESUME_QUIRK BIT(10) + /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) =20 @@ -1093,6 +1096,8 @@ struct dwc3_scratchpad_array { * change quirk. * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate * check during HS transmit. + * @enable_guctl1_resume_quirk: Set if we enable quirk for fixing improper= crc + * generation after resume from suspend. * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed * instances in park mode. * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk @@ -1308,6 +1313,7 @@ struct dwc3 { unsigned dis_u2_freeclk_exists_quirk:1; unsigned dis_del_phy_power_chg_quirk:1; unsigned dis_tx_ipgap_linecheck_quirk:1; + unsigned enable_guctl1_resume_quirk:1; unsigned parkmode_disable_ss_quirk:1; =20 unsigned tx_de_emphasis_quirk:1; --=20 2.17.1