From nobody Sun Sep 22 03:26:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0FCFC433EF for ; Mon, 13 Jun 2022 06:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237814AbiFMGs4 (ORCPT ); Mon, 13 Jun 2022 02:48:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233976AbiFMGsu (ORCPT ); Mon, 13 Jun 2022 02:48:50 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4D351209A; Sun, 12 Jun 2022 23:48:49 -0700 (PDT) X-UUID: 5489f771649b476e95c7a53268d2d193-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:8698b5ac-da29-43c3-8708-dcff6fa161f5,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:2a19b09,CLOUDID:c5628037-84c0-4f9a-9fbd-acd4a0e9ad0f,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 5489f771649b476e95c7a53268d2d193-20220613 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1248244147; Mon, 13 Jun 2022 14:48:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 08/12] drm/mediatek: dpi: move the yuv422_en_bit to SoC config Date: Mon, 13 Jun 2022 14:48:37 +0800 Message-ID: <20220613064841.10481-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the yuv422 en bit to SoC specific config Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 2c0e9670c209..b709b7776848 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_conf { /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -357,7 +358,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -825,6 +827,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -840,6 +843,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -854,6 +858,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -868,6 +873,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0