From nobody Sun Sep 22 03:40:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88CD8C433EF for ; Mon, 13 Jun 2022 06:49:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232745AbiFMGtW (ORCPT ); Mon, 13 Jun 2022 02:49:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237582AbiFMGsw (ORCPT ); Mon, 13 Jun 2022 02:48:52 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 773C012A82; Sun, 12 Jun 2022 23:48:51 -0700 (PDT) X-UUID: f0a6beabe7e044518249c944c6742d56-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:1b4b6ab1-4162-4969-9f9f-c6a22ede5d9a,OB:20,L OB:10,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:100 X-CID-INFO: VERSION:1.1.5,REQID:1b4b6ab1-4162-4969-9f9f-c6a22ede5d9a,OB:20,LOB :10,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:100 X-CID-META: VersionHash:2a19b09,CLOUDID:89715ac6-12ba-4305-bfdf-9aefbdc32516,C OID:bcbce69a159a,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:0,BEC:nil X-UUID: f0a6beabe7e044518249c944c6742d56-20220613 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 407175481; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 05/12] drm/mediatek: dpi: move dimension mask to SoC config Date: Mon, 13 Jun 2022 14:48:34 +0800 Message-ID: <20220613064841.10481-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the dimension mask to the SoC config Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index c1438c744120..0b6d959d878f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,8 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ + u32 dimension_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -156,30 +158,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); } =20 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } =20 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -813,6 +815,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -825,6 +828,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -847,6 +852,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0