From nobody Sun Sep 22 04:47:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1455C433EF for ; Mon, 13 Jun 2022 06:49:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238340AbiFMGtk (ORCPT ); Mon, 13 Jun 2022 02:49:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236449AbiFMGsy (ORCPT ); Mon, 13 Jun 2022 02:48:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FDE312D23; Sun, 12 Jun 2022 23:48:52 -0700 (PDT) X-UUID: 1b8b54823a7e42748fbc619270fff0af-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:0502538a-4f17-4d8e-859e-117308ab2bb5,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09,CLOUDID:8f628037-84c0-4f9a-9fbd-acd4a0e9ad0f,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 1b8b54823a7e42748fbc619270fff0af-20220613 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1492750858; Mon, 13 Jun 2022 14:48:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:44 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 10/12] drm/mediatek: dpi: Add dpintf support Date: Mon, 13 Jun 2022 14:48:39 +0800 Message-ID: <20220613064841.10481-11-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jitao shi . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 115 ++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 126 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 6b8cf648a5b5..08c8f21b4421 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -71,6 +71,7 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *pll_gate_clk; struct clk *pixel_clk; struct clk *tvd_clk; int irq; @@ -126,6 +127,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -439,6 +441,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->pll_gate_clk); + clk_disable_unprepare(dpi->tvd_clk); } =20 static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -448,10 +452,23 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount !=3D 1) return 0; =20 + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_refcount; + } + ret =3D clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; + goto err_engine; + } + + ret =3D clk_prepare_enable(dpi->pll_gate_clk); + if (ret) { + dev_err(dpi->dev, + "Failed to enable pll_gate_clk clock: %d\n", ret); + goto err_ck_cg; } =20 ret =3D clk_prepare_enable(dpi->pixel_clk); @@ -467,7 +484,11 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; =20 err_pixel: + clk_disable_unprepare(dpi->pll_gate_clk); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); +err_engine: + clk_disable_unprepare(dpi->tvd_clk); err_refcount: dpi->refcount--; return ret; @@ -498,12 +519,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, pll_rate =3D clk_get_rate(dpi->tvd_clk); =20 vm.pixelclock =3D pll_rate / factor; + + if (dpi->conf->is_dpintf) + vm.pixelclock /=3D 4; + if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -516,9 +541,21 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; + hsync.sync_width =3D vm.hsync_len; hsync.back_porch =3D vm.hback_porch; hsync.front_porch =3D vm.hfront_porch; + + /* + * For dp_intf, we need to divide everything by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->is_dpintf) { + hsync.sync_width =3D vm.hsync_len / 4; + hsync.back_porch =3D vm.hback_porch / 4; + hsync.front_porch =3D vm.hfront_porch / 4; + } + hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -560,13 +597,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 + mtk_dpi_enable(dpi); + return 0; } =20 @@ -643,7 +687,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_brid= ge *bridge, dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } @@ -688,7 +735,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); =20 - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -802,6 +849,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -811,6 +868,12 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { .c_bottom =3D 0x0010, .c_top =3D 0x0FE0, @@ -818,6 +881,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D= { .y_top =3D 0x0FE0, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpintf_limit =3D { + .c_bottom =3D 0x0000, + .c_top =3D 0xFFF, + .y_bottom =3D 0x0000, + .y_top =3D 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -883,6 +953,19 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .limit =3D &mtk_dpi_limit, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .limit =3D &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -935,6 +1018,15 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; } =20 + dpi->pll_gate_clk =3D devm_clk_get_optional(dev, "pll_gate"); + if (IS_ERR(dpi->pll_gate_clk)) { + ret =3D PTR_ERR(dpi->pll_gate_clk); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", ret); + + return ret; + } + dpi->pixel_clk =3D devm_clk_get(dev, "pixel"); if (IS_ERR(dpi->pixel_clk)) { ret =3D PTR_ERR(dpi->pixel_clk); @@ -1005,6 +1097,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dp_intf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe1662..f7f0272dbd6a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,9 +40,13 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 #define CH_SWAP_MASK (0x7 << 0) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 @@ -80,8 +84,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +99,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +229,5 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 2aab1e1eda36..5bef085714a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -427,6 +427,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_RDMA] =3D "rdma", [MTK_DISP_UFOE] =3D "ufoe", [MTK_DISP_WDMA] =3D "wdma", + [MTK_DP_INTF] =3D "dp-intf", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", }; @@ -450,6 +451,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DRM_OVL_ADAPTOR] =3D { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_a= daptor }, [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -575,6 +578,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index af9a6671f9c4..3084cc4e2830 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 78e79c8449c8..3b885ad61ac3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -788,6 +788,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dp_intf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -931,6 +933,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_OVL_ADAPTOR || comp_type =3D=3D MTK_DISP_RDMA || + comp_type =3D=3D MTK_DP_INTF || comp_type =3D=3D MTK_DPI || comp_type =3D=3D MTK_DSI) { dev_info(dev, "Adding component match for %pOF\n", --=20 2.18.0