From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69EBCC433EF for ; Mon, 13 Jun 2022 06:49:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237832AbiFMGtP (ORCPT ); Mon, 13 Jun 2022 02:49:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237474AbiFMGsw (ORCPT ); Mon, 13 Jun 2022 02:48:52 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B19D11A3B; Sun, 12 Jun 2022 23:48:50 -0700 (PDT) X-UUID: 46c2b918818d49909f5a050e277b8f2f-20220613 X-CID-P-RULE: Spam_GS6885AD X-CID-O-INFO: VERSION:1.1.5,REQID:9955839d-2032-4ab1-870b-2a52d4c70e25,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS6885AD ,ACTION:quarantine,TS:115 X-CID-INFO: VERSION:1.1.5,REQID:9955839d-2032-4ab1-870b-2a52d4c70e25,OB:0,LOB: 0,IP:0,URL:25,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:115 X-CID-META: VersionHash:2a19b09,CLOUDID:86715ac6-12ba-4305-bfdf-9aefbdc32516,C OID:bcbce69a159a,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:0,BEC:nil X-UUID: 46c2b918818d49909f5a050e277b8f2f-20220613 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 623802408; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:42 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 01/12] dt-bindings: mediatek,dpi: Add DP_INTF compatible Date: Mon, 13 Jun 2022 14:48:30 +0800 Message-ID: <20220613064841.10481-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann DP_INTF is similar to DPI but does not have the exact same feature set or register layouts. DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI. In this patch, we also do these string replacement: - s/mediatek/MediaTek/ in title. - s/Mediatek/MediaTek/ in description. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen --- .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index 77ee1b923991..ca1b48e78581 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller =20 maintainers: - CK Hu - Jitao shi =20 description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The MediaTek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data= on a + parallel output bus. =20 properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dp_intf =20 reg: maxItems: 1 @@ -36,12 +37,14 @@ properties: - description: Pixel Clock - description: Engine Clock - description: DPI PLL + - description: Clock gate for PLL =20 clock-names: items: - const: pixel - const: engine - const: pll + - const: pll_gate =20 pinctrl-0: true pinctrl-1: true @@ -55,7 +58,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of= an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip. =20 required: - compatible --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CAE2C433EF for ; Mon, 13 Jun 2022 06:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238422AbiFMGtu (ORCPT ); Mon, 13 Jun 2022 02:49:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237694AbiFMGsz (ORCPT ); Mon, 13 Jun 2022 02:48:55 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38CC613F1E; Sun, 12 Jun 2022 23:48:53 -0700 (PDT) X-UUID: bf36bd13de4840e3a0fe3502c4b1b909-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:95091e13-a609-4911-9058-eea9af0f258b,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:95091e13-a609-4911-9058-eea9af0f258b,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:88715ac6-12ba-4305-bfdf-9aefbdc32516,C OID:bcbce69a159a,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: bf36bd13de4840e3a0fe3502c4b1b909-20220613 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 658693792; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:42 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 02/12] drm/mediatek: dpi: move dpi limits to SoC config Date: Mon, 13 Jun 2022 14:48:31 +0800 Message-ID: <20220613064841.10481-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the dpi limits to the SoC specific config. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index e61cd67b978f..ce8c5eefe5f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + const struct mtk_dpi_yc_limit *limit; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi= , u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } =20 -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit =3D dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); =20 - limit.c_bottom =3D 0x0010; - limit.c_top =3D 0x0FE0; - limit.y_bottom =3D 0x0010; - limit.y_top =3D 0x0FE0; - dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol =3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); =20 - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { + .c_bottom =3D 0x0010, + .c_top =3D 0x0FE0, + .y_bottom =3D 0x0010, + .y_top =3D 0x0FE0, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt2701_conf =3D { @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8183_conf =3D { @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8192_conf =3D { @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static int mtk_dpi_probe(struct platform_device *pdev) --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 377D7C43334 for ; Mon, 13 Jun 2022 06:49:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238439AbiFMGt4 (ORCPT ); Mon, 13 Jun 2022 02:49:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237720AbiFMGsz (ORCPT ); Mon, 13 Jun 2022 02:48:55 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ED931581B; Sun, 12 Jun 2022 23:48:53 -0700 (PDT) X-UUID: 42f531b43e3a4355b674f5f6bbd5cdef-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:353ba3d0-a0e9-4b12-ac16-fdbf83731228,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09,CLOUDID:87715ac6-12ba-4305-bfdf-9aefbdc32516,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 42f531b43e3a4355b674f5f6bbd5cdef-20220613 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 755631472; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 03/12] drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config Date: Mon, 13 Jun 2022 14:48:32 +0800 Message-ID: <20220613064841.10481-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Dp_intf does not support CK/DE polarity because the polarity information is not used for eDP and DP while dp_intf is only for eDP and DP. Therefore, we add a bit of flexibility to support SoCs without CK/DE pol support. Signed-off-by: Guillaume Ranquet [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index ce8c5eefe5f1..15218c1e8c11 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -211,13 +212,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask; =20 - pol =3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL)= | + mask =3D HSYNC_POL | VSYNC_POL; + pol =3D (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_PO= L) | (dpi_pol->vsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |=3D CK_POL | DE_POL; + pol |=3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); } =20 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -799,6 +807,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -809,6 +818,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -818,6 +828,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -827,6 +838,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E885DC43334 for ; Mon, 13 Jun 2022 06:49:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235485AbiFMGt3 (ORCPT ); Mon, 13 Jun 2022 02:49:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237551AbiFMGsw (ORCPT ); Mon, 13 Jun 2022 02:48:52 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99F9F12A86; Sun, 12 Jun 2022 23:48:51 -0700 (PDT) X-UUID: 6153f37f00554545860bb19a2fbb724b-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:95579b9f-f73c-4432-a9b7-49a87fbc990e,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:25,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:20 X-CID-META: VersionHash:2a19b09,CLOUDID:ba715ac6-12ba-4305-bfdf-9aefbdc32516,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:5,IP:nil,URL:0,File:nil, QS:0,BEC:nil X-UUID: 6153f37f00554545860bb19a2fbb724b-20220613 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 85491784; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 04/12] drm/mediatek: dpi: implement a swap_input toggle in SoC config Date: Mon, 13 Jun 2022 14:48:33 +0800 Message-ID: <20220613064841.10481-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet The hardware design of dp_intf does not support input swap, so we add a bit of flexibility to support SoCs without swap_input support. Signed-off-by: Guillaume Ranquet [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 15218c1e8c11..c1438c744120 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -378,18 +379,21 @@ static void mtk_dpi_config_color_format(struct mtk_dp= i *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -808,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -819,6 +824,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +835,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +846,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88CD8C433EF for ; Mon, 13 Jun 2022 06:49:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232745AbiFMGtW (ORCPT ); Mon, 13 Jun 2022 02:49:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237582AbiFMGsw (ORCPT ); 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Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 05/12] drm/mediatek: dpi: move dimension mask to SoC config Date: Mon, 13 Jun 2022 14:48:34 +0800 Message-ID: <20220613064841.10481-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the dimension mask to the SoC config Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index c1438c744120..0b6d959d878f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,8 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ + u32 dimension_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -156,30 +158,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); } =20 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } =20 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -813,6 +815,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -825,6 +828,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -847,6 +852,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; 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Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 06/12] drm/mediatek: dpi: move hvsize_mask to SoC config Date: Mon, 13 Jun 2022 14:48:35 +0800 Message-ID: <20220613064841.10481-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the hvsize mask to SoC specific config. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 0b6d959d878f..afd81ae307da 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_conf { bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; + /* HSIZE and VSIZE mask (no shift) */ + u32 hvsize_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -243,8 +245,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *d= pi, bool inter) =20 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 hei= ght) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); } =20 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -816,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -841,6 +847,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +860,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CEA7CCA47B for ; Mon, 13 Jun 2022 06:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237784AbiFMGtK (ORCPT ); Mon, 13 Jun 2022 02:49:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237283AbiFMGsw (ORCPT ); Mon, 13 Jun 2022 02:48:52 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B5A41209F; Sun, 12 Jun 2022 23:48:50 -0700 (PDT) X-UUID: d0a8895a24524ce6a4eaaa89477d3eb1-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:18d49c5c-fc2c-4f75-9d42-9be9ac5b61bb,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:bb715ac6-12ba-4305-bfdf-9aefbdc32516,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: d0a8895a24524ce6a4eaaa89477d3eb1-20220613 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1405203782; Mon, 13 Jun 2022 14:48:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 07/12] drm/mediatek: dpi: move swap_shift to SoC config Date: Mon, 13 Jun 2022 14:48:36 +0800 Message-ID: <20220613064841.10481-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the swap shift value to SoC specific config. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index afd81ae307da..2c0e9670c209 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_conf { u32 dimension_mask; /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; + u32 channel_swap_shift; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -349,7 +350,9 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, break; } =20 - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, + val << dpi->conf->channel_swap_shift, + CH_SWAP_MASK << dpi->conf->channel_swap_shift); } =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -821,6 +824,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -835,6 +839,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -848,6 +853,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -861,6 +867,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0FCFC433EF for ; Mon, 13 Jun 2022 06:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237814AbiFMGs4 (ORCPT ); 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Mon, 13 Jun 2022 14:48:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 08/12] drm/mediatek: dpi: move the yuv422_en_bit to SoC config Date: Mon, 13 Jun 2022 14:48:37 +0800 Message-ID: <20220613064841.10481-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the yuv422 en bit to SoC specific config Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 2c0e9670c209..b709b7776848 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_conf { /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -357,7 +358,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -825,6 +827,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -840,6 +843,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -854,6 +858,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -868,6 +873,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA313CCA47B for ; Mon, 13 Jun 2022 06:49:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237947AbiFMGtB (ORCPT ); Mon, 13 Jun 2022 02:49:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237527AbiFMGsw (ORCPT ); Mon, 13 Jun 2022 02:48:52 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E138112774; Sun, 12 Jun 2022 23:48:50 -0700 (PDT) X-UUID: 428d7ab21d214bfa9d57b09635188dc0-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:38f08c3e-46d6-4d92-8419-0414511f76bf,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:c4628037-84c0-4f9a-9fbd-acd4a0e9ad0f,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 428d7ab21d214bfa9d57b09635188dc0-20220613 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 714407134; Mon, 13 Jun 2022 14:48:46 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 13 Jun 2022 14:48:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:43 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v11 09/12] drm/mediatek: dpi: move the csc_enable bit to SoC config Date: Mon, 13 Jun 2022 14:48:38 +0800 Message-ID: <20220613064841.10481-10-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add flexibility by moving the csc_enable bit to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index b709b7776848..6b8cf648a5b5 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -133,6 +133,7 @@ struct mtk_dpi_conf { u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; + u32 csc_enable_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -364,7 +365,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi= *dpi, bool enable) =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); } =20 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -828,6 +830,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -844,6 +847,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -859,6 +863,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -874,6 +879,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1455C433EF for ; Mon, 13 Jun 2022 06:49:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238340AbiFMGtk (ORCPT ); Mon, 13 Jun 2022 02:49:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236449AbiFMGsy (ORCPT ); Mon, 13 Jun 2022 02:48:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FDE312D23; Sun, 12 Jun 2022 23:48:52 -0700 (PDT) X-UUID: 1b8b54823a7e42748fbc619270fff0af-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:0502538a-4f17-4d8e-859e-117308ab2bb5,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09,CLOUDID:8f628037-84c0-4f9a-9fbd-acd4a0e9ad0f,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 1b8b54823a7e42748fbc619270fff0af-20220613 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1492750858; Mon, 13 Jun 2022 14:48:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:44 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 10/12] drm/mediatek: dpi: Add dpintf support Date: Mon, 13 Jun 2022 14:48:39 +0800 Message-ID: <20220613064841.10481-11-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jitao shi . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 115 ++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 126 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 6b8cf648a5b5..08c8f21b4421 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -71,6 +71,7 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *pll_gate_clk; struct clk *pixel_clk; struct clk *tvd_clk; int irq; @@ -126,6 +127,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -439,6 +441,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->pll_gate_clk); + clk_disable_unprepare(dpi->tvd_clk); } =20 static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -448,10 +452,23 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount !=3D 1) return 0; =20 + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_refcount; + } + ret =3D clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; + goto err_engine; + } + + ret =3D clk_prepare_enable(dpi->pll_gate_clk); + if (ret) { + dev_err(dpi->dev, + "Failed to enable pll_gate_clk clock: %d\n", ret); + goto err_ck_cg; } =20 ret =3D clk_prepare_enable(dpi->pixel_clk); @@ -467,7 +484,11 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; =20 err_pixel: + clk_disable_unprepare(dpi->pll_gate_clk); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); +err_engine: + clk_disable_unprepare(dpi->tvd_clk); err_refcount: dpi->refcount--; return ret; @@ -498,12 +519,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, pll_rate =3D clk_get_rate(dpi->tvd_clk); =20 vm.pixelclock =3D pll_rate / factor; + + if (dpi->conf->is_dpintf) + vm.pixelclock /=3D 4; + if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -516,9 +541,21 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; + hsync.sync_width =3D vm.hsync_len; hsync.back_porch =3D vm.hback_porch; hsync.front_porch =3D vm.hfront_porch; + + /* + * For dp_intf, we need to divide everything by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->is_dpintf) { + hsync.sync_width =3D vm.hsync_len / 4; + hsync.back_porch =3D vm.hback_porch / 4; + hsync.front_porch =3D vm.hfront_porch / 4; + } + hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -560,13 +597,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 + mtk_dpi_enable(dpi); + return 0; } =20 @@ -643,7 +687,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_brid= ge *bridge, dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } @@ -688,7 +735,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); =20 - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -802,6 +849,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -811,6 +868,12 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { .c_bottom =3D 0x0010, .c_top =3D 0x0FE0, @@ -818,6 +881,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D= { .y_top =3D 0x0FE0, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpintf_limit =3D { + .c_bottom =3D 0x0000, + .c_top =3D 0xFFF, + .y_bottom =3D 0x0000, + .y_top =3D 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -883,6 +953,19 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .limit =3D &mtk_dpi_limit, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .limit =3D &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -935,6 +1018,15 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; } =20 + dpi->pll_gate_clk =3D devm_clk_get_optional(dev, "pll_gate"); + if (IS_ERR(dpi->pll_gate_clk)) { + ret =3D PTR_ERR(dpi->pll_gate_clk); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", ret); + + return ret; + } + dpi->pixel_clk =3D devm_clk_get(dev, "pixel"); if (IS_ERR(dpi->pixel_clk)) { ret =3D PTR_ERR(dpi->pixel_clk); @@ -1005,6 +1097,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dp_intf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe1662..f7f0272dbd6a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,9 +40,13 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 #define CH_SWAP_MASK (0x7 << 0) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 @@ -80,8 +84,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +99,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +229,5 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 2aab1e1eda36..5bef085714a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -427,6 +427,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_RDMA] =3D "rdma", [MTK_DISP_UFOE] =3D "ufoe", [MTK_DISP_WDMA] =3D "wdma", + [MTK_DP_INTF] =3D "dp-intf", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", }; @@ -450,6 +451,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DRM_OVL_ADAPTOR] =3D { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_a= daptor }, [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -575,6 +578,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index af9a6671f9c4..3084cc4e2830 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 78e79c8449c8..3b885ad61ac3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -788,6 +788,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dp_intf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -931,6 +933,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_OVL_ADAPTOR || comp_type =3D=3D MTK_DISP_RDMA || + comp_type =3D=3D MTK_DP_INTF || comp_type =3D=3D MTK_DPI || comp_type =3D=3D MTK_DSI) { dev_info(dev, "Adding component match for %pOF\n", --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8302CC433EF for ; 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Mon, 13 Jun 2022 14:48:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:44 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 11/12] drm/mediatek: dpi: Only enable dpi after the bridge is enabled Date: Mon, 13 Jun 2022 14:48:40 +0800 Message-ID: <20220613064841.10481-12-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Enabling the dpi too early causes glitches on screen. Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 08c8f21b4421..9668bd5dd14a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -480,7 +480,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); =20 - mtk_dpi_enable(dpi); return 0; =20 err_pixel: @@ -726,6 +725,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *br= idge) =20 mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode); + mtk_dpi_enable(dpi); } =20 static enum drm_mode_status --=20 2.18.0 From nobody Sun Sep 22 01:29:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AAEFC43334 for ; Mon, 13 Jun 2022 06:50:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238479AbiFMGuA (ORCPT ); Mon, 13 Jun 2022 02:50:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237803AbiFMGs4 (ORCPT ); Mon, 13 Jun 2022 02:48:56 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91AF215827; Sun, 12 Jun 2022 23:48:54 -0700 (PDT) X-UUID: 852b16fdbd084e3fa7b56955cdeaf3a3-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:e1b1ec7c-91a3-4f45-aac3-02461839e6e2,OB:20,L OB:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:e1b1ec7c-91a3-4f45-aac3-02461839e6e2,OB:20,LOB :0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:11725ac6-12ba-4305-bfdf-9aefbdc32516,C OID:ef7ad5cd4226,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 852b16fdbd084e3fa7b56955cdeaf3a3-20220613 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1925287180; Mon, 13 Jun 2022 14:48:46 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 13 Jun 2022 14:48:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jun 2022 14:48:44 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v11 12/12] drm/mediatek: dpi: Add matrix_sel helper Date: Mon, 13 Jun 2022 14:48:41 +0800 Message-ID: <20220613064841.10481-13-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220613064841.10481-1-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guillaume Ranquet Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format. Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 9668bd5dd14a..dc355a512963 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -387,6 +387,25 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi= *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } =20 +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, enum mtk_dpi_out_color= _format format) +{ + u32 matrix_sel =3D 0; + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <=3D 720) + matrix_sel =3D 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -394,6 +413,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -401,6 +421,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index f7f0272dbd6a..96c117202d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -230,4 +230,7 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) =20 +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0) + #endif /* __MTK_DPI_REGS_H */ --=20 2.18.0