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Peter Anvin" , "Yazen Ghannam" , Smita Koralahalli Subject: [PATCH v5] x86/mce: Check for writes ignored in MCA_STATUS register Date: Fri, 10 Jun 2022 19:25:15 +0000 Message-ID: <20220610192515.98540-1-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 421965ae-3d90-4652-2bd2-08da4b16fa86 X-MS-TrafficTypeDiagnostic: BL0PR12MB4737:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VshlL2BvHesT5ZcK5qATEFu9/WT1SIsXzut5t5Bz6PDmX9QFiFZ41e0/miYckrK/ITqytgsOWJ4tpFPHu/9JBXN2spnHB0sQo5dGGYcJL0qUbYVC+GQ6t6CrigVdRX2xHJ5d+Mav/NbRG574Z8stQYC0JZE3Ak3XjBpcml35dEFrM1EMFulYj/JXAFvSxD0b9kwSQNbTLfFNeJPUAf+1X5GgT0uZqr2qWUH+sujb2thawRt/o6AilgmsDERgcU5JGke/55cs03F6Tg3N+GIsUDe99M+nTOJJbxUBPGshnoU2/NFjZPMyElauIBiG9xv5aX7BKKiKh+6f+WVands9V+Twqmj/fYdVEGP1gBSaQYOC73slFBKgiWCc7XaYWZkExX4NOhop1YDdU0WwlCQMEWpNxAnk7lQ/oDUagM7oHG11EJxwgH+IGNqCFcLSGmYlaPhFc7Zi12Zljd6aumIM6dMQn5Fy4Mk4fToOFrN0UAejkMBljsNMILnEgbkMH/+tyt0cZsa7sEDjBwkWm0TrLsyg1dxA+KAoq/Q+PB4Cja2FN0hdD8aQCkk0QijNkVFC70mDnEBiF0lKjU20kunhtX0cAXxP1RpzJiIt2bkNCCzBHLQyUU7qQMTgoxxStJWRMXEZuxa1T+7SwHG3lD73vYyeigVTUV+ICQOiKvYmeBXij51NyJsUTU0I4SwiKwLPNPK9I5+fQKk7uqFxojEp0exFjO/P4A323x5dFYo+e7UlnLB0sEmphPToH1rt9hw6XZSSodkf1WNpqTmFzj/nVJqJEpqvlThdPwv5d7WPFM30dotEGScYd2ixq17iysp6XedYK5sthKudxOw7rMtW6vLR6MLxEy4hvhVbnfRDskI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(40470700004)(36840700001)(46966006)(36756003)(356005)(82310400005)(70586007)(70206006)(8676002)(316002)(5660300002)(54906003)(81166007)(110136005)(4326008)(36860700001)(2906002)(7696005)(6666004)(26005)(336012)(86362001)(186003)(1076003)(8936002)(83380400001)(47076005)(16526019)(40460700003)(508600001)(966005)(426003)(2616005)(21314003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2022 19:25:28.8932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 421965ae-3d90-4652-2bd2-08da4b16fa86 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4737 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to Section 2.1.16.3 under HWCR[McStatusWrEn] in "PPR for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021", the status register may sometimes enforce write ignored behavior independent of the value of HWCR[McStatusWrEn] depending on the platform settings. Hence, evaluate for writes ignored for MCA_STATUS to determine if hardware error injection is possible. Perform this evaluation early during module init and store the result in the static "hw_injection_possible" variable. Query this variable for subsequent error injections and limit checking for MCA_STATUS only once on driver init. Avoid exporting mce_flags into modules and check for smca feature from 'X86_FEATURE_SMCA' flag directly. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Smita Koralahalli --- Link: https://lkml.kernel.org/r/20220214233640.70510-2-Smita.KoralahalliChannabas= appa@amd.com v2: msr_ops -> mca_msr_reg(). simulation -> injection. pr_info() -> pr_err(). Aligned on ",". v3: Removed "x86/mce: Use mca_msr_reg() in prepare_msrs()" patch. and made changes on the existing MCx_{STATUS, ADDR, MISC} macros. v4: Simplified the code by just checking for writes ignored behavior in MCA_STATUS register. Introduced prepare_mca_status() and performed writes ignored checks inside the function. Rephrased error message. v5: Evaluated for writes ignored early and only once during module init. Introduced "hw_injection_possible" variable to store the result of writes ignored behavior of MCA_STATUS. This variable is checked before performing subsequent hw error injections. --- arch/x86/kernel/cpu/mce/inject.c | 50 +++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mce/internal.h | 2 +- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 5fbd7ffb3233..ac5582691530 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -33,6 +33,8 @@ =20 #include "internal.h" =20 +static bool hw_injection_possible =3D true; + /* * Collect all the MCi_XXX settings */ @@ -339,6 +341,8 @@ static int __set_inj(const char *buf) =20 for (i =3D 0; i < N_INJ_TYPES; i++) { if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) { + if (i > SW_INJ && !hw_injection_possible) + continue; inj_type =3D i; return 0; } @@ -376,7 +380,11 @@ static ssize_t flags_write(struct file *filp, const ch= ar __user *ubuf, =20 err =3D __set_inj(__buf); if (err) { - pr_err("%s: Invalid flags value: %s\n", __func__, __buf); + pr_err("%s: Invalid flags value: %s: %s\n", __func__, + (!hw_injection_possible + ? " (SW-only injection possible on this platform)" + : ""), + __buf); return err; } =20 @@ -501,6 +509,8 @@ static void do_inject(void) unsigned int cpu =3D i_mce.extcpu; u8 b =3D i_mce.bank; =20 + pr_info("Using '%s' error injection method", flags_options[inj_type]); + i_mce.tsc =3D rdtsc_ordered(); =20 i_mce.status |=3D MCI_STATUS_VAL; @@ -717,11 +727,49 @@ static void __init debugfs_init(void) &i_mce, dfs_fls[i].fops); } =20 +static void check_hw_inj_possible(void) +{ + u8 bank; + + /* + * This behavior exists only on SMCA systems though its not directly + * related to SMCA. + */ + if (!cpu_feature_enabled(X86_FEATURE_SMCA)) + return; + + get_cpu(); + + for (bank =3D 0; bank < MAX_NR_BANKS; ++bank) { + u64 status =3D MCI_STATUS_VAL, ipid; + + rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid); + + if (!ipid) + continue; + + wrmsrl(mca_msr_reg(bank, MCA_STATUS), status); + rdmsrl(mca_msr_reg(bank, MCA_STATUS), status); + + if (!status) { + hw_injection_possible =3D false; + pr_warn("Platform does not allow error injection, try using APEI EINJ i= nstead.\n"); + } + + /* Exit after the check for first available MCA bank */ + break; + } + + put_cpu(); +} + static int __init inject_init(void) { if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL)) return -ENOMEM; =20 + check_hw_inj_possible(); + debugfs_init(); =20 register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 4ae0e603f7fa..7e03f5b7f6bd 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -211,7 +211,7 @@ noinstr u64 mce_rdmsrl(u32 msr); =20 static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) { - if (mce_flags.smca) { + if (cpu_feature_enabled(X86_FEATURE_SMCA)) { switch (reg) { case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); --=20 2.17.1