From nobody Sun Sep 22 01:34:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA6E9C433EF for ; Thu, 9 Jun 2022 10:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242937AbiFIKlH (ORCPT ); Thu, 9 Jun 2022 06:41:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243394AbiFIKkp (ORCPT ); Thu, 9 Jun 2022 06:40:45 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4515A35DB1A; Thu, 9 Jun 2022 03:40:12 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 20A5266017C7; Thu, 9 Jun 2022 11:40:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654771211; bh=XsdKca6uJqVHP/fpe/JGNltV33I9zIbmdBk8VfIBHU4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=grhQQ7l0fxS0nE/QuH0wy0PvUmj2vFgdYu7M8vFf3deBIEaJt7TGwQt4JHSSlJkey KW7H1VFqaIh+dCG9wyw9x2tMiAmHhyG5jITZDY88uOT9TKXI1nSpdB4W5yzwHMeuq5 pXfBARcaRcd/vE1NRxU8Aru+DV7A10v5cWgRT4QhrTcgb4iDl4WLYRoBU4dcmXkxTX ENCk8OYQLp1VkSiPgp0IQSFcsWFqbODDdYe8Q5n3JwHRZE36OVnuIXJvfjwfwDSGSL LYdskul928uHc6cD20stZsm4zZvq9N07xMW0Oi/jepPqxvZuCyj3LL+obrCZEPwwjV 0bZw1J288bbgA== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, AngeloGioacchino Del Regno Subject: [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 Date: Thu, 9 Jun 2022 12:40:00 +0200 Message-Id: <20220609104001.97753-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609104001.97753-1-angelogioacchino.delregno@collabora.com> References: <20220609104001.97753-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding support for MT6795, add a new flag named TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat checks there in the future. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0ea0848581e9..8611cf8e4bd5 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -140,6 +140,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) /* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ #define HAS_PERI_IOMMU1_REG BIT(17) +#define TF_PORT_TO_ADDR_MT8173 BIT(18) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -960,7 +961,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_dat= a *data, unsigned int ban * Global control settings are in bank0. May re-init these global registe= rs * since no sure if there is bank0 consumers. */ - if (data->plat_data->m4u_plat =3D=3D M4U_MT8173) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { regval =3D F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; } else { @@ -1437,7 +1438,8 @@ static const struct mtk_iommu_plat_data mt8167_data = =3D { static const struct mtk_iommu_plat_data mt8173_data =3D { .m4u_plat =3D M4U_MT8173, .flags =3D HAS_4GB_MODE | HAS_BCLK | RESET_AXI | - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN1, .banks_num =3D 1, .banks_enable =3D {true}, --=20 2.35.1