From nobody Sat Sep 21 23:34:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E116CCA47D for ; Thu, 9 Jun 2022 10:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243013AbiFIKI3 (ORCPT ); Thu, 9 Jun 2022 06:08:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234965AbiFIKIP (ORCPT ); Thu, 9 Jun 2022 06:08:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 421A162E2; Thu, 9 Jun 2022 03:08:10 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5839A66017C7; Thu, 9 Jun 2022 11:08:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654769289; bh=HGU3F/fPzfALJBmgYOFXFZVVSN1REtbO7A5z7wOIIZ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4zoEc3kuavp5jU+vdoOQdnw6/dPK/kfiEiqQx4QU5cgAXifm+z3TfYRX1Siej/qw tXs4c40wF8cUIsiQpPmsEtxtfuaV/t1dZKHL9IboZ/WtZJQ/HB9YZ3z4Qfj6wDQJvl sz2PC7QAC/m09CBmCzffnGWDHDcdIb5wE7r0ifWgu5l0tr49uboZWzILqc6pjeur9N D/9YT2Sz3Onn0OQ/ZfYz3Ggc5nSG2ZMhQVUP97vtQiLMZHywzrM9lR1rJzbKoVJNLE Vm86cY1OvO3TzLOkDmKB3joUZW2hOLDb5D+M1ajkmmMKxternyYnK1yWVtJFtz/VkZ Rb33r5B+uwMdQ== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v3 1/6] dt-bindings: iommu: mediatek: Add mediatek,infracfg phandle Date: Thu, 9 Jun 2022 12:07:57 +0200 Message-Id: <20220609100802.54513-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> References: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add property "mediatek,infracfg" to let the mtk_iommu driver retrieve a phandle to the infracfg syscon instead of performing a per-soc compatible lookup in the entire devicetree and set it as a required property for MT2712 and MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/iommu/mediatek,iommu.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/= Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 2ae3bbad7f1a..4142a568b293 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -101,6 +101,10 @@ properties: items: - const: bclk =20 + mediatek,infracfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the mediatek infracfg syscon + mediatek,larbs: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 @@ -167,6 +171,18 @@ allOf: required: - power-domains =20 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2712-m4u + - mediatek,mt8173-m4u + + then: + required: + - mediatek,infracfg + - if: # The IOMMUs don't have larbs. not: properties: --=20 2.35.1 From nobody Sat Sep 21 23:34:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DEA6CCA480 for ; Thu, 9 Jun 2022 10:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242982AbiFIKI1 (ORCPT ); Thu, 9 Jun 2022 06:08:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234415AbiFIKIP (ORCPT ); Thu, 9 Jun 2022 06:08:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41490624A; Thu, 9 Jun 2022 03:08:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3686C66017C8; Thu, 9 Jun 2022 11:08:09 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654769289; bh=7NH0zCAnj6DTlLIJ/fPDdoJP+dAMJTzS1hu071yicYQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GyKAfIQh74M6E0tS7YI+WWQ8i656pqE/dLB+PGHHNhMJCyezDxe/wNPQTf6/Z1Lb6 2nOCQ8aQAScMRdbalLEvlepTF4pmn+kYGgE+z9wo7GaA1j7ZTgfUZtTUCDRjtnd1ma xiPp1BQ9iM8iXzXh/qZy65LX8UXNXukkqgoeWsUofAN/8jwlGCSI1KOD9UxVRxcE2V +HpUPseyFCLwBBIAT5VfImJBx9zVRN6VanQ1fqtE0c3i7pW5Q//ovmvcJmuP8UGoNC UcoNwTeiCV2evdJxw8041q5e12xpGLvwPgZTVi7//4c2+RnClJy3RHqvcr0kYmoh4h 5MX9E1q6M/9zw== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v3 2/6] iommu: mtk_iommu: Lookup phandle to retrieve syscon to infracfg Date: Thu, 9 Jun 2022 12:07:58 +0200 Message-Id: <20220609100802.54513-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> References: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver will get support for more SoCs and the list of infracfg compatibles is expected to grow: in order to prevent getting this situation out of control and see a long list of compatible strings, add support to retrieve a handle to infracfg's regmap through a new "mediatek,infracfg" phandle. In order to keep retrocompatibility with older devicetrees, the old way is kept in place. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Reviewed-by: Miles Chen =20 Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index bb9dd92c9898..90685946fcbe 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1140,22 +1140,32 @@ static int mtk_iommu_probe(struct platform_device *= pdev) data->protect_base =3D ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); =20 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { - switch (data->plat_data->m4u_plat) { - case M4U_MT2712: - p =3D "mediatek,mt2712-infracfg"; - break; - case M4U_MT8173: - p =3D "mediatek,mt8173-infracfg"; - break; - default: - p =3D NULL; + infracfg =3D syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,inf= racfg"); + if (IS_ERR(infracfg)) { + /* + * Legacy devicetrees will not specify a phandle to + * mediatek,infracfg: in that case, we use the older + * way to retrieve a syscon to infra. + * + * This is for retrocompatibility purposes only, hence + * no more compatibles shall be added to this. + */ + switch (data->plat_data->m4u_plat) { + case M4U_MT2712: + p =3D "mediatek,mt2712-infracfg"; + break; + case M4U_MT8173: + p =3D "mediatek,mt8173-infracfg"; + break; + default: + p =3D NULL; + } + + infracfg =3D syscon_regmap_lookup_by_compatible(p); + if (IS_ERR(infracfg)) + return PTR_ERR(infracfg); } =20 - infracfg =3D syscon_regmap_lookup_by_compatible(p); - - if (IS_ERR(infracfg)) - return PTR_ERR(infracfg); - ret =3D regmap_read(infracfg, REG_INFRA_MISC, &val); if (ret) return ret; --=20 2.35.1 From nobody Sat Sep 21 23:34:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59978CCA47F for ; Thu, 9 Jun 2022 10:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242933AbiFIKIV (ORCPT ); Thu, 9 Jun 2022 06:08:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235153AbiFIKIP (ORCPT ); Thu, 9 Jun 2022 06:08:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0310363CF; Thu, 9 Jun 2022 03:08:12 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1688E66017C9; Thu, 9 Jun 2022 11:08:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654769290; bh=+xTyEZ131wWMOMNxSY33aVPVZoxl3tqtIBcQv4cQtYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jQ0LgA4FXh4NTGt0fqXLzSjxIk35Va6Sa6B0gJWMushLSqFJg+Beh7Vh63EhvpMo4 fuXid8sXiUvv3dDi3aEtR8bq2XpIxEb/JrYdMrQvnUebHVs7U78QSk+eJ3U714kw2Q F1BFsAYbMp+RW5xnnwEDa1RJEiNeFaU172kpfCQykCEeeUuMzFgjPH/44RgW057BBw Qo2hcx51zaqJKORLQEDJG2y5Dyf/mSeWazI1F8DhTXw+AfxpfWFXQDe5jia4ERIhhj Hi1PPJPHHw9wBPd+BXVki8npxPB8Dp+TL0dpmqz6Fx9fVp7tv2/mr9o2jSlpBPgmVt Lo5bOD9XU5+AA== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v3 3/6] arm64: dts: mediatek: mt8173: Add mediatek,infracfg phandle for IOMMU Date: Thu, 9 Jun 2022 12:07:59 +0200 Message-Id: <20220609100802.54513-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> References: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The IOMMU driver now looks for the "mediatek,infracfg" phandle as a new way to retrieve a syscon to that: even though the old way is retained, it has been deprecated and the driver will write a message in kmsg advertising to use the phandle way instead. For this reason, assign the right phandle to mediatek,infracfg in the iommu node. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen =20 --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 40d7b47fc52e..825a3c670373 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -588,6 +588,7 @@ iommu: iommu@10205000 { interrupts =3D ; clocks =3D <&infracfg CLK_INFRA_M4U>; clock-names =3D "bclk"; + mediatek,infracfg =3D <&infracfg>; mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>, <&larb3>, <&larb4>, <&larb5>; #iommu-cells =3D <1>; --=20 2.35.1 From nobody Sat Sep 21 23:34:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 932BBCCA482 for ; Thu, 9 Jun 2022 10:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243035AbiFIKIb (ORCPT ); Thu, 9 Jun 2022 06:08:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235229AbiFIKIP (ORCPT ); Thu, 9 Jun 2022 06:08:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0320963D7; Thu, 9 Jun 2022 03:08:12 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E996F66017CB; Thu, 9 Jun 2022 11:08:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654769291; bh=CgNYAOaieQLCVcum8jYWv0FFa/H0G4zrGj0sGsj1tXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K4v9L0EwV6ZsghUeg0tMGf6fhREdFwlSxn5OIdaxyAuxixlQ4vc1mzjV5mAiMi/0S Y3WXyYPd5tu9/AhpTbDVMRDqtHIkAD9u8XCJtHJ0M4R5Vx41+7VZI5lkjfagzYkXBf FYA8CDWVDbT13PoUBpcVoVXTi+lypmCRFqqQzicyUgtTCOBYsHDd19KU9nWfupPSKp NnML1F+R9cf9+URrZzLDaTkg0aUKxsjzbtMz3Dfe2MKnICQY8o+9L/126eozTriZ3a 5dqcZDmn1GD8GaG/PgCqGYCcEi/AJlcZWRmdRQP4mBPofkwleHAMeQi0NjgSWnBXRl W2OGPbpFxLcbQ== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v3 4/6] arm64: dts: mediatek: mt2712e: Add mediatek,infracfg phandle for IOMMU Date: Thu, 9 Jun 2022 12:08:00 +0200 Message-Id: <20220609100802.54513-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> References: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The IOMMU driver now looks for the "mediatek,infracfg" phandle as a new way to retrieve a syscon to that: even though the old way is retained, it has been deprecated and the driver will write a message in kmsg advertising to use the phandle way instead. For this reason, assign the right phandle to mediatek,infracfg in the iommu node. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen =20 --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dt= s/mediatek/mt2712e.dtsi index 623eb3beabf2..4797537cb368 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -329,6 +329,7 @@ iommu0: iommu@10205000 { interrupts =3D ; clocks =3D <&infracfg CLK_INFRA_M4U>; clock-names =3D "bclk"; + mediatek,infracfg =3D <&infracfg>; mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>, <&larb3>, <&larb6>; #iommu-cells =3D <1>; @@ -346,6 +347,7 @@ iommu1: iommu@1020a000 { interrupts =3D ; clocks =3D <&infracfg CLK_INFRA_M4U>; clock-names =3D "bclk"; + mediatek,infracfg =3D <&infracfg>; mediatek,larbs =3D <&larb4>, <&larb5>, <&larb7>; #iommu-cells =3D <1>; }; --=20 2.35.1 From nobody Sat Sep 21 23:34:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21B40C433EF for ; Thu, 9 Jun 2022 10:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235153AbiFIKId (ORCPT ); Thu, 9 Jun 2022 06:08:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242775AbiFIKIQ (ORCPT ); Thu, 9 Jun 2022 06:08:16 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E31860FA; Thu, 9 Jun 2022 03:08:15 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id CAD9866017CA; Thu, 9 Jun 2022 11:08:11 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654769292; bh=pb2gWlG7j2g032SqdnNvyy3B/6lmxFBQubwWdcY6ii4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q9sTvQ6OjmfN2Xr+h60kQLRKdH+Ux3vnvpmUoxw3cSwR++4MBAYYuBli09cSDm7R9 /8vEybuz6HL0qQ3LpazzQETe61gJ2WTP+h+Qoahk2WXFeRpczFWosmchVsQWu4oPoY fRJV1prrWSfchOnxeH/5SNCNFV0hOgK7unGczlDq8gIL0DeVYOz9NZ2wYud5c9YuPo pqwbhAOF+jlLIF807YlqGcdaP5P7aEsSjDSPsX5HjRZVOmcaWB9Pr6IL6p3/eMsCze xj8V0I/woD8cOlcaRepHc2UphyFB9OkBkdrla784kO4WOQs46nyMTgvXvV+IShUwX6 nVaHIcLshW5hA== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v3 5/6] dt-bindings: iommu: mediatek: Add mediatek,pericfg phandle Date: Thu, 9 Jun 2022 12:08:01 +0200 Message-Id: <20220609100802.54513-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> References: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add property "mediatek,pericfg" to let the mtk_iommu driver retrieve a phandle to the infracfg syscon instead of performing a per-soc compatible lookup in the entire devicetree and set it as a required property for MT8195's infra IOMMU. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/iommu/mediatek,iommu.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/= Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 4142a568b293..d5e3272a54e8 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -116,6 +116,10 @@ properties: Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must= sort according to the local arbiter index, like larb0, larb1, larb2... =20 + mediatek,pericfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the mediatek pericfg syscon + '#iommu-cells': const: 1 description: | @@ -183,6 +187,16 @@ allOf: required: - mediatek,infracfg =20 + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-iommu-infra + + then: + required: + - mediatek,pericfg + - if: # The IOMMUs don't have larbs. not: properties: --=20 2.35.1 From nobody Sat Sep 21 23:34:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C000EC433EF for ; Thu, 9 Jun 2022 10:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242910AbiFIKIg (ORCPT ); Thu, 9 Jun 2022 06:08:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242763AbiFIKIQ (ORCPT ); Thu, 9 Jun 2022 06:08:16 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 378B25FC8; Thu, 9 Jun 2022 03:08:15 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AD97A66017CC; Thu, 9 Jun 2022 11:08:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1654769293; bh=Plms5A1aPKPSw6D4rqzNZbSfoJtYh6ZPWxqrodjCyng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hPu7vlTYqvPWk04niq1EAUwsL2W3fSGKAoBbW6zTm2JV9mwOV8aXa//KUFGWQaZxw 7s9sYunRMusw/qp+ZxpiHTriyjgwjEt/xlqkrzOKckn8GuiYAHuqoUJYTVX8K2GdfJ 3GNQYJjp9RFVOgsZG7JiC0VHrRnAUI3LoeErDsE3eQ7fCICH0xpYdx9hQhdE8uri2g slqkg2Tzkw/DFMnwgck0DA7dvY73eupKyozNYz/2OS56feC6lYMQOCRZCpm0FDf6Sy GY93oKQUTH3z54ZQl9UX+xhgKYppD8kbWauVYDcdMxSdSJ3dAqufFaLpu6bwQJdNTt 0EjYwWP1HQ4Pw== From: AngeloGioacchino Del Regno To: yong.wu@mediatek.com Cc: joro@8bytes.org, will@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski@linaro.org, AngeloGioacchino Del Regno Subject: [PATCH v3 6/6] iommu: mtk_iommu: Lookup phandle to retrieve syscon to pericfg Date: Thu, 9 Jun 2022 12:08:02 +0200 Message-Id: <20220609100802.54513-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> References: <20220609100802.54513-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On some SoCs (of which only MT8195 is supported at the time of writing), the "R" and "W" (I/O) enable bits for the IOMMUs are in the pericfg_ao register space and not in the IOMMU space: as it happened already with infracfg, it is expected that this list will grow. Instead of specifying pericfg compatibles on a per-SoC basis, following what was done with infracfg, let's lookup the syscon by phandle instead. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 90685946fcbe..0ea0848581e9 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -138,6 +138,8 @@ /* PM and clock always on. e.g. infra iommu */ #define PM_CLK_AO BIT(15) #define IFA_IOMMU_PCIE_SUPPORT BIT(16) +/* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ +#define HAS_PERI_IOMMU1_REG BIT(17) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -187,7 +189,6 @@ struct mtk_iommu_plat_data { u32 flags; u32 inv_sel_reg; =20 - char *pericfg_comp_str; struct list_head *hw_list; unsigned int iova_region_nr; const struct mtk_iommu_iova_region *iova_region; @@ -1218,14 +1219,16 @@ static int mtk_iommu_probe(struct platform_device *= pdev) goto out_runtime_disable; } } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && - data->plat_data->pericfg_comp_str) { - infracfg =3D syscon_regmap_lookup_by_compatible(data->plat_data->pericfg= _comp_str); - if (IS_ERR(infracfg)) { - ret =3D PTR_ERR(infracfg); - goto out_runtime_disable; + MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_PERI_IOMMU1_REG)) { + data->pericfg =3D syscon_regmap_lookup_by_phandle(dev->of_node, "mediate= k,pericfg"); + if (IS_ERR(data->pericfg)) { + p =3D "mediatek,mt8195-pericfg_ao"; + data->pericfg =3D syscon_regmap_lookup_by_compatible(p); + if (IS_ERR(data->pericfg)) { + ret =3D PTR_ERR(data->pericfg); + goto out_runtime_disable; + } } - - data->pericfg =3D infracfg; } =20 platform_set_drvdata(pdev, data); @@ -1484,8 +1487,8 @@ static const struct mtk_iommu_plat_data mt8192_data = =3D { static const struct mtk_iommu_plat_data mt8195_data_infra =3D { .m4u_plat =3D M4U_MT8195, .flags =3D WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_A= O | - MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, - .pericfg_comp_str =3D "mediatek,mt8195-pericfg_ao", + HAS_PERI_IOMMU1_REG | MTK_IOMMU_TYPE_INFRA | + IFA_IOMMU_PCIE_SUPPORT, .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, .banks_num =3D 5, .banks_enable =3D {true, false, false, false, true}, --=20 2.35.1