From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5840FC433EF for ; Thu, 9 Jun 2022 09:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242842AbiFIJiV (ORCPT ); Thu, 9 Jun 2022 05:38:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242807AbiFIJiS (ORCPT ); Thu, 9 Jun 2022 05:38:18 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1054032EE8 for ; Thu, 9 Jun 2022 02:38:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654767497; x=1686303497; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WM3JFuf+XYcullGR01eKGb7NQo6CAvDdzpgDWQsXV8g=; b=iMJhbE391xB5R4nQu68u47Ofcymh9MmgHoneZiNhcK4gDXlaKCeeYGi8 pb40LXDO2QN/j0i5Bd8LYthj8Lv1UP6n9TVHfY7C5cO1EKIbHDYkVyy5i aYjNDMyAYuDvdZGDnxcxSje4G9lv7gdj9jk35S2aJOWGnA1gj8DypUkWX LyLbbmuOB3a2rLUMzmKCPdp2B+EpVFF62w/Y8SvNvGFf1HBCV08eToPSs 3ZMRTe03eV1LUGN4X0C5dI1vGmWvqeAKNkQRXW+xnAwQV4QX7PJ96EbcY 26PFF8bnQxhKmH5ZFUrU9KIK1m8RAK4Vo4YuRFQCU/5wAt0f52/mszBkJ w==; X-IronPort-AV: E=Sophos;i="5.91,287,1647327600"; d="scan'208";a="99267783" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jun 2022 02:38:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Jun 2022 02:38:14 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Jun 2022 02:38:13 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [RESEND][PATCH 1/3] clocksource/drivers/timer-microchip-pit64b: remove suspend/resume ops for ce Date: Thu, 9 Jun 2022 12:40:39 +0300 Message-ID: <20220609094041.1796372-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220609094041.1796372-1-claudiu.beznea@microchip.com> References: <20220609094041.1796372-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove suspend and resume ops for clockevent and add set_state_oneshot() instead. Along with this mchp_pit64b_{suspend, resume}() were called on proper function to disable/enable clocks. This will allow disabling clocks for clockevent in case it is not selected as active clockevent. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 30 +++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index abce83d2f00b..b51259395ac3 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -173,7 +173,8 @@ static int mchp_pit64b_clkevt_shutdown(struct clock_eve= nt_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); + if (!clockevent_state_detached(cedev)) + mchp_pit64b_suspend(timer); =20 return 0; } @@ -182,35 +183,37 @@ static int mchp_pit64b_clkevt_set_periodic(struct clo= ck_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, MCHP_PIT64B_IER_PERIOD); =20 return 0; } =20 -static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, - struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT, MCHP_PIT64B_IER_PERIOD); =20 return 0; } =20 -static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, + struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - mchp_pit64b_suspend(timer); -} - -static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) -{ - struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); + mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + MCHP_PIT64B_IER_PERIOD); =20 - mchp_pit64b_resume(timer); + return 0; } =20 static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) @@ -395,9 +398,8 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_p= it64b_timer *timer, ce->clkevt.rating =3D 150; ce->clkevt.set_state_shutdown =3D mchp_pit64b_clkevt_shutdown; ce->clkevt.set_state_periodic =3D mchp_pit64b_clkevt_set_periodic; + ce->clkevt.set_state_oneshot =3D mchp_pit64b_clkevt_set_oneshot; ce->clkevt.set_next_event =3D mchp_pit64b_clkevt_set_next_event; - ce->clkevt.suspend =3D mchp_pit64b_clkevt_suspend; - ce->clkevt.resume =3D mchp_pit64b_clkevt_resume; ce->clkevt.cpumask =3D cpumask_of(0); ce->clkevt.irq =3D irq; =20 --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68682CCA47D for ; Thu, 9 Jun 2022 09:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242892AbiFIJi0 (ORCPT ); Thu, 9 Jun 2022 05:38:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242758AbiFIJiT (ORCPT ); Thu, 9 Jun 2022 05:38:19 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B37C633355 for ; Thu, 9 Jun 2022 02:38:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654767498; x=1686303498; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MhR3GL37aD2094muc0mbYoEzyBnN3ng+SbxKNMGBHqU=; b=q5QoWxf0NMDM5fBlnxHxi3KAiu5GA3brQHsYx3iRKxFQmaIVmZMuhCp6 eI0VXRewFiUgmSUSj3SfoQpwU4EoOPQdyf9ErBuHkqXsKRN6uosGAahLl ROPgUdMDiwB/OdmdXsImLfd4Lj+xJ+Rz7GvRqRfvs/hEeLc83FUNAmtxd IAYD2YV7o+NHjJp/XQeV2GbcCTnJQBs22Limtlw/mWBPQ31Pqv72eTjfQ X7XXhu3Ig4AohAuD94jd9FJR06IBtkQTsr8nm4Zh2clYoC1kNbf2U7nfz 5QxRsupAID9wx51vmct4Wx3a/Fp/8R13sIgQBEc8AhXbK91LX4O2WIt/o w==; X-IronPort-AV: E=Sophos;i="5.91,287,1647327600"; d="scan'208";a="99267784" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jun 2022 02:38:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Jun 2022 02:38:16 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Jun 2022 02:38:15 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [RESEND][PATCH 2/3] clocksource/drivers/timer-microchip-pit64b: use mchp_pit64b_{suspend, resume} Date: Thu, 9 Jun 2022 12:40:40 +0300 Message-ID: <20220609094041.1796372-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220609094041.1796372-1-claudiu.beznea@microchip.com> References: <20220609094041.1796372-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 24 ++++---------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index b51259395ac3..f50705698283 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -344,6 +344,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, if (!cs) return -ENOMEM; =20 + mchp_pit64b_resume(timer); mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); =20 mchp_pit64b_cs_base =3D timer->base; @@ -365,8 +366,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); =20 /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); + mchp_pit64b_suspend(timer); kfree(cs); =20 return ret; @@ -450,19 +450,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, if (ret) goto irq_unmap; =20 - ret =3D clk_prepare_enable(timer.pclk); - if (ret) - goto irq_unmap; - - if (timer.mode & MCHP_PIT64B_MR_SGCLK) { - ret =3D clk_prepare_enable(timer.gclk); - if (ret) - goto pclk_unprepare; - + if (timer.mode & MCHP_PIT64B_MR_SGCLK) clk_rate =3D clk_get_rate(timer.gclk); - } else { + else clk_rate =3D clk_get_rate(timer.pclk); - } clk_rate =3D clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); =20 if (clkevt) @@ -471,15 +462,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, ret =3D mchp_pit64b_init_clksrc(&timer, clk_rate); =20 if (ret) - goto gclk_unprepare; + goto irq_unmap; =20 return 0; =20 -gclk_unprepare: - if (timer.mode & MCHP_PIT64B_MR_SGCLK) - clk_disable_unprepare(timer.gclk); -pclk_unprepare: - clk_disable_unprepare(timer.pclk); irq_unmap: irq_dispose_mapping(irq); io_unmap: --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59351C43334 for ; Thu, 9 Jun 2022 09:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240041AbiFIJih (ORCPT ); Thu, 9 Jun 2022 05:38:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234406AbiFIJiU (ORCPT ); Thu, 9 Jun 2022 05:38:20 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED32E33355 for ; Thu, 9 Jun 2022 02:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654767500; x=1686303500; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uJ5qZvhAQ1nIadAE2aDvP4HNyjdst+87wL1ry98HR+g=; b=eEueqbgSd6x0SpGwnY2By2cYbvPhPMdYdJGGhCgWl6srTeaXNgI6slMc ikOFvA3R3I2TggQL9rEsFddyC8SF4oiGNF5cRDmIuFqGQlBjCPY6rijbh f127cgWe2eiIOcRyYNN5M0DbB9Ac41PbC8VBboc5npUvC3LmmsZajuN1N 1a1kY3i0HKvhHPs+4JKuwQryJGebMPUvg9R3gfMO5foiGcStDfVKymdaY 7MYv4agnr9QYYc1YU4htnWS3LckED9BUb9TiK8l9qp6Ml8hE0w3vWspa6 4+8/iaqfsiHxVongGh88MyXNQb4pDU1HR8ozxhbM5skwg95qFpfbpvqUu g==; X-IronPort-AV: E=Sophos;i="5.91,287,1647327600"; d="scan'208";a="159549787" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jun 2022 02:38:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Jun 2022 02:38:18 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Jun 2022 02:38:17 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [RESEND][PATCH 3/3] clocksource/drivers/timer-microchip-pit64b: fix compilation warnings Date: Thu, 9 Jun 2022 12:40:41 +0300 Message-ID: <20220609094041.1796372-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220609094041.1796372-1-claudiu.beznea@microchip.com> References: <20220609094041.1796372-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following compilation warnings: timer-microchip-pit64b.c:68: warning: cannot understand function prototype:= 'struct mchp_pit64b_clkevt ' timer-microchip-pit64b.c:82: warning: cannot understand function prototype:= 'struct mchp_pit64b_clksrc ' timer-microchip-pit64b.c:283: warning: Function parameter or member 'timer'= not described in 'mchp_pit64b_init_mode' timer-microchip-pit64b.c:283: warning: Function parameter or member 'max_ra= te' not described in 'mchp_pit64b_init_mode' Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index f50705698283..d5f1436f33d9 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -61,7 +61,7 @@ struct mchp_pit64b_timer { }; =20 /** - * mchp_pit64b_clkevt - PIT64B clockevent data structure + * struct mchp_pit64b_clkevt - PIT64B clockevent data structure * @timer: PIT64B timer * @clkevt: clockevent */ @@ -75,7 +75,7 @@ struct mchp_pit64b_clkevt { struct mchp_pit64b_clkevt, clkevt)) =20 /** - * mchp_pit64b_clksrc - PIT64B clocksource data structure + * struct mchp_pit64b_clksrc - PIT64B clocksource data structure * @timer: PIT64B timer * @clksrc: clocksource */ @@ -245,8 +245,10 @@ static void __init mchp_pit64b_pres_compute(u32 *pres,= u32 clk_rate, } =20 /** - * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at - * runtime; this includes prescaler and SGCLK bit + * mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used= at + * runtime; this includes prescaler and SGCLK bit + * @timer: pointer to pit64b timer to init + * @max_rate: maximum rate that timer's clock could use * * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has= to * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk ra= te --=20 2.34.1