From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF805CCA485 for ; Thu, 9 Jun 2022 09:29:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240078AbiFIJ36 (ORCPT ); Thu, 9 Jun 2022 05:29:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233466AbiFIJ3t (ORCPT ); Thu, 9 Jun 2022 05:29:49 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88AC4265FBF for ; Thu, 9 Jun 2022 02:29:46 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id v1so35590427ejg.13 for ; Thu, 09 Jun 2022 02:29:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fJgKFMAN9XJcQFXSIBW4zb7s2vD8f3jyjsxvG6sAqRM=; b=auf48QyAWW6DZqUwau9GfDXaTM/n+lX6tK+nWSa5AjM15Fy8+nXLC9b0hwqLXrzNyL MsvVCHfuZqmeQKapyOpfQQzkxniNGgTGGJ/nnEHubG2huBk3o4pwpCStcnHPqlDHnSqJ ILNuVDMFAGaTiZVX0gT+7dqokUEEaIn1bw+oIosCLjlWp5F31xCCvOWA37D+CQtvmslH NT74Gou10r8h9r7HIPMzuM99zi29OOuOV8iTfAzSFddw7grZ9mqhdYGUVTHWV6crZIVj I3icS1Gz4oQ2DdPX2IxJaSFy4tKcoA1Hp6ugMUpbEF3f7WFznXO+KvsU7ZLgJc+tZbhS eUGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fJgKFMAN9XJcQFXSIBW4zb7s2vD8f3jyjsxvG6sAqRM=; b=EUAiSR3L9dnoTN39XSmGCG4wcnMonJBLiTQ3rJ1n4S0RDvz+X0NbSgp/bihDltlzqU O2QpKw36MfnwVEv2QYdnYRF/BA7BWU3Ec5iwsSG8Ih78zsJjNpIQcPnY040UGFnU3o5Y E932RoKV1/7C2CHzL44niFvoFavE7VLsfxMv0KxROoolvQET7/YVy5sXM/nxLh+kbRnN jeoGQs2W+EjrxOT3tiW6ALyc4AMNrPDvaLUIPij9SSIMLWHEouw8pwWn/uFo8ozR6wL5 enL0l7pbxwLgLsgGOoN7ASXvA9uN5JbZkFjF9MCgAw0m37BhaKafeJGZxztn/m11MCBX iZWA== X-Gm-Message-State: AOAM531hT5UtBimIi3O4wXHYRLeR9+KFQwLY6Ejoswfr+AYo/ZJ11ioX zqy3q6M7gJDSWQ4y3Q2T61chVA== X-Google-Smtp-Source: ABdhPJxJUOFMqR/aHNywQZi7vQBO0lulUn4MK0goRVj8Co2AsVCKs5zP899BJ2chAURT6N1y+ONWiQ== X-Received: by 2002:a17:907:8692:b0:711:d49f:994d with SMTP id qa18-20020a170907869200b00711d49f994dmr16555809ejc.578.1654766985025; Thu, 09 Jun 2022 02:29:45 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:44 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v5 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Date: Thu, 9 Jun 2022 11:29:35 +0200 Message-Id: <20220609092940.304740-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace &rpmhpd power domain integers with their respective defines in order to improve legibility. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index c0137bdcf94b..52428b6df64e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1656,8 +1656,8 @@ mpss: remoteproc@4080000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 0>, - <&rpmhpd 12>; + power-domains =3D <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MSS>; power-domain-names =3D "cx", "mss"; =20 interconnects =3D <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; @@ -2167,8 +2167,8 @@ slpi: remoteproc@5c00000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains =3D <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names =3D "lcx", "lmx"; =20 memory-region =3D <&pil_slpi_mem>; @@ -2235,8 +2235,8 @@ cdsp: remoteproc@98900000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 0>, - <&rpmhpd 10>; + power-domains =3D <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; power-domain-names =3D "cx", "mxc"; =20 interconnects =3D <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -2540,8 +2540,8 @@ adsp: remoteproc@17300000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 - power-domains =3D <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains =3D <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names =3D "lcx", "lmx"; =20 memory-region =3D <&pil_adsp_mem>; --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37B99C433EF for ; Thu, 9 Jun 2022 09:30:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241844AbiFIJaH (ORCPT ); Thu, 9 Jun 2022 05:30:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238994AbiFIJ3x (ORCPT ); Thu, 9 Jun 2022 05:29:53 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FC23267179 for ; Thu, 9 Jun 2022 02:29:47 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id x62so30378805ede.10 for ; Thu, 09 Jun 2022 02:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3K0yeOxisyM0JQpus5poZjk78yeWZzBvVOOOvacU4w4=; b=VOYQ6Qr26l4SLbTedytzwf4wjkSZ7RgBqYQqm0QKMyu7tVsRs47BziAXJlxyg369Bj N1K75R2wZWHauYjVBmqZSMCJQbIV/JCarFmeoCCZiELkiNyuijHnzf0g7QOCboDJR+HZ fPifhcvcdw+YJJ0o4PPtDBLyNn/dr2I0wiLfhtN0GPhtYF+YtKaxYCC5i7St6fmWE6Si LOo08BNziiqpQOKKQQ9nOiSeS4o1+Gdo22WopYeNnQ2DEpM5Zag/PQpxzBpBKnoQsTjQ gS6A0vNPTmBxFuurslHk8x2H9qeCPv+Alc7+AEPI4yDYVHdEuD4Bj2OFi0Ose+QoltcH fq1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3K0yeOxisyM0JQpus5poZjk78yeWZzBvVOOOvacU4w4=; b=7C9t6mWiJ0exoIOkm1Yl0MOBmbRWoGkPUryAnHwZBjpYBDivsVOIODsPEwvOeDm/oI DlXXlKl/0uXLpQLi/ZzjFZztSzTT3ARG4VoJ/BiKKep4AkK3P0prmhilPcu8oHx4IHvl KpA+W1nCYDvLHxwvZt6Wj2kMLww/BQw2+0cYt2K0jZduj0T27Nw1YY5gChkSKwVm5Ray ZmfJTZaMqzZZI7R/hHLhwC79cXcei4jX5KkEGQEeJLzFcAENcBXZrfv4McYMfsVO9168 l6MCy6r0hMXs4xV9NVFbYucIECZQJr6bFzYz2cneJl4J1U3TeRKCQ9LkK+DyB5xjArrl Iy0A== X-Gm-Message-State: AOAM532PlsoWh8iOlLffdZLC3j1IyD2wJ6ADY5yY5NOSat+ujY5LvnY5 5G4rPAUdRU+6n93YKw0qM2tsrQ== X-Google-Smtp-Source: ABdhPJzc30Xevb52ZVguNpz/g8K+58D+N4dhRONYYryRHvDZJC0BmEBxm55xgs5BejNdcO7JXHHgdw== X-Received: by 2002:aa7:c396:0:b0:42d:8b86:a8dc with SMTP id k22-20020aa7c396000000b0042d8b86a8dcmr43154042edq.54.1654766986220; Thu, 09 Jun 2022 02:29:46 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:45 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC Date: Thu, 9 Jun 2022 11:29:36 +0200 Message-Id: <20220609092940.304740-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss Signed-off-by: Jonathan Marek --- Changes since v1 - Remove .name assignments for clk_parent_data - Dmitry - Use ARRAY_SIZE where possible - Dmitry - Remove commented out code - Dmitry - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry - Assign .parent_hws instead of .hw - Dmitry Changes since v2 - Switch license to dual BSD/GPL - Bjorn - Add Jonathans SoB - Jonathan - Add Linaro to copyright statement - Bjorn - Make .hw.init assignment const - Bjorn - Extract & deduplicate bi_tcxo parent_data - Bjorn - Removed further .name assignment - Bjorn - Move of_device_id declaration - Bjorn Changes since v3 - Change license to BSD/GPL - Rob/Bjorn - Switch from .fw_name to .index Changes since v4 - Change year of copyright statement - Change to dual license for header file - Rob drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bc4dcf356d82..b11235c21952 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -712,6 +712,14 @@ config SM_GPUCC_8250 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_GPUCC_8350 + tristate "SM8350 Graphics Clock Controller" + select SM_GCC_8350 + help + Support for the graphics clock controller on SM8350 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 36789f5233ef..ef9c64824424 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) +=3D gcc-sm8450.o obj-$(CONFIG_SM_GPUCC_6350) +=3D gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) +=3D gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) +=3D gpucc-sm8250.o +obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8150) +=3D videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm835= 0.c new file mode 100644 index 000000000000..68d85757e064 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-divider.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_5lpe_vco[] =3D { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x18, + .alpha =3D 0x6000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2A9A699C, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static const struct clk_parent_data gpu_cc_parent =3D { + .fw_name =3D "bi_tcxo", +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_pll0", + .parent_data =3D &gpu_cc_parent, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x1A, + .alpha =3D 0xAAA, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2A9A699C, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x100, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_pll1", + .parent_data =3D &gpu_cc_parent, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + gpu_cc_parent, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .fw_name =3D "gcc_gpu_gpll0_clk_src" }, + { .fw_name =3D "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + gpu_cc_parent, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .fw_name =3D "gcc_gpu_gpll0_clk_src" }, + { .fw_name =3D "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x1120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x117c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src =3D { + .reg =3D 0x11c0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "gpu_cc_hub_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src =3D { + .reg =3D 0x11bc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x1078, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1078, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk =3D { + .halt_reg =3D 0x1170, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1170, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x107c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x107c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk =3D { + .halt_reg =3D 0x1088, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1088, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_apb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x1098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1098, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_at_clk =3D { + .halt_reg =3D 0x1080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_qdss_at_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_trig_clk =3D { + .halt_reg =3D 0x1094, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1094, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_qdss_trig_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk =3D { + .halt_reg =3D 0x1084, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1084, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_qdss_tsctr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { + .halt_reg =3D 0x108c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_snoc_dvm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk =3D { + .halt_reg =3D 0x1004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_aon_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x109c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x109c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x120c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x120c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x1064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk =3D { + .halt_reg =3D 0x105c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x105c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_qdss_tsctr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk =3D { + .halt_reg =3D 0x1058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_vsense_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x5000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x5000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x1178, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1178, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x1204, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1204, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk =3D { + .halt_reg =3D 0x802c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x802c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_mnd1x_0_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_mnd1x_1_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x1090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1090, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc =3D { + .gdscr =3D 0x106c, + .gds_hw_ctrl =3D 0x1540, + .pd =3D { + .name =3D "gpu_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc =3D { + .gdscr =3D 0x100c, + .clamp_io_ctrl =3D 0x1508, + .pd =3D { + .name =3D "gpu_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_sm8350_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] =3D &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_QDSS_AT_CLK] =3D &gpu_cc_cx_qdss_at_clk.clkr, + [GPU_CC_CX_QDSS_TRIG_CLK] =3D &gpu_cc_cx_qdss_trig_clk.clkr, + [GPU_CC_CX_QDSS_TSCTR_CLK] =3D &gpu_cc_cx_qdss_tsctr_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_QDSS_TSCTR_CLK] =3D &gpu_cc_gx_qdss_tsctr_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] =3D &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] =3D &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] =3D &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] =3D &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm8350_resets[] =3D { + [GPUCC_GPU_CC_ACD_BCR] =3D { 0x1160 }, + [GPUCC_GPU_CC_CB_BCR] =3D { 0x116c }, + [GPUCC_GPU_CC_CX_BCR] =3D { 0x1068 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] =3D { 0x1174 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] =3D { 0x10a0 }, + [GPUCC_GPU_CC_GMU_BCR] =3D { 0x111c }, + [GPUCC_GPU_CC_GX_BCR] =3D { 0x1008 }, + [GPUCC_GPU_CC_XO_BCR] =3D { 0x1000 }, +}; + +static struct gdsc *gpu_cc_sm8350_gdscs[] =3D { + [GPU_CX_GDSC] =3D &gpu_cx_gdsc, + [GPU_GX_GDSC] =3D &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm8350_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8030, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8350_desc =3D { + .config =3D &gpu_cc_sm8350_regmap_config, + .clks =3D gpu_cc_sm8350_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sm8350_clocks), + .resets =3D gpu_cc_sm8350_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sm8350_resets), + .gdscs =3D gpu_cc_sm8350_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sm8350_gdscs), +}; + +static int gpu_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &gpu_cc_sm8350_desc); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); +} + +static const struct of_device_id gpu_cc_sm8350_match_table[] =3D { + { .compatible =3D "qcom,sm8350-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); + +static struct platform_driver gpu_cc_sm8350_driver =3D { + .probe =3D gpu_cc_sm8350_probe, + .driver =3D { + .name =3D "sm8350-gpucc", + .of_match_table =3D gpu_cc_sm8350_match_table, + }, +}; + +static int __init gpu_cc_sm8350_init(void) +{ + return platform_driver_register(&gpu_cc_sm8350_driver); +} +subsys_initcall(gpu_cc_sm8350_init); + +static void __exit gpu_cc_sm8350_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm8350_driver); +} +module_exit(gpu_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); +MODULE_LICENSE("GPL v2"); --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25C94C43334 for ; Thu, 9 Jun 2022 09:30:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241307AbiFIJaD (ORCPT ); Thu, 9 Jun 2022 05:30:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238564AbiFIJ3x (ORCPT ); Thu, 9 Jun 2022 05:29:53 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0425A267CD2 for ; Thu, 9 Jun 2022 02:29:48 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id kq6so33240597ejb.11 for ; Thu, 09 Jun 2022 02:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oQCEzz12ukJcqXabLCIweZqpeRWMz2frfEfSdC7n6WI=; b=xEq2Ezz6CrU830NkrO8MBbZYSvUHIf31/ROvyYHt1UvRN8h7Rk8UAddUikfjj4Pe98 GKB6iI9LQgq4j8uKqQuLWc3b33FkPKRG5Ied+Sk7gBDribwOGs+EC273NPCD0pYtNa/O 0ifY1cDH2fRcHcpi1/Hy5//iyDMd/b1mmwoS69RXU2WtkS8e3JyNtlA5UFgv5B6hhhGk m2aaai2OcDNnI5hunNZa8tOShkHGNb7TG/fxeZu5OrCYR3AcyAonUAIxPwfV4nPX4APO MWO8unOcxkPzhRYGZ3R3hhLY70lXXL/TdkPwzLnPivDx4wbmQjaGtz09bhkm58ElmTdi JzbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oQCEzz12ukJcqXabLCIweZqpeRWMz2frfEfSdC7n6WI=; b=C9z099nHb/RallJTJYnyk6ihlFOtweJTCLV8LGjLCTFx7PUy+PxDfLZ5K4vGo0eoak fz/2Q2aJedf/904TladkxWQvj2GpB43thFnXM/CfA3XqvK1LAtAH7TU8wAshd/Yvl2EE h2tKYWkTYwdGcpbc/lHmnWazEfg2oSNHnELD2c1O68IoiBK8BhtQ78RbooAd2LxfieTk E9ABqjJ/VEKyYfpTAW49pSx58Q3WAndQJPtohiVaNqW7ilEzzHvOMfqkVr4bQvcIbEYh IoE2RxQQdNRuvQ9fD6SNexLkugqV8mU54+DLwo/aTUSyGPHCqvaPpHy/cmZfgFRerk4l gAKA== X-Gm-Message-State: AOAM531scF+Oym7bCWU5wEt8UkreHakERQaqU9IHnao1L6FlKKwfRVbe Ljea5nOpL2/nMnhJiT0dogsvAQ== X-Google-Smtp-Source: ABdhPJwk+xmn5SurY9iYay63P74ewXYNsm5jhUhp81Z4B4384bJPHBOD2iMAck8Efwj0WS+WPX5O1g== X-Received: by 2002:a17:907:62a1:b0:6da:7952:d4d2 with SMTP id nd33-20020a17090762a100b006da7952d4d2mr34722809ejc.260.1654766987446; Thu, 09 Jun 2022 02:29:47 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:46 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Dmitry Baryshkov Subject: [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Thu, 9 Jun 2022 11:29:37 +0200 Message-Id: <20220609092940.304740-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reported-by: kernel test robot Reviewed-by: Rob Herring --- Changes since v3 - Separate from qcom,gpucc - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm83= 50.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml= b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss + +description: | + Qualcomm graphics clock control module which supports the clocks, resets= and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@3d90000 { + compatible =3D "qcom,sm8350-gpucc"; + reg =3D <0 0x03d90000 0 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bin= dings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CF22C433EF for ; Thu, 9 Jun 2022 09:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242241AbiFIJaR (ORCPT ); Thu, 9 Jun 2022 05:30:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239498AbiFIJ3y (ORCPT ); Thu, 9 Jun 2022 05:29:54 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0A23268555 for ; Thu, 9 Jun 2022 02:29:50 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id o7so12983515eja.1 for ; Thu, 09 Jun 2022 02:29:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mM6WMCb4U1Ua1nT40aZTmMzTGzg4MU648qxfTVm3JXk=; b=L9P8wca+7ciOQJEs12e0Qkfn26E7HtyzTpIoXC7a8PgJPk0SQilpoVH4G3+3agpcD7 bukBdPCVyQwzlPvz2moxz7aTFZ5WFPFFt2dwgjNf34m5B7SEM3UHTtPEVh/lOBtq0nOf RtxoXgBmQE9UHpKaMaSvNg7NPw0sPgeqhwWX37uBH2LBOnXpa+BdoN249BCy2wNK90zB ZF1UsuisOCjFJCwBXkYyaNEjkfsM5GI0WiPmk5jn6wyYXdJrTl/I51zFRz9ZYJyXrJEX OsLsKMq8v6H29Cp/wGDfXcshlenIpmRjODloQcy65q5xQLwlx0JO1AoMdLN5KQ0DIIlv YJlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mM6WMCb4U1Ua1nT40aZTmMzTGzg4MU648qxfTVm3JXk=; b=sS7cUONYL/b+1FwfftXNSeZbSiY/zqeHCeQdM9kFlh6bra855clvz7rjz9ieSllhnR tlo9p5+jLGs59jGBvQUpSiuIf3m/JtrLNrbeNc7yybtZD82VP50RY3jhj9lw+UJMUt6O LTFScSxLN+k+Th73jYByucJB01yOBGDgmvxU+2MU4p94M6XQvO3WOdPXIh67sfEsVqKM qxOKhApWwNfrzwkKuxbtBUmDM90T8I3X8zxYPqHPoYb2lQIZQv7pEvUbJQWppKGVGIhV c9xg3LjHXFiIKfIFb5LjMpNFis20Pf1H8pImaZHEheUhtvWLPNZxX0GCZ7It3ogJn555 0JSw== X-Gm-Message-State: AOAM533ePq5W83SvkHbaKBBOtVALSq7II8OHZ8lwXmUtQAdvNKWx58hl aKRDTB1wOVGRp2cAjXP5QHXavO1VJqSBuxrN X-Google-Smtp-Source: ABdhPJyhW9og0a9QQ45Yc1VLDRlN4tfbrY+/J1QJgieiCuV0Ozs3V0oixSAiOANaKTXC8gCQanYF5A== X-Received: by 2002:a17:907:c22:b0:711:dc95:3996 with SMTP id ga34-20020a1709070c2200b00711dc953996mr13452930ejc.62.1654766989019; Thu, 09 Jun 2022 02:29:49 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:48 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC Date: Thu, 9 Jun 2022 11:29:38 +0200 Message-Id: <20220609092940.304740-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to the SM8350 display clock controller. While this controller is similar to the sm8250 controller, the differences are incompatible due to the .fw_name / .index change. Signed-off-by: Robert Foss --- Changes since v1 - Remove comment - Dmitry Changes since v2 - Add my SoB - Bjorn - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag Changes since v3 - Add kconfig dependency on SM_GCC_8350 - Konrad - Change hex to lowercase - Konrad - Split from dispcc-sm8250.c implementation - Switch from .fw_name to .index drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-sm8350.c | 1330 ++++++++++++++++++++++++++++++ 3 files changed, 1340 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b11235c21952..319812a1d614 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -626,6 +626,15 @@ config SM_DISPCC_8250 Say Y if you want to support display devices and functionality such as splash screen. =20 +config SM_DISPCC_8350 + tristate "SM8350 Display Clock Controller" + depends on SM_GCC_8350 + help + Support for the display clock controller on Qualcomm Technologies, Inc + SM8350 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config SM_DISPCC_6350 tristate "SM6350 Display Clock Controller" depends on SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ef9c64824424..70f98320eb1d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_SM_CAMCC_8250) +=3D camcc-sm8250.o obj-$(CONFIG_SM_DISPCC_6125) +=3D dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) +=3D dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_8250) +=3D dispcc-sm8250.o +obj-$(CONFIG_SM_DISPCC_8350) +=3D dispcc-sm8350.o obj-$(CONFIG_SM_GCC_6115) +=3D gcc-sm6115.o obj-$(CONFIG_SM_GCC_6125) +=3D gcc-sm6125.o obj-$(CONFIG_SM_GCC_6350) +=3D gcc-sm6350.o diff --git a/drivers/clk/qcom/dispcc-sm8350.c b/drivers/clk/qcom/dispcc-sm8= 350.c new file mode 100644 index 000000000000..269a0512f207 --- /dev/null +++ b/drivers/clk/qcom/dispcc-sm8350.c @@ -0,0 +1,1330 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_DP_PHY_PLL_LINK_CLK, + DT_DP_PHY_PLL_VCO_DIV_CLK, + DT_DPTX1_PHY_PLL_LINK_CLK, + DT_DPTX1_PHY_PLL_VCO_DIV_CLK, + DT_DPTX2_PHY_PLL_LINK_CLK, + DT_DPTX2_PHY_PLL_VCO_DIV_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + DT_EDP_PHY_PLL_LINK_CLK, + DT_EDP_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DISP_CC_PLL1_OUT_EVEN, + P_DISP_CC_PLL1_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DPTX1_PHY_PLL_LINK_CLK, + P_DPTX1_PHY_PLL_VCO_DIV_CLK, + P_DPTX2_PHY_PLL_LINK_CLK, + P_DPTX2_PHY_PLL_VCO_DIV_CLK, + P_EDP_PHY_PLL_LINK_CLK, + P_EDP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, +}; + +static struct pll_vco vco_table[] =3D { + { 249600000, 2000000000, 0 }, +}; + +static struct pll_vco lucid_5lpe_vco[] =3D { + { 249600000, 1750000000, 0 }, +}; + +static struct alpha_pll_config disp_cc_pll0_config =3D { + .l =3D 0x47, + .alpha =3D 0xE000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x329A699C, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_init_data disp_cc_pll0_init =3D { + .name =3D "disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_ops, +}; + +static struct clk_alpha_pll disp_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D vco_table, + .num_vco =3D ARRAY_SIZE(vco_table), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init =3D &disp_cc_pll0_init +}; + +static struct alpha_pll_config disp_cc_pll1_config =3D { + .l =3D 0x1F, + .alpha =3D 0x4000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x329A699C, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_init_data disp_cc_pll1_init =3D { + .name =3D "disp_cc_pll1", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_ops, +}; + +static struct clk_alpha_pll disp_cc_pll1 =3D { + .offset =3D 0x1000, + .vco_table =3D vco_table, + .num_vco =3D ARRAY_SIZE(vco_table), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init =3D &disp_cc_pll1_init +}; + +static const struct parent_map disp_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, + { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, + { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DPTX1_PHY_PLL_LINK_CLK }, + { .index =3D DT_DPTX1_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DPTX2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DPTX2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_EDP_PHY_PLL_LINK_CLK, 1 }, + { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_EDP_PHY_PLL_LINK_CLK}, + { .index =3D DT_EDP_PHY_PLL_VCO_DIV_CLK}, +}; + +static const struct parent_map disp_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll0.clkr.hw }, + { .hw =3D &disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct parent_map disp_cc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, + /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ +}; + +static const struct clk_parent_data disp_cc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll1.clkr.hw }, + /* { .hw =3D &disp_cc_pll1_out_even.clkr.hw }, */ +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), + F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x22bc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x210c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src =3D { + .cmd_rcgr =3D 0x2128, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_byte1_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src =3D { + .cmd_rcgr =3D 0x223c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_aux1_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src =3D { + .cmd_rcgr =3D 0x21d8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_aux_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src =3D { + .cmd_rcgr =3D 0x2208, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_link1_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src =3D { + .cmd_rcgr =3D 0x2174, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_link_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x21c0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_pixel1_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x21f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_pixel2_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src =3D { + .cmd_rcgr =3D 0x21a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_pixel_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src =3D { + .cmd_rcgr =3D 0x228c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_aux_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src =3D { + .cmd_rcgr =3D 0x22a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_7, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_gtc_clk_src", + .parent_data =3D disp_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src =3D { + .cmd_rcgr =3D 0x2270, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_link_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src =3D { + .cmd_rcgr =3D 0x2258, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_pixel_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_aux_clk =3D { + .halt_reg =3D 0x2078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2078, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_edp_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_gtc_clk =3D { + .halt_reg =3D 0x207c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x207c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_gtc_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_clk =3D { + .halt_reg =3D 0x2070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2070, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_link_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_intf_clk =3D { + .halt_reg =3D 0x2074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2074, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_pixel_clk =3D { + .halt_reg =3D 0x206c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x206c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_edp_pixel_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x2144, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src =3D { + .cmd_rcgr =3D 0x2160, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_esc1_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), + F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), + F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x20c4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x2094, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_6, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src =3D { + .cmd_rcgr =3D 0x20ac, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_6, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_pclk1_clk_src", + .parent_data =3D disp_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src =3D { + .cmd_rcgr =3D 0x20dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .freq_tbl =3D ftbl_disp_cc_mdss_rot_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_rot_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x20f4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x2124, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src =3D { + .reg =3D 0x2140, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "disp_cc_mdss_byte1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src =3D { + .reg =3D 0x2220, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src =3D { + .reg =3D 0x218c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "disp_cc_mdss_dp_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x207c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x207c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x2028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte1_clk =3D { + .halt_reg =3D 0x2030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte1_intf_clk =3D { + .halt_reg =3D 0x2034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_byte1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux1_clk =3D { + .halt_reg =3D 0x2068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2068, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_aux1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk =3D { + .halt_reg =3D 0x2054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2054, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link1_clk =3D { + .halt_reg =3D 0x205c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x205c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_link1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link1_intf_clk =3D { + .halt_reg =3D 0x2060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2060, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_link1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk =3D { + .halt_reg =3D 0x2040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_link_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk =3D { + .halt_reg =3D 0x2044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2044, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk =3D { + .halt_reg =3D 0x2050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2050, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel2_clk =3D { + .halt_reg =3D 0x2058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk =3D { + .halt_reg =3D 0x204c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x204c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_dp_pixel_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x2038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2038, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc1_clk =3D { + .halt_reg =3D 0x203c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x203c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x200c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x201c, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x201c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0x4004, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x4004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x2004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x2008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk =3D { + .halt_reg =3D 0x2014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_rot_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk =3D { + .halt_reg =3D 0x400c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_rscc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk =3D { + .halt_reg =3D 0x4008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_rscc_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x2024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2024, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc =3D { + .gdscr =3D 0x3000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL, + .supply =3D "mmcx", +}; + +static struct clk_regmap *disp_cc_sm8350_clocks[] =3D { + [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_BYTE1_CLK] =3D &disp_cc_mdss_byte1_clk.clkr, + [DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &disp_cc_mdss_byte1_clk_src.clkr, + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &disp_cc_mdss_byte1_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &disp_cc_mdss_byte1_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX1_CLK] =3D &disp_cc_mdss_dp_aux1_clk.clkr, + [DISP_CC_MDSS_DP_AUX1_CLK_SRC] =3D &disp_cc_mdss_dp_aux1_clk_src.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] =3D &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] =3D &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK1_CLK] =3D &disp_cc_mdss_dp_link1_clk.clkr, + [DISP_CC_MDSS_DP_LINK1_CLK_SRC] =3D &disp_cc_mdss_dp_link1_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] =3D &disp_cc_mdss_dp_link1_div_clk_sr= c.clkr, + [DISP_CC_MDSS_DP_LINK1_INTF_CLK] =3D &disp_cc_mdss_dp_link1_intf_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] =3D &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] =3D &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dp_link_div_clk_src.= clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] =3D &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] =3D &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL2_CLK] =3D &disp_cc_mdss_dp_pixel2_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] =3D &disp_cc_mdss_dp_pixel2_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] =3D &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] =3D &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK] =3D &disp_cc_mdss_edp_aux_clk.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK_SRC] =3D &disp_cc_mdss_edp_aux_clk_src.clkr, + [DISP_CC_MDSS_EDP_GTC_CLK] =3D &disp_cc_mdss_edp_gtc_clk.clkr, + [DISP_CC_MDSS_EDP_GTC_CLK_SRC] =3D &disp_cc_mdss_edp_gtc_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK] =3D &disp_cc_mdss_edp_link_clk.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK_SRC] =3D &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_INTF_CLK] =3D &disp_cc_mdss_edp_link_intf_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK] =3D &disp_cc_mdss_edp_pixel_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] =3D &disp_cc_mdss_edp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_ESC1_CLK] =3D &disp_cc_mdss_esc1_clk.clkr, + [DISP_CC_MDSS_ESC1_CLK_SRC] =3D &disp_cc_mdss_esc1_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_PCLK1_CLK] =3D &disp_cc_mdss_pclk1_clk.clkr, + [DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &disp_cc_mdss_pclk1_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] =3D &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] =3D &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] =3D &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, + [DISP_CC_PLL1] =3D &disp_cc_pll1.clkr, +}; + +static const struct qcom_reset_map disp_cc_sm8350_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x2000 }, + [DISP_CC_MDSS_RSCC_BCR] =3D { 0x4000 }, +}; + +static struct gdsc *disp_cc_sm8350_gdscs[] =3D { + [MDSS_GDSC] =3D &mdss_gdsc, +}; + +static const struct regmap_config disp_cc_sm8350_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc disp_cc_sm8350_desc =3D { + .config =3D &disp_cc_sm8350_regmap_config, + .clks =3D disp_cc_sm8350_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_sm8350_clocks), + .resets =3D disp_cc_sm8350_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_sm8350_resets), + .gdscs =3D disp_cc_sm8350_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_sm8350_gdscs), +}; + +static const struct of_device_id disp_cc_sm8350_match_table[] =3D { + { .compatible =3D "qcom,sc8180x-dispcc" }, + { .compatible =3D "qcom,sm8150-dispcc" }, + { .compatible =3D "qcom,sm8350-dispcc" }, + { .compatible =3D "qcom,sm8350-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_sm8350_match_table); + +static void disp_cc_sm8350_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + +static int disp_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret =3D devm_add_action_or_reset(&pdev->dev, disp_cc_sm8350_pm_runtime_di= sable, &pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &disp_cc_sm8350_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION !=3D CLK_ALPHA_PLL_TYPE_LUCID); + + disp_cc_mdss_ahb_clk_src.cmd_rcgr =3D 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val =3D 0x2a9a699c; + disp_cc_pll0_config.test_ctl_hi1_val =3D 0x01800000; + disp_cc_pll0_init.ops =3D &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table =3D lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val =3D 0x2a9a699c; + disp_cc_pll1_config.test_ctl_hi1_val =3D 0x01800000; + disp_cc_pll1_init.ops =3D &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table =3D lucid_5lpe_vco; + + clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); + + /* Enable clock gating for MDP clocks */ + regmap_update_bits(regmap, 0x8000, 0x10, 0x10); + + /* DISP_CC_XO_CLK always-on */ + regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + + ret =3D qcom_cc_really_probe(pdev, &disp_cc_sm8350_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver disp_cc_sm8350_driver =3D { + .probe =3D disp_cc_sm8350_probe, + .driver =3D { + .name =3D "disp_cc-sm8350", + .of_match_table =3D disp_cc_sm8350_match_table, + }, +}; + +static int __init disp_cc_sm8350_init(void) +{ + return platform_driver_register(&disp_cc_sm8350_driver); +} +subsys_initcall(disp_cc_sm8350_init); + +static void __exit disp_cc_sm8350_exit(void) +{ + platform_driver_unregister(&disp_cc_sm8350_driver); +} +module_exit(disp_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); +MODULE_LICENSE("GPL v2"); --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C68DC433EF for ; Thu, 9 Jun 2022 09:30:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234390AbiFIJa1 (ORCPT ); Thu, 9 Jun 2022 05:30:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240522AbiFIJ3z (ORCPT ); Thu, 9 Jun 2022 05:29:55 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B9F026A912 for ; Thu, 9 Jun 2022 02:29:51 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id h23so35213247ejj.12 for ; Thu, 09 Jun 2022 02:29:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tk8xKk87g7KBs4W4kVam7IN5r8rBhn+IuNaPzOCvkIw=; b=MvqSF2C/gpuiIsR1eSf/uq4UboM18mebtjm1gBpJ5iOX/w4rxrtA83bZjtI+3/HuJ9 KYpuNrbqgXjb/by+hio9F2JJ5FFH5+MaDGxzBiFkk8ygc/LJqku7HGTNjvWwOaDUP/Nr J6CFxYLVN5YqolZiESku49SJeTyrNetTd64UNzPwc6Ai5bVxlfkARV0LBFu/wkpS5klf F0/vw3gQ9KO1xmuiTVb9gYfLbSLdSl2PigW7yE7ZKPJ3In8+z/XKUMUAoDFCaBBsxUid CTfoX3+UGjpD/zllGo0iOafyyux1JDQkzo7RUywolWpQ0as681piWLWIYGyuqReaNpSQ MQqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tk8xKk87g7KBs4W4kVam7IN5r8rBhn+IuNaPzOCvkIw=; b=58jZT/RSyD2oBhbTUOBDrbOZQaFCX51P1UiLVReIx6uxwHaNIFx+mzqMq9Z21/FT2v sVD7eSrzQwN6hJIan0i09ccVMLcUDbYofFkruxX4fiwEw9+QG78IS0eLaPjAXYqgFKtn jdNx5WkMsXJ+muI5DuPPxh8Q9yt9uPR3Rvbai1m01oC0ez1hiNqGZO3t0JqU9KBftcr+ Fihq6D1AC9Ae64JgR8mR2rgOzn3WE4EDxbJAlxTTL6DG4InINh/TJvSlug94mO9wfgjp DOUdHk6r6IzhaGk808ILfLT8+BfHspxLdevZNHrxFtkUhRpKplfthrwu3ErPk3+e1Yja TIJw== X-Gm-Message-State: AOAM533MvfzWSJvoK/WPoyf3nsZCPN1G8f+CKurAC0t9HcWmJKqSlszt pBkrXBw+wa0CAJvrztVTZX/3ihn7c4jWt6Gj X-Google-Smtp-Source: ABdhPJx40CklTvHnvZRbXzyT8+3O05/kofWZm+QaUbSdhNWpUItOQa9FbvmrnCaduxCob2rME6ki6Q== X-Received: by 2002:a17:906:5d14:b0:6ff:4a45:11de with SMTP id g20-20020a1709065d1400b006ff4a4511demr34179801ejt.576.1654766991526; Thu, 09 Jun 2022 02:29:51 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:50 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Rob Herring Subject: [PATCH v5 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Thu, 9 Jun 2022 11:29:39 +0200 Message-Id: <20220609092940.304740-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add sm8350 DISPCC bindings, while these bindings are similar to the sm8x50 bindings, the way clocks are represented has changed in ABI incompatible ways. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- Changes since v2 - Add my SoB - Bjorn Changes since v3 - Separate from qcom,dispcc-sm8x50 - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v4 - Add RB - Rob .../bindings/clock/qcom,dispcc-sm8350.yaml | 104 ++++++++++++++++++ .../bindings/clock/qcom,dispcc-sm8x50.yaml | 4 +- .../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 3 files changed, 107 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8= 350.yaml create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yam= l b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml new file mode 100644 index 000000000000..d7e8739cab32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SM8350 + +maintainers: + - Robert Foss + +description: | + Qualcomm display clock control module which supports the clocks, resets = and + power domains on SM8350. + + See also: + dt-bindings/clock/qcom,dispcc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-dispcc + + clocks: + items: + - description: Board XO source + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + - description: Link clock from DPTX1 PHY + - description: VCO DIV clock from DPTX1 PHY + - description: Link clock from DPTX2 PHY + - description: VCO DIV clock from DPTX2 PHY + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from EDP PHY + - description: VCO DIV clock from EDP PHY + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@af00000 { + compatible =3D "qcom,sm8350-dispcc"; + reg =3D <0 0x0af00000 0 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&dp_phy 0>, + <&dp_phy 1>, + <&dptx1_phy 0>, + <&dptx1_phy 1>, + <&dptx2_phy 0>, + <&dptx2_phy 1>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yam= l b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..951fe2ecb7a6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250= /SM8350 =20 maintainers: - Jonathan Marek =20 description: | Qualcomm display clock control module which supports the clocks, resets = and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250. =20 See also: dt-bindings/clock/qcom,dispcc-sm8150.h diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bi= ndings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file --=20 2.34.1 From nobody Mon Apr 27 23:53:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90FE7C433EF for ; Thu, 9 Jun 2022 09:30:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242316AbiFIJag (ORCPT ); Thu, 9 Jun 2022 05:30:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234050AbiFIJ3z (ORCPT ); Thu, 9 Jun 2022 05:29:55 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84EFC267CD2 for ; Thu, 9 Jun 2022 02:29:54 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id fd25so30417827edb.3 for ; Thu, 09 Jun 2022 02:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JeSI4uQxR2QJYLMBJ1DqLjl1fY9poS8Q+KM6xI9FOz4=; b=f0Ck0il7HMPwkoG6M1COIc/Igd98jl1VfQkKdJy4S/qTGJhIxDuXVvtJo9nEZazlSX uwVhHnSmPw6cr9j0zHGdhRmujf10aBH6FMCKl5wkykfv/xQg5bTB7Snaj8HnpXcTFSkT eKnMB9BxkbOb4jngECD7mXncmSblVDcmMIQOyEKglg+8VC6DfBt/3srtqWSBFbIatgG1 FPQMznt8deXN8b1yGhpdbrumdayW3OZ86yZbkXu6yc2joRbFgqQtS+E3R8cn+9nPK5A+ NEjSZJgHMAxc9NGtyxhSLI7dyDNoARgORFQUgRCRJikDEqFJneKlyjegmvTDrAIo2tDU uecA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JeSI4uQxR2QJYLMBJ1DqLjl1fY9poS8Q+KM6xI9FOz4=; b=jeDfr8+hj82M+AfEK2Z3DEWpdviz1NC5kkJrJ/YWyWbrIkmRBnk2wv29JjQTzsSRnZ xQuxaHo26h/uJ2pLIkSBg0g7kKVWCbqixKbO5erRtDxe/cV1DoW3rdpWEK7klGYcXaFa XVaEJCgoYrW+RkrQUYeEcm10VG5OCimirTJGheHWDsFJzE5EriW58Vpv19lVyWPlz815 LGV/xRkj8ZaYSCDx9EOpjksi+eprUFLlQceuIp5VaQlpCcQ/Blwa+VUc9d525OHoNs11 s8nn+jiGnpZb0z0MQ20zGaaAbPOF63SaE8kpaUIgYDDQ88UMKs2dIWYzF97pYJ4KmBI8 PhBg== X-Gm-Message-State: AOAM533CZ9pkn30+4oPqNx510ppetlsLNP6zIjhBt+Y3UhrbzRApwKCT 57xqYt3vJijUm+FAz3xHwxP+IQ== X-Google-Smtp-Source: ABdhPJyMQf7bVUF7T8t94AiIgb/4gHLlxihQ+nlVbUR0Oa2i2+oloZZh8upehaCbMBPUSYbOtks4hg== X-Received: by 2002:a05:6402:1d4a:b0:42e:93de:17f4 with SMTP id dz10-20020a0564021d4a00b0042e93de17f4mr35910158edb.8.1654766993011; Thu, 09 Jun 2022 02:29:53 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:52 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v5 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Date: Thu, 9 Jun 2022 11:29:40 +0200 Message-Id: <20220609092940.304740-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- Changes since v2 - Remove interconnect include - Bjorn Changes since v3 - Switch from .fw_name to .index arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 52428b6df64e..df0f3dd38f0f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -2525,6 +2526,30 @@ usb_2_dwc3: usb@a800000 { }; }; =20 + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm8350-dispcc"; + reg =3D <0 0x0af00000 0 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + + power-domains =3D <&rpmhpd SM8350_MMCX>; + power-domain-names =3D "mmcx"; + }; + adsp: remoteproc@17300000 { compatible =3D "qcom,sm8350-adsp-pas"; reg =3D <0 0x17300000 0 0x100>; --=20 2.34.1