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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id cr11-20020a056870ebcb00b000f33a37411dsm8554122oab.26.2022.06.07.14.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:38:49 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Jassi Brar Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: mailbox: qcom-ipcc: Add NSP1 client Date: Tue, 7 Jun 2022 14:41:10 -0700 Message-Id: <20220607214113.4057684-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607214113.4057684-1-bjorn.andersson@linaro.org> References: <20220607214113.4057684-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a client for the NSP1 found in some recent Qualcomm platforms. Signed-off-by: Bjorn Andersson Acked-by: Jassi Brar Acked-by: Krzysztof Kozlowski --- Jassi, there's no code dependency on this constant, so it's only going to be referenced from the dts (patch 2/4). I would appreciate if I could get an A= ck and merge this together with the dts changes. include/dt-bindings/mailbox/qcom-ipcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/= mailbox/qcom-ipcc.h index 9296d0bb5f34..fbfa3febc66d 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -30,6 +30,7 @@ #define IPCC_CLIENT_PCIE1 14 #define IPCC_CLIENT_PCIE2 15 #define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_NSP1 18 #define IPCC_CLIENT_TME 23 #define IPCC_CLIENT_WPSS 24 =20 --=20 2.35.1 From nobody Tue Apr 28 02:28:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B56AC43334 for ; Wed, 8 Jun 2022 01:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237300AbiFHBNj (ORCPT ); Tue, 7 Jun 2022 21:13:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575215AbiFGX0z (ORCPT ); Tue, 7 Jun 2022 19:26:55 -0400 Received: from mail-oa1-x2f.google.com (mail-oa1-x2f.google.com [IPv6:2001:4860:4864:20::2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37E4E1C13A for ; Tue, 7 Jun 2022 14:38:56 -0700 (PDT) Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-e5e433d66dso24844504fac.5 for ; Tue, 07 Jun 2022 14:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NY6zrt0/STX9B/nShE9GQqAIWlY3cBIWnmmq7Jl5PbE=; b=abTAITYmb9qhNCib+T7DrRIVfTpsPD0GFfm5Rg1Glp5SjCH0kWXm73zXb0CRNdOXVk MmqT3qlJ5CBkh37rTz8ZI8DyNOjA5Bjn0rkY+4fYKVIAyXK2OO0Sadj/+GjERDLc00se HISbAAv/WOEBBVx8quLOTLzr+4BbyMVrmp77BbmblQSFRQHsD1HsMiCNV1EIK8S/uR5E hAH6B/L2M+2gikARTYPB3dC+aw/wbeDbWiI0RbSpq+tA7SaTZ9/YLpL5ogMfpd6VfKOe i6LqfOS8Nx4jHy35QlmwRiDqbyC2vby47qXveGKF4SbnQUTrikR1loDrN+4t7SwMfsKF sWww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NY6zrt0/STX9B/nShE9GQqAIWlY3cBIWnmmq7Jl5PbE=; b=taLIKp+3ss8P50f+utM4nNtlJtMIfth2qYNOEkkzD+HUfqsCYp7j7tvpaQo/1lJngb VSpENpKhQeKM38oMO9CWs/vm7CHxglvSREGHI+UmbLfts61McTCLOYCDQG4J4J+hUuFD WtW6DeKmakkPGFJMXDhkPomU22j0xj6jv8so1JSJEmXU3j/tqHuMGYopywwgj0+QclRU PftUkGcdZNpcWhtA6+zG4g3ukAHej8LX0h1Qm8lIMaP1ABXMquT9aqNfvHeHQcrgz6NX HQEgO59IosjQhlKESUQ0yX5+WYaXXLJRcMhm5M4Wher8WJq+X4uNpHM4vet8MSG+RsEk EidQ== X-Gm-Message-State: AOAM5316RwD979U1ukP2860TSA4nQsb39htO2cwvxSbQYMdyvq8oOK4P YMrPWHlmMfs0KHQ0beJScMZHqA== X-Google-Smtp-Source: ABdhPJzUrYLBws8J8HnxupNf8i1rVVEh8yykDzXJWrg76MFLCmpgyQayDfBmuCz0ccLOVDIco5stWg== X-Received: by 2002:a05:6870:560d:b0:fb:3917:85a9 with SMTP id m13-20020a056870560d00b000fb391785a9mr590859oao.164.1654637931504; Tue, 07 Jun 2022 14:38:51 -0700 (PDT) Received: from ripper.. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id cr11-20020a056870ebcb00b000f33a37411dsm8554122oab.26.2022.06.07.14.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:38:51 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam Cc: Jassi Brar , Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: qcom: add SC8280XP platform Date: Tue, 7 Jun 2022 14:41:11 -0700 Message-Id: <20220607214113.4057684-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607214113.4057684-1-bjorn.andersson@linaro.org> References: <20220607214113.4057684-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce initial support for the Qualcomm SC8280XP platform, aka 8cx Gen 3. This initial contribution supports SMP, CPUfreq, CPU cluster idling, GCC, TLMM, SMMU, RPMh regulators, power-domains and clocks, interconnects, some QUPs, UFS, remoteprocs, USB, watchdog, LLCC and tsens. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2195 ++++++++++++++++++++++++ 1 file changed, 2195 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi new file mode 100644 index 000000000000..4143813643ad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -0,0 +1,2195 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <38400000>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32764>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + }; + opp-691200000 { + opp-hz =3D /bits/ 64 <691200000>; + }; + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz =3D /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + }; + opp-1996800000 { + opp-hz =3D /bits/ 64 <1996800000>; + }; + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + }; + opp-2227200000 { + opp-hz =3D /bits/ 64 <2227200000>; + }; + opp-2342400000 { + opp-hz =3D /bits/ 64 <2342400000>; + }; + opp-2438400000 { + opp-hz =3D /bits/ 64 <2438400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz =3D /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz =3D /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz =3D /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz =3D /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz =3D /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz =3D /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz =3D /bits/ 64 <2284800000>; + }; + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + }; + opp-2496000000 { + opp-hz =3D /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + }; + opp-2688000000 { + opp-hz =3D /bits/ 64 <2688000000>; + }; + opp-2803200000 { + opp-hz =3D /bits/ 64 <2803200000>; + }; + opp-2899200000 { + opp-hz =3D /bits/ 64 <2899200000>; + }; + opp-2995200000 { + opp-hz =3D /bits/ 64 <2995200000>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_0>; + power-domains =3D <&CPU_PD0>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_100>; + power-domains =3D <&CPU_PD1>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_100: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_200>; + power-domains =3D <&CPU_PD2>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_200: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_300>; + power-domains =3D <&CPU_PD3>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + L2_300: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_400>; + power-domains =3D <&CPU_PD4>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_400: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_500>; + power-domains =3D <&CPU_PD5>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_500: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_600>; + power-domains =3D <&CPU_PD6>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_600: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_700>; + power-domains =3D <&CPU_PD7>; + power-domain-names =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + #cooling-cells =3D <2>; + L2_700: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + + core4 { + cpu =3D <&CPU4>; + }; + + core5 { + cpu =3D <&CPU5>; + }; + + core6 { + cpu =3D <&CPU6>; + }; + + core7 { + cpu =3D <&CPU7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <355>; + exit-latency-us =3D <909>; + min-residency-us =3D <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <241>; + exit-latency-us =3D <1461>; + min-residency-us =3D <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + idle-state-name =3D "cluster-power-collapse"; + arm,psci-suspend-param =3D <0x4100c344>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9987>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sc8280xp", "qcom,scm"; + }; + }; + + aggre1_noc: interconncet-aggre1-noc { + compatible =3D "qcom,sc8280xp-aggre1-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible =3D "qcom,sc8280xp-aggre2-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,sc8280xp-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible =3D "qcom,sc8280xp-config-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible =3D "qcom,sc8280xp-dc-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible =3D "qcom,sc8280xp-gem-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_noc: interconnect-lpass-ag-noc { + compatible =3D "qcom,sc8280xp-lpass-ag-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible =3D "qcom,sc8280xp-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible =3D "qcom,sc8280xp-mmss-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible =3D "qcom,sc8280xp-nspa-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible =3D "qcom,sc8280xp-nspb-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible =3D "qcom,sc8280xp-system-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&CLUSTER_SLEEP_0>; + }; + }; + + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + memory@80000000 { + reg =3D <0 0x80000000 0 0x860000>; + no-map; + }; + + cmd_db: memory@80860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0 0x80860000 0 0x20000>; + no-map; + }; + + memory@80880000 { + reg =3D <0 0x80880000 0 0x80000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible =3D "qcom,smem"; + reg =3D <0 0x80900000 0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + memory@80b00000 { + reg =3D <0 0x80b00000 0 0x100000>; + no-map; + }; + + memory@83b00000 { + reg =3D <0 0x83b00000 0 0x1700000>; + no-map; + }; + + memory@85b00000 { + reg =3D <0 0x85b00000 0 0xc00000>; + no-map; + }; + + pil_adsp_mem: memory@86c00000 { + reg =3D <0 0x86c00000 0 0x2000000>; + no-map; + }; + + pil_nsp0_mem: memory@8a100000 { + reg =3D <0 0x8a100000 0 0x1e00000>; + no-map; + }; + + pil_nsp1_mem: memory@8c600000 { + reg =3D <0 0x8c600000 0 0x1e00000>; + no-map; + }; + + memory@aeb00000 { + reg =3D <0 0xaeb00000 0 0x16600000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-nsp0 { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_nsp0_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_nsp0_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-nsp1 { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <617>, <616>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <12>; + + smp2p_nsp1_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_nsp1_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + compatible =3D "simple-bus"; + + gcc: clock-controller@100000 { + compatible =3D "qcom,gcc-sc8280xp"; + reg =3D <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_0_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_1_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + }; + + ipcc: mailbox@408000 { + compatible =3D "qcom,sc8280xp-ipcc", "qcom,ipcc"; + reg =3D <0 0x00408000 0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + qup2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x008c0000 0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0xa3 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + qup2_uart17: serial@884000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00884000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + qup2_i2c5: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + }; + + qup0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x009c0000 0 0x6000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0x563 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + qup0_i2c4: i2c@990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00990000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + }; + + qup1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x00ac0000 0 0x6000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0x83 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0 0x01d84000 0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0xe0 0x0>; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,sc8280xp-qmp-ufs-phy"; + reg =3D <0 0x01d87000 0 0xe10>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clock-names =3D "ref", + "ref_aux"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + status =3D "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg =3D <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + }; + }; + + ufs_card_hc: ufshc@1da4000 { + compatible =3D "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0 0x01da4000 0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_card_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_CARD_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc UFS_CARD_GDSC>; + + iommus =3D <&apps_smmu 0x4a0 0x0>; + + clocks =3D <&gcc GCC_UFS_CARD_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_UFS_CARD_AHB_CLK>, + <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status =3D "disabled"; + }; + + ufs_card_phy: phy@1da7000 { + compatible =3D "qcom,sc8280xp-qmp-ufs-phy"; + reg =3D <0 0x01da7000 0 0xe10>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clock-names =3D "ref", + "ref_aux"; + clocks =3D <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; + + resets =3D <&ufs_card_hc 0>; + reset-names =3D "ufsphy"; + status =3D "disabled"; + + ufs_card_phy_lanes: phy@1da7400 { + reg =3D <0 0x01da7400 0 0x108>, + <0 0x01da7600 0 0x1e0>, + <0 0x01da7c00 0 0x1dc>, + <0 0x01da7800 0 0x108>, + <0 0x01da7a00 0 0x1e0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + usb_0_hsphy: phy@88e5000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e5000 0 0x400>; + status =3D "disabled"; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy0: phy@88e7000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e7000 0 0x400>; + status =3D "disabled"; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + }; + + usb_2_hsphy1: phy@88e8000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e8000 0 0x400>; + status =3D "disabled"; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB2_HS1_CLKREF_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + }; + + usb_2_hsphy2: phy@88e9000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e9000 0 0x400>; + status =3D "disabled"; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB2_HS2_CLKREF_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; + }; + + usb_2_hsphy3: phy@88ea000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088ea000 0 0x400>; + status =3D "disabled"; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB2_HS3_CLKREF_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; + }; + + usb_2_qmpphy0: phy-wrapper@88ef000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088ef000 0 0x1c8>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + usb_2_ssphy0: phy@88efe00 { + reg =3D <0 0x088efe00 0 0x160>, + <0 0x088f0000 0 0x1ec>, + <0 0x088ef200 0 0x1f0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb2_phy0_pipe_clk"; + }; + }; + + usb_2_qmpphy1: phy-wrapper@88f1000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088f1000 0 0x1c8>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + usb_2_ssphy1: phy@88efe00 { + reg =3D <0 0x088f1e00 0 0x160>, + <0 0x088f2000 0 0x1ec>, + <0 0x088f1200 0 0x1f0>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb2_phy1_pipe_clk"; + }; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,sc8280xp-adsp-pas"; + reg =3D <0 0x03000000 0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names =3D "lcx", "lmx"; + + memory-region =3D <&pil_adsp_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + }; + }; + + usb_0_qmpphy: phy-wrapper@88ec000 { + compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; + reg =3D <0 0x088ec000 0 0x1e4>, + <0 0x088eb000 0 0x40>, + <0 0x088ed000 0 0x1c8>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_EUD_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + usb_0_ssphy: usb3-phy@88e9200 { + reg =3D <0 0x088eb400 0 0x100>, + <0 0x088eb600 0 0x3ec>, + <0 0x088ec400 0 0x1f0>, + <0 0x088eba00 0 0x100>, + <0 0x088ebc00 0 0x3ec>, + <0 0x088ec700 0 0x64>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb0_phy_pipe_clk_src"; + }; + + usb_0_dpphy: dp-phy@88ed200 { + reg =3D <0 0x088ed200 0 0x200>, + <0 0x088ed400 0 0x200>, + <0 0x088eda00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; + + usb_1_hsphy: phy@8902000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x08902000 0 0x400>; + status =3D "disabled"; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@8904000 { + compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; + reg =3D <0 0x08904000 0 0x1e4>, + <0 0x08903000 0 0x40>, + <0 0x08905000 0 0x1c8>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + + resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", "common"; + + power-domains =3D <&gcc USB30_SEC_GDSC>; + + usb_1_ssphy: usb3-phy@88e9200 { + reg =3D <0 0x08903400 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904400 0 0x1f0>, + <0 0x08903a00 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904200 0 0x18>; + #phy-cells =3D <0>; + #clock-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb1_phy_pipe_clk_src"; + }; + + usb_1_dpphy: dp-phy@88ed200 { + reg =3D <0 0x08904200 0 0x200>, + <0 0x08904400 0 0x200>, + <0 0x08904a00 0 0x200>, + <0 0x08904600 0 0x200>, + <0 0x08904800 0 0x200>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; + + usb_2: usb@a4f8800 { + compatible =3D "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a4f8800 0 0x400>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names =3D "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks =3D <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&pdc 127 IRQ_TYPE_EDGE_RISING>, + <&pdc 126 IRQ_TYPE_EDGE_RISING>, + <&pdc 129 IRQ_TYPE_EDGE_RISING>, + <&pdc 128 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + resets =3D <&gcc GCC_USB30_MP_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + usb_2_dwc3: usb@a800000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a400000 0 0xd93c>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x800 0x0>; + phys =3D <&usb_2_hsphy0>, <&usb_2_ssphy0>; + phy-names =3D "usb2-phy", "usb3-phy"; + /* + * TODO: Link controller to all 6 phys. + * phys =3D <&usb_2_hsphy0>, <&usb_2_ssphy0>, + * <&usb_2_hsphy1>, <&usb_2_ssphy1>, + * <&usb_2_hsphy2>, + * <&usb_2_hsphy3>; + * phy-names =3D "usb2-phy", "usb3-phy"; + */ + }; + }; + + usb_0: usb@a6f8800 { + compatible =3D "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a6f8800 0 0x400>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names =3D "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + usb_0_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a600000 0 0xcd00>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x820 0x0>; + phys =3D <&usb_0_hsphy>, <&usb_0_ssphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; + + usb_1: usb@a8f8800 { + compatible =3D "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a8f8800 0 0x400>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names =3D "core", "iface", "bus_aggr", "utmi", "sleep", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks =3D <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains =3D <&gcc USB30_SEC_GDSC>; + + resets =3D <&gcc GCC_USB30_SEC_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + usb_1_dwc3: usb@a800000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a800000 0 0xcd00>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x860 0x0>; + phys =3D <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; + + system-cache-controller@9200000 { + compatible =3D "qcom,sc8280xp-llcc"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; + reg-names =3D "llcc_base", "llcc_broadcast_base"; + interrupts =3D ; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sc8280xp-pdc", "qcom,pdc"; + reg =3D <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges =3D <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 3>, + <69 86 1>, + <70 520 54>, + <124 609 28>, + <159 638 1>, + <160 720 8>, + <168 801 1>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 1>, + <216 646 5>, + <221 390 5>, + <226 700 3>, + <229 240 3>, + <232 269 1>, + <233 377 1>, + <234 372 1>, + <235 138 1>, + <236 857 1>, + <237 860 1>, + <238 137 1>, + <239 668 1>, + <240 366 1>, + <241 949 1>, + <242 815 5>, + <247 769 1>, + <248 768 1>, + <249 663 1>, + <250 799 2>, + <252 798 1>, + <253 765 1>, + <254 763 1>, + <255 454 1>, + <258 139 1>, + <259 786 2>, + <261 370 2>, + <263 158 2>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible =3D "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors =3D <14>; + interrupts-extended =3D <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible =3D "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts-extended =3D <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible =3D "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0 0x0c300000 0 0x400>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + spmi_bus: spmi@c440000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,sc8280xp-tlmm"; + reg =3D <0 0x0f100000 0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 230>; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sc8280xp-smmu-500", "arm,mmu-500"; + reg =3D <0 0x15000000 0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts =3D ; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0 0x20000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic-its@17a40000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0 0x17a40000 0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17c10000 { + compatible =3D "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; + reg =3D <0 0x17c10000 0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + clock-frequency =3D <19200000>; + + frame@17c21000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x0 0x17c21000 0x0 0x1000>, + <0x0 0x17c22000 0x0 0x1000>; + }; + + frame@17c23000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0 0x17c23000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17c25000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0 0x17c25000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17c27000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0 0x17c26000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17c29000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0 0x17c29000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17c2b000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0 0x17c2b000 0x0 0x1000>; + status =3D "disabled"; + }; + + frame@17c2d000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x0 0x17c2d000 0x0 0x1000>; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sc8280xp-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sc8280xp-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible =3D "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + }; + + remoteproc_nsp0: remoteproc@1b300000 { + compatible =3D "qcom,sc8280xp-nsp0-pas"; + reg =3D <0 0x1b300000 0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_NSP>; + power-domain-names =3D "nsp"; + + memory-region =3D <&pil_nsp0_mem>; + + qcom,smem-states =3D <&smp2p_nsp0_out 0>; + qcom,smem-state-names =3D "stop"; + + interconnects =3D <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "nsp0"; + qcom,remote-pid =3D <5>; + + fastrpc { + compatible =3D "qcom,fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x3181 0x0420>; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x3182 0x0420>; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x3183 0x0420>; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x3184 0x0420>; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x3185 0x0420>; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x3186 0x0420>; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu 0x3187 0x0420>; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu 0x3188 0x0420>; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@10 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <10>; + iommus =3D <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@11 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <11>; + iommus =3D <&apps_smmu 0x318c 0x0420>; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu 0x318d 0x0420>; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu 0x318e 0x0420>; + }; + + compute-cb@14 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <14>; + iommus =3D <&apps_smmu 0x318f 0x0420>; + }; + }; + }; + }; + + remoteproc_nsp1: remoteproc@21300000 { + compatible =3D "qcom,sc8280xp-nsp1-pas"; + reg =3D <0 0x21300000 0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_NSP>; + power-domain-names =3D "nsp"; + + memory-region =3D <&pil_nsp1_mem>; + + qcom,smem-states =3D <&smp2p_nsp1_out 0>; + qcom,smem-state-names =3D "stop"; + + interconnects =3D <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0= >; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "nsp1"; + qcom,remote-pid =3D <12>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + mem-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 15>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; +}; --=20 2.35.1 From nobody Tue Apr 28 02:28:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA8D4CCA483 for ; Wed, 8 Jun 2022 02:14:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1444203AbiFHCJ4 (ORCPT ); Tue, 7 Jun 2022 22:09:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575172AbiFGX0w (ORCPT ); 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id cr11-20020a056870ebcb00b000f33a37411dsm8554122oab.26.2022.06.07.14.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:38:51 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam Cc: Jassi Brar , Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: qcom: sc8280x: Add reference device Date: Tue, 7 Jun 2022 14:41:12 -0700 Message-Id: <20220607214113.4057684-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607214113.4057684-1-bjorn.andersson@linaro.org> References: <20220607214113.4057684-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add basic support for the SC8280XP reference device, which allows it to boot to a shell (using EFIFB) with functional storage (UFS), USB, keyboard, touchpad, touchscreen, backlight and remoteprocs. The PMICs are, per socinfo, reused from other platforms. But given that the address of the PMICs doesn't match other cases and that it's desirable to label things according to the schematics a new dtsi file is created to represent the reference combination of PMICs. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 423 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 108 +++++ 3 files changed, 532 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 2f8aec2cc6db..ceeae094a59f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-villager-r0= .dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts new file mode 100644 index 000000000000..1031ee039107 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/ { + model =3D "Qualcomm SC8280XP CRD"; + compatible =3D "qcom,sc8280xp-crd", "qcom,sc8280xp"; + + aliases { + serial0 =3D &qup2_uart17; + }; + + backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pmc8280c_lpg 3 1000000>; + enable-gpios =3D <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply =3D <&vreg_edp_bl>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_bl_en>, <&edp_bl_pwm>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + vreg_edp_bl: edp-bl-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_EDP_BL"; + + regulator-min-microvolt =3D <3600000>; + regulator-max-microvolt =3D <3600000>; + + gpio =3D <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: misc-3p3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_MISC_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8280_1_gpios 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + + reserved-memory { + }; +}; + +&apps_rsc { + pmc8280-1-rpmh-regulators { + compatible =3D "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-l3-l5-supply =3D <&vreg_s11b>; + + vreg_s11b: smps11 { + regulator-name =3D "vreg_s11b"; + regulator-min-microvolt =3D <1272000>; + regulator-max-microvolt =3D <1272000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l6b: ldo6 { + regulator-name =3D "vreg_l6b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-boot-on; + }; + }; + + pmc8280c-rpmh-regulators { + compatible =3D "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l13c: ldo13 { + regulator-name =3D "vreg_l13c"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + + pmc8280-2-rpmh-regulators { + compatible =3D "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-l4-supply =3D <&vreg_s11b>; + + vreg_l3d: ldo3 { + regulator-name =3D "vreg_l3d"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l4d: ldo4 { + regulator-name =3D "vreg_l4d"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l6d: ldo6 { + regulator-name =3D "vreg_l6d"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7d: ldo7 { + regulator-name =3D "vreg_l7d"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l9d: ldo9 { + regulator-name =3D "vreg_l9d"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + +}; + +&pmc8280c_lpg { + status =3D "okay"; +}; + +&pmk8280_pon_pwrkey { + status =3D "okay"; +}; + +&qup0 { + status =3D "okay"; +}; + +&qup0_i2c4 { + status =3D "okay"; + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup0_i2c4_default>, <&ts0_default>; + + hid@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + hid-descr-addr =3D <0x1>; + + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&qup1 { + status =3D "okay"; +}; + +&qup2 { + status =3D "okay"; +}; + +&qup2_i2c5 { + status =3D "okay"; + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + + hid@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + hid-descr-addr =3D <0x1>; + + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + }; + + hid@68 { + compatible =3D "hid-over-i2c"; + reg =3D <0x68>; + hid-descr-addr =3D <0x1>; + + interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&qup2_uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +&remoteproc_adsp { + status =3D "okay"; + firmware-name =3D "qcom/sc8280xp/qcadsp8280.mbn"; +}; + +&remoteproc_nsp0 { + status =3D "okay"; + firmware-name =3D "qcom/sc8280xp/qccdsp8280.mbn"; +}; + +&ufs_mem_hc { + status =3D "okay"; + + reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l7c>; + vcc-max-microamp =3D <800000>; + vccq-supply =3D <&vreg_l3d>; + vccq-max-microamp =3D <900000>; +}; + +&ufs_mem_phy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l6b>; + vdda-pll-supply =3D <&vreg_l3b>; +}; + +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "host"; +}; + +&usb_0_hsphy { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l9d>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l7d>; +}; + +&usb_0_qmpphy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l9d>; + vdda-pll-supply =3D <&vreg_l4d>; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l4b>; + vdda18-supply =3D <&vreg_l1c>; + vdda33-supply =3D <&vreg_l13c>; +}; + +&usb_1_qmpphy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l4b>; + vdda-pll-supply =3D <&vreg_l3b>; +}; + +/* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ + +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins =3D "gpio8"; + function =3D "normal"; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins =3D "gpio9"; + function =3D "normal"; + }; + + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins =3D "gpio1"; + function =3D "normal"; + }; +}; + +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins =3D "gpio8"; + function =3D "func1"; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + + kybd_default: kybd-default-state { + disable { + pins =3D "gpio102"; + function =3D "gpio"; + output-low; + }; + + int-n { + pins =3D "gpio104"; + function =3D "gpio"; + bias-disable; + }; + + reset { + pins =3D "gpio105"; + function =3D "gpio"; + bias-disable; + }; + }; + + qup0_i2c4_default: qup0-i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + + bias-disable; + drive-strength =3D <16>; + }; + + qup2_i2c5_default: qup2-i2c5-default-state { + pins =3D "gpio81", "gpio82"; + function =3D "qup21"; + + bias-disable; + drive-strength =3D <16>; + }; + + tpad_default: tpad-default-state { + int-n { + pins =3D "gpio182"; + function =3D "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + int-n { + pins =3D "gpio175"; + function =3D "gpio"; + bias-pull-up; + }; + + reset-n { + pins =3D "gpio99"; + function =3D "gpio"; + output-high; + drive-strength =3D <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot= /dts/qcom/sc8280xp-pmics.dtsi new file mode 100644 index 000000000000..36ed7d808ab8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +&spmi_bus { + pmk8280: pmic@0 { + compatible =3D "qcom,pmk8350", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmk8280_pon: pon@1300 { + compatible =3D "qcom,pm8998-pon"; + reg =3D <0x1300>; + + pmk8280_pon_pwrkey: pwrkey { + compatible =3D "qcom,pmk8350-pwrkey"; + interrupts =3D <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code =3D ; + status =3D "disabled"; + }; + }; + }; + + pmc8280_1: pmic@1 { + compatible =3D "qcom,pm8350", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmc8280_1_gpios: gpio@8800 { + compatible =3D "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmc8280_1_gpios 0 0 10>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmc8280c: pmic@2 { + compatible =3D "qcom,pm8350c", "qcom,spmi-pmic"; + reg =3D <0x2 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmc8280c_gpios: gpio@8800 { + compatible =3D "qcom,pm8350c-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmc8280c_gpios 0 0 9>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pmc8280c_lpg: lpg@e800 { + compatible =3D "qcom,pm8350c-pwm"; + reg =3D <0xe800>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + #pwm-cells =3D <2>; + + status =3D "disabled"; + }; + }; + + pmc8280_2: pmic@3 { + compatible =3D "qcom,pm8350", "qcom,spmi-pmic"; + reg =3D <0x3 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmc8280_2_gpios: gpio@8800 { + compatible =3D "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmc8280_2_gpios 0 0 10>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmr735a: pmic@4 { + compatible =3D "qcom,pmr735a", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmr735a_gpios: gpio@8800 { + compatible =3D "qcom,pmr735a-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmr735a_gpios 0 0 4>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.35.1 From nobody Tue Apr 28 02:28:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 070AEC04E85 for ; Wed, 8 Jun 2022 00:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1391971AbiFHAvk (ORCPT ); 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id cr11-20020a056870ebcb00b000f33a37411dsm8554122oab.26.2022.06.07.14.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:38:52 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam Cc: Jassi Brar , Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: qcom: add SA8540P and ADP Date: Tue, 7 Jun 2022 14:41:13 -0700 Message-Id: <20220607214113.4057684-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607214113.4057684-1-bjorn.andersson@linaro.org> References: <20220607214113.4057684-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce the Qualcomm SA8540P automotive platform and the SA8295P ADP development board. The SA8540P and SC8280XP are fairly similar, so the SA8540P is built ontop of the SC8280XP dtsi to reduce duplication. As more advanced features are integrated this might be re-evaluated. This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh regulators, debug UART, PMICs, remoteprocs (NSPs crashes shortly after booting) and USB. The SA8295P ADP contains four PM8450 PMICs, which according to their revid are compatible with PM8150. They are defined within the ADP for now, to avoid creating additional .dtsi files for PM8150 with just addresses changed - and to allow using the labels from the schematics. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 434 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8540p.dtsi | 133 +++++++ 3 files changed, 568 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8295p-adp.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8540p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ceeae094a59f..2f416b84b71c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8295p-adp.dts new file mode 100644 index 000000000000..f78203d7bfd2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "sa8540p.dtsi" + +/ { + model =3D "Qualcomm SA8295P ADP"; + compatible =3D "qcom,sa8295p-adp", "qcom,sa8540p"; + + aliases { + serial0 =3D &qup2_uart17; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reserved-memory { + }; +}; + +&apps_rsc { + pmm8540-a-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1208000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l13a: ldo13 { + regulator-name =3D "vreg_l13a"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + + pmm8540-c-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l3c: ldo3 { + regulator-name =3D "vreg_l3c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1208000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l10c: ldo10 { + regulator-name =3D "vreg_l10c"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l17c: ldo17 { + regulator-name =3D "vreg_l17c"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; + + pmm8540-g-regulators { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vreg_l3g: ldo3 { + regulator-name =3D "vreg_l3g"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l7g: ldo7 { + regulator-name =3D "vreg_l7g"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + + vreg_l8g: ldo8 { + regulator-name =3D "vreg_l8g"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + }; + }; +}; + +&qup2 { + status =3D "okay"; +}; + +&qup2_uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +&remoteproc_adsp { + status =3D "okay"; + firmware-name =3D "qcom/sa8540p/adsp.mbn"; +}; + +&remoteproc_nsp0 { + status =3D "okay"; + firmware-name =3D "qcom/sa8540p/cdsp.mbn"; +}; + +&remoteproc_nsp1 { + status =3D "okay"; + firmware-name =3D "qcom/sa8540p/cdsp1.mbn"; +}; + +&spmi_bus { + pm8450a: pmic@0 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450a_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8450c: pmic@4 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450c_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8450e: pmic@8 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x8 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450e_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pm8450g: pmic@c { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0xc SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8450g_gpios: gpio@c000 { + compatible =3D "qcom,pm8150-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; + +&ufs_mem_hc { + status =3D "okay"; + + reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17c>; + vcc-max-microamp =3D <800000>; + vccq-supply =3D <&vreg_l6c>; + vccq-max-microamp =3D <900000>; +}; + +&ufs_mem_phy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l8g>; + vdda-pll-supply =3D <&vreg_l3g>; +}; + +&ufs_card_hc { + status =3D "okay"; + + reset-gpios =3D <&tlmm 229 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l10c>; + vcc-max-microamp =3D <800000>; + vccq-supply =3D <&vreg_l3c>; + vccq-max-microamp =3D <900000>; +}; + +&ufs_card_phy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l8g>; + vdda-pll-supply =3D <&vreg_l3g>; +}; + +&usb_0 { + status =3D "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "peripheral"; +}; + +&usb_0_hsphy { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7a>; + vdda33-supply =3D <&vreg_l13a>; +}; + +&usb_0_qmpphy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l3a>; + vdda-pll-supply =3D <&vreg_l5a>; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l1c>; + vdda18-supply =3D <&vreg_l7c>; + vdda33-supply =3D <&vreg_l2c>; +}; + +&usb_1_qmpphy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l4c>; + vdda-pll-supply =3D <&vreg_l1c>; +}; + +&usb_2 { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb2_en_state>, <&usb3_en_state>, <&usb4_en_state>, <&usb= 5_en_state>; +}; + +&usb_2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_2_hsphy0 { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; +}; + +&usb_2_hsphy1 { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; +}; + +&usb_2_hsphy2 { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; +}; + +&usb_2_hsphy3 { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l5a>; + vdda18-supply =3D <&vreg_l7g>; + vdda33-supply =3D <&vreg_l13a>; +}; + +&usb_2_qmpphy0 { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l3a>; + vdda-pll-supply =3D <&vreg_l5a>; +}; + +&usb_2_qmpphy1 { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l3a>; + vdda-pll-supply =3D <&vreg_l5a>; +}; + +/* PINCTRL */ +&pm8450c_gpios { + usb2_en_state: usb2-en-state { + pins =3D "gpio9"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; + +&pm8450e_gpios { + usb3_en_state: usb3-en-state { + pins =3D "gpio5"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; + +&pm8450g_gpios { + usb4_en_state: usb4-en-state { + pins =3D "gpio5"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; + + usb5_en_state: usb5-en-state { + pins =3D "gpio9"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qc= om/sa8540p.dtsi new file mode 100644 index 000000000000..8ea2886fbab2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include "sc8280xp.dtsi" + +/delete-node/ &cpu0_opp_table; +/delete-node/ &cpu4_opp_table; + +/ { + cpu0_opp_table: cpu0-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz =3D /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + }; + opp-710400000 { + opp-hz =3D /bits/ 64 <710400000>; + }; + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz =3D /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + }; + opp-2131200000 { + opp-hz =3D /bits/ 64 <2131200000>; + }; + opp-2246400000 { + opp-hz =3D /bits/ 64 <2246400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz =3D /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz =3D /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz =3D /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz =3D /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz =3D /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz =3D /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz =3D /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz =3D /bits/ 64 <2284800000>; + }; + opp-2380800000 { + opp-hz =3D /bits/ 64 <2380800000>; + }; + opp-2496000000 { + opp-hz =3D /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + }; + }; +}; + +&rpmhpd { + compatible =3D "qcom,sa8540p-rpmhpd"; +}; --=20 2.35.1