From nobody Tue Apr 28 02:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DE2CC43334 for ; Tue, 7 Jun 2022 16:39:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345107AbiFGQjk (ORCPT ); Tue, 7 Jun 2022 12:39:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345087AbiFGQji (ORCPT ); Tue, 7 Jun 2022 12:39:38 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46338C8BD1; Tue, 7 Jun 2022 09:39:37 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id q12-20020a17090a304c00b001e2d4fb0eb4so21316769pjl.4; Tue, 07 Jun 2022 09:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mnuX2XuAZH2+4k0j70brZ2CKznHIP3JRJnTSoZMTWkg=; b=cjrZ07iwc2EALTYW1XrWSK/VzNuGI2H/RL1mBuzHM2OYSp3yL3HqqgekI3npRRr+7Q vh6T5/5vsGE3XklV73vEFl+Yqm4KMfU5sSygWTGupnJvL1YzsOi0Bq3VCiDVFdtplgcW AI74ppgBbW5fTiK8WHAIdVdKWpk7N7QCocGSxXZ4/4rDJKYuPXrG7UHKALDk1HXEdJWR XMBUq1XJQs0CcXXsXDfA7klOA16ZqfiRnyF1PlGq/BiSZ5QRcOnNm57AB/yRzIB6zMxi Lm0Qg72j2yiX7s+hUQPYyVM1WKucepwbLF/4L6bc/eurH7xYn9sbduzcD7b3bzCoET+S XugQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mnuX2XuAZH2+4k0j70brZ2CKznHIP3JRJnTSoZMTWkg=; b=OtYpva4jn4bcd+JrqaNllwT6ziTUPOtGj7KEAB4d4yOy3MYuDFZFwPPUrbGVqt8Y/Y 6kSBPwV5R4EZlyUj+ivTB4n4m3Mqd8JAiQ1lNMQ+SOwy820cdFzx1L/Wlk4FsJGSGkkK bwBOypjM4trP+6fsCDQM5Nz459quLVq83xeBDFt1Txb/0WmdW/YCnFo38PX4EKHFEaLY bDCKRroQ2eDxGIYctkNnKhiV48DLLboST7bawFI91sJFMxX76kajgpkvRKRzKJ+fZyxf vPvqei9Ma+oxubiGgNPgFznA59ja97yNANQbZIq48fi8f2a4/qEFUYFuqHmoWPIgk4lA qikA== X-Gm-Message-State: AOAM531wUbphjkBVTfdo147duW03a53o1JTOgWeTi00gjLkockUD9FoK 7hxwWI5BkWmfwmRqWWWoNzg= X-Google-Smtp-Source: ABdhPJww6wXD/7mS2SvdH5jDFtcbiEE6U8bBZ8OHhGKV6nDUwaPh058LyFjaR41wIulAkCXHnCPLKA== X-Received: by 2002:a17:90a:a096:b0:1df:58d7:5b20 with SMTP id r22-20020a17090aa09600b001df58d75b20mr32805835pjp.212.1654619976713; Tue, 07 Jun 2022 09:39:36 -0700 (PDT) Received: from potin-quanta.dhcpserver.local (125-228-123-29.hinet-ip.hinet.net. [125.228.123.29]) by smtp.gmail.com with ESMTPSA id d15-20020aa797af000000b0051bbc198f3fsm12560272pfq.13.2022.06.07.09.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 09:39:36 -0700 (PDT) From: Potin Lai To: Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Andrew Jeffery , Rob Herring , Rayn Chen Cc: Patrick Williams , Potin Lai , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Potin Lai Subject: [PATCH v3 1/2] aspeed: i2c: add clock duty cycle property Date: Wed, 8 Jun 2022 00:37:02 +0800 Message-Id: <20220607163703.26355-2-potin.lai.pt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220607163703.26355-1-potin.lai.pt@gmail.com> References: <20220607163703.26355-1-potin.lai.pt@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce i2c-clk-duty-cycle property for setting a minimum clock high percentage. This driver calculate clk_high and clk_low with giving duty cycle. If it could not find a suit clk_high and clk_low, it apply default duty cycle 50%. Signed-off-by: Potin Lai --- drivers/i2c/busses/i2c-aspeed.c | 56 ++++++++++++++++++++++++++------- 1 file changed, 45 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspee= d.c index 67e8b97c0c95..825d23f79be7 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,8 @@ #include #include =20 +#define DEFAULT_I2C_CLK_DUTY_CYCLE 50 + /* I2C Register */ #define ASPEED_I2C_FUN_CTRL_REG 0x00 #define ASPEED_I2C_AC_TIMING_REG1 0x04 @@ -149,9 +152,11 @@ struct aspeed_i2c_bus { spinlock_t lock; struct completion cmd_complete; u32 (*get_clk_reg_val)(struct device *dev, - u32 divisor); + u32 divisor, + u32 duty_cycle); unsigned long parent_clk_frequency; u32 bus_frequency; + u32 duty_cycle; /* Transaction state. */ enum aspeed_i2c_master_state master_state; struct i2c_msg *msgs; @@ -798,9 +803,11 @@ static const struct i2c_algorithm aspeed_i2c_algo =3D { =20 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev, u32 clk_high_low_mask, - u32 divisor) + u32 divisor, + u32 duty_cycle) { u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp; + u32 tmp_base_clk_divisor; =20 /* * SCL_high and SCL_low represent a value 1 greater than what is stored @@ -842,10 +849,32 @@ static u32 aspeed_i2c_get_clk_reg_val(struct device *= dev, "clamping clock divider: divider requested, %u, is greater than largest= possible divider, %u.\n", divisor, (1 << base_clk_divisor) * clk_high_low_max); } else { - tmp =3D (divisor + (1 << base_clk_divisor) - 1) + for (tmp_base_clk_divisor =3D base_clk_divisor; + tmp_base_clk_divisor <=3D ASPEED_I2CD_TIME_BASE_DIVISOR_MASK; + tmp_base_clk_divisor++) { + /* calculate clk_high and clk_low with duty cycle */ + tmp =3D (divisor + (1 << tmp_base_clk_divisor) - 1) + >> tmp_base_clk_divisor; + + clk_high =3D DIV_ROUND_UP(tmp * duty_cycle, 100); + clk_low =3D tmp - clk_high; + + if (max(clk_high, clk_low) <=3D (clk_high_low_mask + 1)) + break; + } + + if (tmp_base_clk_divisor <=3D ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) + base_clk_divisor =3D tmp_base_clk_divisor; + else { + dev_err(dev, + "could not find clk_high and clk_low with duty cycle %u%%\n, recalcula= te with base_clk_divisor %u and duty_cycle 50%%", + duty_cycle, base_clk_divisor); + duty_cycle =3D 50; + tmp =3D (divisor + (1 << base_clk_divisor) - 1) >> base_clk_divisor; - clk_low =3D tmp / 2; - clk_high =3D tmp - clk_low; + clk_high =3D DIV_ROUND_UP(tmp * duty_cycle, 100); + clk_low =3D tmp - clk_high; + } =20 if (clk_high) clk_high--; @@ -863,22 +892,22 @@ static u32 aspeed_i2c_get_clk_reg_val(struct device *= dev, & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK); } =20 -static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor) +static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor= , u32 duty_cycle) { /* * clk_high and clk_low are each 3 bits wide, so each can hold a max * value of 8 giving a clk_high_low_max of 16. */ - return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor); + return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor, duty_cycle= ); } =20 -static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor) +static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor= , u32 duty_cycle) { /* * clk_high and clk_low are each 4 bits wide, so each can hold a max * value of 16 giving a clk_high_low_max of 32. */ - return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor); + return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor, duty_cycle= ); } =20 /* precondition: bus.lock has been acquired. */ @@ -891,7 +920,7 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *b= us) clk_reg_val &=3D (ASPEED_I2CD_TIME_TBUF_MASK | ASPEED_I2CD_TIME_THDSTA_MASK | ASPEED_I2CD_TIME_TACST_MASK); - clk_reg_val |=3D bus->get_clk_reg_val(bus->dev, divisor); + clk_reg_val |=3D bus->get_clk_reg_val(bus->dev, divisor, bus->duty_cycle); writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); =20 @@ -1009,11 +1038,16 @@ static int aspeed_i2c_probe_bus(struct platform_dev= ice *pdev) bus->bus_frequency =3D I2C_MAX_STANDARD_MODE_FREQ; } =20 + ret =3D of_property_read_u32(pdev->dev.of_node, + "i2c-clk-duty-cycle-min", &bus->duty_cycle); + if (ret < 0 || !bus->duty_cycle || bus->duty_cycle > 100) + bus->duty_cycle =3D DEFAULT_I2C_CLK_DUTY_CYCLE; + match =3D of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node); if (!match) bus->get_clk_reg_val =3D aspeed_i2c_24xx_get_clk_reg_val; else - bus->get_clk_reg_val =3D (u32 (*)(struct device *, u32)) + bus->get_clk_reg_val =3D (u32 (*)(struct device *, u32, u32)) match->data; =20 /* Initialize the I2C adapter */ --=20 2.17.1 From nobody Tue Apr 28 02:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 976B7C433EF for ; Tue, 7 Jun 2022 16:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345087AbiFGQjw (ORCPT ); Tue, 7 Jun 2022 12:39:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345110AbiFGQjk (ORCPT ); Tue, 7 Jun 2022 12:39:40 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4ABAC8BF1; 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[125.228.123.29]) by smtp.gmail.com with ESMTPSA id d15-20020aa797af000000b0051bbc198f3fsm12560272pfq.13.2022.06.07.09.39.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 09:39:39 -0700 (PDT) From: Potin Lai To: Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Andrew Jeffery , Rob Herring , Rayn Chen Cc: Patrick Williams , Potin Lai , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Potin Lai Subject: [PATCH v3 2/2] dt-bindings: aspeed-i2c: add properties for setting i2c clock duty cycle Date: Wed, 8 Jun 2022 00:37:03 +0800 Message-Id: <20220607163703.26355-3-potin.lai.pt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220607163703.26355-1-potin.lai.pt@gmail.com> References: <20220607163703.26355-1-potin.lai.pt@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce a new property for setting a minimum duty cycle for clock high. * i2c-clk-duty-cycle-min: a minimum percentage of clock high Signed-off-by: Potin Lai --- Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Docume= ntation/devicetree/bindings/i2c/aspeed,i2c.yaml index ea643e6c3ef5..af4c49111cc0 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -49,6 +49,14 @@ properties: description: states that there is another master active on this bus =20 + i2c-clk-duty-cycle-min: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 100 + default: 50 + description: + a minimum percentage of clock high + required: - reg - compatible --=20 2.17.1