From nobody Tue Apr 28 03:56:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 718A7C433EF for ; Mon, 6 Jun 2022 16:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241720AbiFFQa5 (ORCPT ); Mon, 6 Jun 2022 12:30:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241716AbiFFQau (ORCPT ); Mon, 6 Jun 2022 12:30:50 -0400 X-Greylist: delayed 62 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 06 Jun 2022 09:30:48 PDT Received: from ewsoutbound.kpnmail.nl (ewsoutbound.kpnmail.nl [195.121.94.183]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58E0B331C1C for ; Mon, 6 Jun 2022 09:30:47 -0700 (PDT) X-KPN-MessageId: 54269503-e5b5-11ec-8ee3-005056992ed3 Received: from smtp.kpnmail.nl (unknown [10.31.155.7]) by ewsoutbound.so.kpn.org (Halon) with ESMTPS id 54269503-e5b5-11ec-8ee3-005056992ed3; Mon, 06 Jun 2022 18:25:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kpnmail.nl; s=kpnmail01; h=mime-version:message-id:date:subject:to:from; bh=t63OwfhftQBAyL+fD30q+bT1pNxqFcyfuKg2Jivjc+Q=; b=NnR5/jMNJy7fKwGLzBDJb+7vKGxpMv6unVQu+wRU6nzH03mDnN54TZX2zuFBwYfIgIZy9JVAnU86A cNYoWSn+98xKLKM1s8yf0m/qTohHXKno0oZDU6xpzQ61gPoH84pLhrQkZlwYZpNV8H1UYiYN3FoLw/ FZe6Qpa3GMUp/iGw= X-KPN-MID: 33|aL9PUIB7qkWLTPrS0P64JdvWC3henaHPZmFqEnNfYTMTLrlXAfey2k1eZRTcV/G JqPqfuq/HDP8UfyOKzoEunHjtNzJusZNnGI/gT7ZsFaE= X-KPN-VerifiedSender: No X-CMASSUN: 33|A8jqBSxURq+ObuYB9ir+OR6sDf0y1Pyq+KNCzoUeVKU7xfk/lnYhgxDZOP/oTZ8 NuID5OAQyQIEWmMoElTqImQ== X-Originating-IP: 80.61.163.207 Received: from copland.sibelius.xs4all.nl (80-61-163-207.fixed.kpn.net [80.61.163.207]) by smtp.xs4all.nl (Halon) with ESMTPSA id ddb736f1-e5b5-11ec-961a-005056998788; Mon, 06 Jun 2022 18:29:41 +0200 (CEST) From: Mark Kettenis To: kernel@esmil.dk, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Mark Kettenis , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: dts: startfive: currect number of external interrupts Date: Mon, 6 Jun 2022 18:29:23 +0200 Message-Id: <20220606162924.71418-1-kettenis@openbsd.org> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex such as the L2 cache controller. But all 133 interrupts are external interrupts as far as the PLIC is concerned. Fixing the property that specifies the number of external interrupts allows the driver to manage these additional interrupts, whch is important since the interrupts for the L2 cache controller are enabled by default. Signed-off-by: Mark Kettenis --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index 69f22f9aad9d..f48e232a72a7 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -118,7 +118,7 @@ plic: interrupt-controller@c000000 { interrupt-controller; #address-cells =3D <0>; #interrupt-cells =3D <1>; - riscv,ndev =3D <127>; + riscv,ndev =3D <133>; }; =20 clkgen: clock-controller@11800000 { --=20 2.36.0