From nobody Sun Sep 22 01:48:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53F12C43334 for ; Mon, 6 Jun 2022 05:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229745AbiFFF26 (ORCPT ); Mon, 6 Jun 2022 01:28:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229960AbiFFF2U (ORCPT ); Mon, 6 Jun 2022 01:28:20 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82F8413FD57; Sun, 5 Jun 2022 22:11:39 -0700 (PDT) X-UUID: ed707747f42e4aa2afee77f25b9df1e3-20220606 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:2160d87d-65ce-4808-a524-8fc2a9d40391,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:20 X-CID-META: VersionHash:2a19b09,CLOUDID:edca447e-c8dc-403a-96e8-6237210dceee,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: ed707747f42e4aa2afee77f25b9df1e3-20220606 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 947476993; Mon, 06 Jun 2022 13:11:33 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 6 Jun 2022 13:11:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 6 Jun 2022 13:11:32 +0800 From: Bo-Chen Chen To: , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [RESEND v4 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Date: Mon, 6 Jun 2022 13:11:29 +0800 Message-ID: <20220606051131.14182-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220606051131.14182-1-rex-bc.chen@mediatek.com> References: <20220606051131.14182-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Nancy.Lin" Add vdosys1 RDMA definition. Signed-off-by: Nancy.Lin Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Tested-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,mdp-rdma.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,mdp-rdma.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,md= p-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,m= dp-rdma.yaml new file mode 100644 index 000000000000..678abb321cc2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.= yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MDP RDMA + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + The MediaTek MDP RDMA stands for Read Direct Memory Access. + It provides real time data to the back-end panel driver, such as DSI, + DPI and DP_INTF. + It contains one line buffer to store the sufficient pixel data. + RDMA device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for d= etails. + +properties: + compatible: + - const: mediatek,mt8195-vdo1-rdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA Clock + + iommus: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4= arguments, + such as gce node, subsys id, offset and register size. The subsys id= that is + mapping to the register of display function blocks is defined in the= gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - iommus + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + rdma@1c104000 { + compatible =3D "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c104000 0 0x1000>; + interrupts =3D ; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x4000 0x10= 00>; + }; + }; --=20 2.18.0