From nobody Sun Sep 22 02:08:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C5B6C433EF for ; Tue, 31 May 2022 13:53:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345089AbiEaNxG (ORCPT ); Tue, 31 May 2022 09:53:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345179AbiEaNwG (ORCPT ); Tue, 31 May 2022 09:52:06 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89FE89BACD for ; Tue, 31 May 2022 06:51:25 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id e2so18823647wrc.1 for ; Tue, 31 May 2022 06:51:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lS6mPjcp3pJcGZKSKOrBRDQ5D/bjAdtV0DGXyq7R5yA=; b=jWZkTEvodPuiB96Qs6mXattako2shiUcmHOK5JCPnAa/+dANk3kCQEaU2j85maInOS 7wccapwJAXJMVZSv5+22WnUBpFJo9r7NT/6S0QVmHHcnH5qh8r4urIOxZVxgFcsi0Gb/ QG42jxpY2LIJZvOqzPN9R1RWaMUTe81vHnQNMi9Q5WKx/Zbaomv4SJJAsmekVgErWqtf 89s8Cpd8ZdPXDgHVg7CM8bMLUKHuOm0mcoOg34P2RLVV1QQdIHx7UkLLvk1SGeQfCGoF 9VmuXQD2zv3Xea/wA2mZUbXLA11NotIMmfx/FonKioSuGfAmLTCIcYFQW6OmwGnj17+K f18g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lS6mPjcp3pJcGZKSKOrBRDQ5D/bjAdtV0DGXyq7R5yA=; b=7S4IG0M9BqVAF+sQpDdPeA4D9PH2YobAgraP2TJEuKniTNyitmE0dbUOyLPo7wFNK5 GnumOIrbG6ftfBk86oDWTPdbFfk4mCIHPNGJGDdZ/kZ8H+EGyjIICviwUAIHa/VAT1H8 9+FezNYxozBMUiXqz6SpHZMC4gjmITJaO3/fh9rYoSVpQwakHzu3aaOKs4qy7cqmjKgX LU5GZZZmfXA7dc4bCKMZL25Gj4rzYNEwTpcMct/zHgLyBZC+set7riQ7rtV7vhen8Dfi 5Ls5hAO4MVM5JJGEp+j3kHfHGanv+Jv2A7OmFbN3TdqGOq1mg6NMVJ1ikXACxDbQ7S1H fVXA== X-Gm-Message-State: AOAM530DkG+rcbwRBjOnOb5y/iS5zTtAH+Co7tNrO9xXzHLGrEOsbaHp tvoSRQDE0kZQ8RvCT/PRhPxBng== X-Google-Smtp-Source: ABdhPJyxUqp7A5lKp0lBRLaWN+7I+dgn6zxQIsw6ockQUNU2QQ+BWz60+i5V4pEHknJmf3zXNnmz2Q== X-Received: by 2002:adf:f905:0:b0:20f:ca3e:387f with SMTP id b5-20020adff905000000b0020fca3e387fmr42257311wrr.362.1654005069500; Tue, 31 May 2022 06:51:09 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b00394351e35edsm2404806wms.26.2022.05.31.06.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 06:51:08 -0700 (PDT) From: Fabien Parent To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, qii.wang@mediatek.com, matthias.bgg@gmail.com, jic23@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, chunfeng.yun@mediatek.com, broonie@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-iio@vger.kernel.org, linux-mmc@vger.kernel.org, linux-phy@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Fabien Parent Subject: [PATCH 16/17] arm64: dts: mediatek: add mt8365 device-tree Date: Tue, 31 May 2022 15:50:25 +0200 Message-Id: <20220531135026.238475-17-fparent@baylibre.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531135026.238475-1-fparent@baylibre.com> References: <20220531135026.238475-1-fparent@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device-tree for the MT8365 SoC. More information can be found about that SoC at the following address: https://www.mediatek.com/products/aiot/i350-mt8365 Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 1047 ++++++++++++++++++++++ 1 file changed, 1047 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi new file mode 100644 index 000000000000..e22b1d259418 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,1047 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8365"; + interrupt-parent =3D <&sysirq>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + ovl0 =3D &ovl0; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + color0 =3D &color0; + ccorr0 =3D &ccorr0; + aal0 =3D &aal0; + gamma0 =3D &gamma0; + dither0 =3D &dither0; + dsi0 =3D &dsi0; + dpi0 =3D &dpi0; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + clock-frequency =3D <1600000000>; + clocks =3D <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + clock-frequency =3D <1600000000>; + clocks =3D <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate", "armpll"; + operating-points-v2 =3D <&cluster0_opp>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + clock-frequency =3D <1600000000>; + clocks =3D <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate", "armpll"; + operating-points-v2 =3D <&cluster0_opp>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + clock-frequency =3D <1600000000>; + clocks =3D <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate", "armpll"; + operating-points-v2 =3D <&cluster0_opp>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + }; + }; + + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-microvolt =3D <650000>; + }; + opp-918000000 { + opp-hz =3D /bits/ 64 <918000000>; + opp-microvolt =3D <668750>; + }; + opp-987000000 { + opp-hz =3D /bits/ 64 <987000000>; + opp-microvolt =3D <687500>; + }; + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + opp-microvolt =3D <706250>; + }; + opp-1125000000 { + opp-hz =3D /bits/ 64 <1125000000>; + opp-microvolt =3D <725000>; + }; + opp-1216000000 { + opp-hz =3D /bits/ 64 <1216000000>; + opp-microvolt =3D <750000>; + }; + opp-1308000000 { + opp-hz =3D /bits/ 64 <1308000000>; + opp-microvolt =3D <775000>; + }; + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <800000>; + }; + opp-1466000000 { + opp-hz =3D /bits/ 64 <1466000000>; + opp-microvolt =3D <825000>; + }; + opp-1533000000 { + opp-hz =3D /bits/ 64 <1533000000>; + opp-microvolt =3D <850000>; + }; + opp-1633000000 { + opp-hz =3D /bits/ 64 <1633000000>; + opp-microvolt =3D <887500>; + }; + opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <912500>; + }; + opp-1767000000 { + opp-hz =3D /bits/ 64 <1767000000>; + opp-microvolt =3D <937500>; + }; + opp-1834000000 { + opp-hz =3D /bits/ 64 <1834000000>; + opp-microvolt =3D <962500>; + }; + opp-1917000000 { + opp-hz =3D /bits/ 64 <1917000000>; + opp-microvolt =3D <993750>; + }; + opp-2001000000 { + opp-hz =3D /bits/ 64 <2001000000>; + opp-microvolt =3D <1025000>; + }; + }; + + clk26m: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg =3D <0 0x43000000 0 0x20000>; + }; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x80000>, + <0 0x0c080000 0 0x80000>; + + interrupts =3D ; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8365-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg: syscon@10001000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8365-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible =3D "syscon"; + reg =3D <0 0x10005000 0 0x1000>; + }; + + scpsys: syscon@10006000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0 0x10006000 0 0x1000>; + #power-domain-cells =3D <1>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8365-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names =3D "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + mediatek,infracfg_nao =3D <&infracfg_nao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg =3D ; + clocks =3D <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names =3D "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + mediatek,smi =3D <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg =3D ; + #power-domain-cells =3D <0>; + mediatek,smi =3D <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg =3D ; + #power-domain-cells =3D <0>; + mediatek,smi =3D <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg =3D ; + clocks =3D <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names =3D "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + mediatek,smi =3D <&smi_common>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names =3D "conn", "conn1"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MFG_SEL>; + clock-names =3D "mfg"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names =3D "audio", "audio1", "audio2"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names =3D "dsp", "dsp1"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible =3D "mediatek,mt8365-wdt", + "mediatek,mt6589-wdt"; + reg =3D <0 0x10007000 0 0x100>; + #reset-cells =3D <1>; + }; + + gpt: apxgpt@10008000 { + compatible =3D "mediatek,mt8365-timer", + "mediatek,mt6577-timer"; + reg =3D <0 0x10008000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SYS_26M_D2>; + clock-names =3D "clk13m"; + }; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8365-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pwrap: pwrap@1000d000 { + compatible =3D "mediatek,mt8365-pwrap"; + reg =3D <0 0x1000d000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_PWRAP_SPI>, + <&infracfg CLK_IFR_PMIC_AP>, + <&infracfg CLK_IFR_PWRAP_SYS>, + <&infracfg CLK_IFR_PWRAP_TMR>; + clock-names =3D "spi", "wrap", "sys", "tmr"; + }; + + keypad: kp@10010000 { + compatible =3D "mediatek,mt6779-keypad"; + reg =3D <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts =3D ; + clocks =3D <&clk26m>; + clock-names =3D "kpd"; + status =3D "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible =3D "mediatek,mt8365-mcucfg", "syscon"; + reg =3D <0 0x10200000 0 0x2000>; + #clock-cells =3D <1>; + }; + + sysirq: intpol-controller@10200a80 { + compatible =3D "mediatek,mt8365-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&gic>; + reg =3D <0 0x10200a80 0 0x20>; + }; + + iommu: iommu@10205000 { + compatible =3D "mediatek,mt8365-m4u"; + reg =3D <0 0x10205000 0 0x1000>; + interrupts =3D ; + mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells =3D <1>; + }; + + infracfg_nao: infracfg-nao@1020e000 { + compatible =3D "syscon"; + reg =3D <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible =3D "mediatek,mt8365-rng", + "mediatek,mt7623-rng"; + reg =3D <0 0x1020f000 0 0x100>; + clocks =3D <&infracfg CLK_IFR_TRNG>; + clock-names =3D "rng"; + }; + + apdma: dma-controller@11000280 { + compatible =3D "mediatek,mt8365-uart-dma", + "mediatek,mt6577-uart-dma"; + reg =3D <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts =3D , + , + , + , + , + ; + dma-requests =3D <6>; + clocks =3D <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "apdma"; + #dma-cells =3D <1>; + }; + + auxadc: adc@11001000 { + compatible =3D "mediatek,mt8365-auxadc", + "mediatek,mt8173-auxadc"; + reg =3D <0 0x11001000 0 0x1000>; + clocks =3D <&infracfg CLK_IFR_AUXADC>; + clock-names =3D "main"; + #io-channel-cells =3D <1>; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 0 + &apdma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 2 + &apdma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart2: serial@11004000 { + compatible =3D "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 4 + &apdma 5>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + pwm: pwm@11006000 { + compatible =3D "mediatek,mt8365-pwm"; + reg =3D <0 0x11006000 0 0x1000>; + #pwm-cells =3D <2>; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + i2c0: i2c@11007000 { + compatible =3D "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg =3D <0 0x11007000 0 0xa0>, + <0 0x11000080 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C0_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@11008000 { + compatible =3D "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg =3D <0 0x11008000 0 0xa0>, + <0 0x11000100 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C1_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@11009000 { + compatible =3D "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg =3D <0 0x11009000 0 0xa0>, + <0 0x11000180 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C2_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi: spi@1100a000 { + compatible =3D "mediatek,mt8365-spi", + "mediatek,mt7622-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x1100a000 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + thermal: thermal@1100b000 { + compatible =3D "mediatek,mt8365-thermal"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_THERM>, + <&infracfg CLK_IFR_AUXADC>; + clock-names =3D "therm", "auxadc"; + mediatek,auxadc =3D <&auxadc>; + mediatek,apmixedsys =3D <&apmixedsys>; + nvmem-cells =3D <&thermal_calibration>; + nvmem-cell-names =3D "calibration-data"; + #thermal-sensor-cells =3D <1>; + }; + + disp_pwm: disp-pwm@1100e000 { + compatible =3D "mediatek,mt8365-disp-pwm", + "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + #pwm-cells =3D <2>; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_IFR_DISP_PWM>; + clock-names =3D "main", "mm"; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + status =3D "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible =3D "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg =3D <0 0x1100f000 0 0xa0>, + <0 0x11000200 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&infracfg CLK_IFR_I2C3_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + ssusb: usb@11201000 { + compatible =3D "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host: usb@11200000 { + compatible =3D "mediatek,mt8365-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status =3D "disabled"; + }; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_IFR_MSDC0_HCLK>, + <&infracfg CLK_IFR_MSDC0_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg CLK_IFR_MSDC1_HCLK>, + <&infracfg CLK_IFR_MSDC1_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + status =3D "disabled"; + }; + + ethernet: ethernet@112a0000 { + compatible =3D "mediatek,mt8365-eth"; + reg =3D <0 0x112a0000 0 0x1000>; + mediatek,pericfg =3D <&infracfg>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names =3D "core", "reg", "trans"; + status =3D "disabled"; + }; + + mipi_tx0: dsi-phy@11c00000 { + compatible =3D "mediatek,mt8365-mipi-tx", + "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11c00000 0 0x800>; + clocks =3D <&clk26m>; + clock-names =3D "ref_clk"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + }; + + efuse: efuse@11c50000 { + compatible =3D "mediatek,mt8365-efuse", "mediatek,efuse"; + reg =3D <0 0x11c50000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + thermal_calibration: calib@180 { + reg =3D <0x180 0xc>; + }; + }; + + u3phy: t-phy@11cc0000 { + compatible =3D "mediatek,mt8365-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #phy-cells =3D <1>; + #size-cells =3D <2>; + ranges; + status =3D "okay"; + + u2port0: usb-phy@11cc0000 { + reg =3D <0 0x11cc0000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + status =3D "okay"; + }; + + u2port1: usb-phy@11cc1000 { + reg =3D <0 0x11cc1000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + status =3D "okay"; + }; + }; + + mfgcfg: syscon@13000000 { + compatible =3D "mediatek,mt8365-mfgcfg", "syscon"; + reg =3D <0 0x13000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + mmsys: syscon@14000000 { + compatible =3D "mediatek,mt8365-mmsys", "syscon"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8365-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + }; + + smi_common: smi@14002000 { + compatible =3D "mediatek,mt8365-smi-common", + "mediatek,mt8186-smi-common"; + reg =3D <0 0x14002000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>; + clock-names =3D "apb", "smi", "gals0", "gals1"; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + }; + + larb0: larb@14003000 { + compatible =3D "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mmsys CLK_MM_MM_SMI_LARB0>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + mediatek,larb-id =3D <0>; + }; + + ovl0: ovl@1400b000 { + compatible =3D "mediatek,mt8365-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x1400b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_OVL0>; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + }; + + rdma0: rdma@1400d000 { + compatible =3D "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1400d000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA0>; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size =3D <5120>; + }; + + color0: color@1400f000 { + compatible =3D "mediatek,mt8365-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x1400f000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@14010000 { + compatible =3D "mediatek,mt8365-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg =3D <0 0x14010000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_CCORR0>; + }; + + aal0: aal@14011000 { + compatible =3D "mediatek,mt8365-disp-aal", + "mediatek,mt8183-disp-aal"; + reg =3D <0 0x14011000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_AAL0>; + }; + + gamma0: gamma@14012000 { + compatible =3D "mediatek,mt8365-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x14012000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_GAMMA0>; + }; + + dither0: dither@14013000 { + compatible =3D "mediatek,mt8365-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x14013000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_DITHER0>; + }; + + dsi0: dsi@14014000 { + compatible =3D "mediatek,mt8365-dsi", + "mediatek,mt8183-dsi"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + }; + + rdma1: rdma@14016000 { + compatible =3D "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14016000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA1>; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size =3D <2048>; + }; + + dpi0: dpi@14018000 { + compatible =3D "mediatek,mt8365-dpi", + "mediatek,mt8192-dpi"; + reg =3D <0 0x14018000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + clocks =3D <&topckgen CLK_TOP_DPI0_SEL>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>, + <&mmsys CLK_MM_DPI0_DPI0>; + clock-names =3D "pixel", "engine", "pll", "dpi"; + status =3D "disabled"; + }; + + camsys: syscon@15000000 { + compatible =3D "mediatek,mt8365-imgsys", "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + larb2: larb@15001000 { + compatible =3D "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg =3D <0 0x15001000 0 0x1000>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mmsys CLK_MM_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB2>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + mediatek,larb-id =3D <2>; + }; + + vdecsys: syscon@16000000 { + compatible =3D "mediatek,mt8365-vdecsys", "syscon"; + reg =3D <0 0x16000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + larb3: larb@16010000 { + compatible =3D "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg =3D <0 0x16010000 0 0x1000>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8365_POWER_DOMAIN_VDEC>; + mediatek,larb-id =3D <3>; + }; + + vencsys: syscon@17000000 { + compatible =3D "mediatek,mt8365-vencsys", "syscon"; + reg =3D <0 0x17000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + larb1: larb@17010000 { + compatible =3D "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg =3D <0 0x17010000 0 0x1000>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8365_POWER_DOMAIN_VENC>; + mediatek,larb-id =3D <1>; + }; + + apu: syscon@19020000 { + compatible =3D "mediatek,mt8365-apu", "syscon"; + reg =3D <0 0x19020000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <1000>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&thermal 0>; + + trips { + threshold: trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + target: trip-point1 { + temperature =3D <105000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_crit: cpu_crit0 { + temperature =3D <117000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D + <&cpu0 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu2 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution =3D <100>; + }; + }; + }; + + tzts1: tzts1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&thermal 1>; + trips {}; + cooling-maps {}; + }; + + tzts2: tzts2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&thermal 2>; + trips {}; + cooling-maps {}; + }; + + tzts3: tzts3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&thermal 3>; + trips {}; + cooling-maps {}; + }; + + tzts4: tzts4-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&thermal 4>; + trips {}; + cooling-maps {}; + }; + }; + + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.36.1