From nobody Tue Apr 28 18:21:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAAB7C433EF for ; Tue, 31 May 2022 04:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243916AbiEaEuy (ORCPT ); Tue, 31 May 2022 00:50:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229468AbiEaEut (ORCPT ); Tue, 31 May 2022 00:50:49 -0400 Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D6DA941B3; Mon, 30 May 2022 21:50:48 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.west.internal (Postfix) with ESMTP id BB4333200935; Tue, 31 May 2022 00:50:45 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Tue, 31 May 2022 00:50:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1653972645; x=1654059045; bh=FW jZmI4EaR1XZe8Uu9VR6zEl9VrAmbrBoz7dMVCbOZc=; b=Yf3f6anEAJsfy/RfKH PrSfWvx9acPMXnwF2eQ5g72tm0NHUl2EzsiP/Xc6VMnx8ALZQMxcIt6GywWStDVh kuYq4g+Ipv/K6HTWylHK7DIUntjP6Y7OIrIlXt+lRG0Qee8gEZdEkSu8UaDmOeaQ 9LcAdDXeRSms+Jtt6UUvpkPO2HmqbjmTYLgJe4Mxp/UDGj8lQcFSwnexGf5JYPYh +R41X7bCrL5qr28kKudQItKl0jpi9Jncl2CjrMeuKgZHA6pCHZMp0z4tYt82JazN rsiR+FWI3XlVnzqhLiaWFBT0ehJhD+QFRSkawJm9QiheAfptfTdQxp8dnvhJlYib Q8nA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1653972645; x=1654059045; bh=FWjZmI4EaR1XZ e8Uu9VR6zEl9VrAmbrBoz7dMVCbOZc=; b=G72N9V5vr7ojnqjYAJ0VpxsMEFnTy 7j8Rio2+pmIKiotZWukVm6ZGUssAizpOjyhe2cyC7+GRruSZHqfQdE8VJeVBBGJr Y4jjuXomtA67UNgNbOZXwkvxrJpzsnBGPorVsqm4AL8LpZKvFqNhLYym9n0DHTon fST6M63NaBlL9CyqWyt00yZu2h8j8NHvKbgJlaUcZvYGpaEjFUZISijp7WrMZ6bn N2hhJ8kgdz47wiMlCTeGiAy4Ce1BhWmB7GI1PprXFQLSNoYFy6IbOk3my57rYlFh ylVlGrhEyxZ2/dEhvfiydwgxG7LP7AsQQYZRArkDUYVFKxTQ/MSojCLCw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrkeejgdeklecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpedukeetueduhedtleetvefguddvvdejhfefudelgfduveeggeehgfdu feeitdevteenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 31 May 2022 00:50:44 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Russell King , Samuel Holland , Bartosz Dudziak , Bjorn Andersson , Krzysztof Kozlowski , Lorenzo Pieralisi , Luca Weiss , Maxime Ripard , Rob Herring , Robin Murphy , Stephan Gerhold , Thierry Reding , Vinod Koul , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 1/3] ARM: sunxi: Remove A31 and A23/A33 platform SMP code Date: Mon, 30 May 2022 23:50:36 -0500 Message-Id: <20220531045038.42230-2-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220531045038.42230-1-samuel@sholland.org> References: <20220531045038.42230-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" U-Boot has provided PSCI on Allwinner A31 and A23/A33 since May 2015, commit 014414f53695 ("ARM: sunxi: Enable PSCI for sun8i"). Since we can assume PSCI is available on these platforms, the custom SMP bringup code is no longer used, and it can be removed. The platform SMP code has a hidden dependency on the legacy PRCM bindings, so it would be broken anyway when those are retired. Signed-off-by: Samuel Holland --- arch/arm/mach-sunxi/Makefile | 1 - arch/arm/mach-sunxi/platsmp.c | 194 ---------------------------------- 2 files changed, 195 deletions(-) delete mode 100644 arch/arm/mach-sunxi/platsmp.c diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 146e623c54d3..e5dc8530e98c 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -3,4 +3,3 @@ CFLAGS_mc_smp.o +=3D -march=3Darmv7-a =20 obj-$(CONFIG_ARCH_SUNXI) +=3D sunxi.o obj-$(CONFIG_ARCH_SUNXI_MC_SMP) +=3D mc_smp.o headsmp.o -obj-$(CONFIG_SMP) +=3D platsmp.o diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c deleted file mode 100644 index 052097e78e6e..000000000000 --- a/arch/arm/mach-sunxi/platsmp.c +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SMP support for Allwinner SoCs - * - * Copyright (C) 2013 Maxime Ripard - * - * Maxime Ripard - * - * Based on code - * Copyright (C) 2012-2013 Allwinner Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64) -#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40) -#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04) -#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08) -#define CPUCFG_GEN_CTRL_REG 0x184 -#define CPUCFG_PRIVATE0_REG 0x1a4 -#define CPUCFG_PRIVATE1_REG 0x1a8 -#define CPUCFG_DBG_CTL0_REG 0x1e0 -#define CPUCFG_DBG_CTL1_REG 0x1e4 - -#define PRCM_CPU_PWROFF_REG 0x100 -#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140) - -static void __iomem *cpucfg_membase; -static void __iomem *prcm_membase; - -static DEFINE_SPINLOCK(cpu_lock); - -static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus) -{ - struct device_node *node; - - node =3D of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm"); - if (!node) { - pr_err("Missing A31 PRCM node in the device tree\n"); - return; - } - - prcm_membase =3D of_iomap(node, 0); - of_node_put(node); - if (!prcm_membase) { - pr_err("Couldn't map A31 PRCM registers\n"); - return; - } - - node =3D of_find_compatible_node(NULL, NULL, - "allwinner,sun6i-a31-cpuconfig"); - if (!node) { - pr_err("Missing A31 CPU config node in the device tree\n"); - return; - } - - cpucfg_membase =3D of_iomap(node, 0); - of_node_put(node); - if (!cpucfg_membase) - pr_err("Couldn't map A31 CPU config registers\n"); - -} - -static int sun6i_smp_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - u32 reg; - int i; - - if (!(prcm_membase && cpucfg_membase)) - return -EFAULT; - - spin_lock(&cpu_lock); - - /* Set CPU boot address */ - writel(__pa_symbol(secondary_startup), - cpucfg_membase + CPUCFG_PRIVATE0_REG); - - /* Assert the CPU core in reset */ - writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); - - /* Assert the L1 cache in reset */ - reg =3D readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); - writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); - - /* Disable external debug access */ - reg =3D readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); - writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); - - /* Power up the CPU */ - for (i =3D 0; i <=3D 8; i++) - writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); - mdelay(10); - - /* Clear CPU power-off gating */ - reg =3D readl(prcm_membase + PRCM_CPU_PWROFF_REG); - writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); - mdelay(1); - - /* Deassert the CPU core reset */ - writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); - - /* Enable back the external debug accesses */ - reg =3D readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); - writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); - - spin_unlock(&cpu_lock); - - return 0; -} - -static const struct smp_operations sun6i_smp_ops __initconst =3D { - .smp_prepare_cpus =3D sun6i_smp_prepare_cpus, - .smp_boot_secondary =3D sun6i_smp_boot_secondary, -}; -CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops= ); - -static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus) -{ - struct device_node *node; - - node =3D of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm"); - if (!node) { - pr_err("Missing A23 PRCM node in the device tree\n"); - return; - } - - prcm_membase =3D of_iomap(node, 0); - of_node_put(node); - if (!prcm_membase) { - pr_err("Couldn't map A23 PRCM registers\n"); - return; - } - - node =3D of_find_compatible_node(NULL, NULL, - "allwinner,sun8i-a23-cpuconfig"); - if (!node) { - pr_err("Missing A23 CPU config node in the device tree\n"); - return; - } - - cpucfg_membase =3D of_iomap(node, 0); - of_node_put(node); - if (!cpucfg_membase) - pr_err("Couldn't map A23 CPU config registers\n"); - -} - -static int sun8i_smp_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - u32 reg; - - if (!(prcm_membase && cpucfg_membase)) - return -EFAULT; - - spin_lock(&cpu_lock); - - /* Set CPU boot address */ - writel(__pa_symbol(secondary_startup), - cpucfg_membase + CPUCFG_PRIVATE0_REG); - - /* Assert the CPU core in reset */ - writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); - - /* Assert the L1 cache in reset */ - reg =3D readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); - writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); - - /* Clear CPU power-off gating */ - reg =3D readl(prcm_membase + PRCM_CPU_PWROFF_REG); - writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); - mdelay(1); - - /* Deassert the CPU core reset */ - writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); - - spin_unlock(&cpu_lock); - - return 0; -} - -static const struct smp_operations sun8i_smp_ops __initconst =3D { - .smp_prepare_cpus =3D sun8i_smp_prepare_cpus, - .smp_boot_secondary =3D sun8i_smp_boot_secondary, -}; -CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops= ); 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Tue, 31 May 2022 00:50:47 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Russell King , Samuel Holland , Bartosz Dudziak , Bjorn Andersson , Krzysztof Kozlowski , Lorenzo Pieralisi , Luca Weiss , Maxime Ripard , Rob Herring , Robin Murphy , Stephan Gerhold , Thierry Reding , Vinod Koul , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 2/3] ARM: dts: sunxi: Remove obsolete CPU enable methods Date: Mon, 30 May 2022 23:50:37 -0500 Message-Id: <20220531045038.42230-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220531045038.42230-1-samuel@sholland.org> References: <20220531045038.42230-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that the platform SMP code has been removed in favor of PSCI, these enable methods are meaningless. Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sun6i-a31.dtsi | 1 - arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31= .dtsi index 715d74854449..9dee04904e31 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -95,7 +95,6 @@ timer { }; =20 cpus { - enable-method =3D "allwinner,sun6i-a31"; #address-cells =3D <1>; #size-cells =3D <0>; =20 diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i= -a23-a33.dtsi index 4461d5098b20..87e2d63ceb0e 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -85,7 +85,6 @@ timer { }; =20 cpus { - enable-method =3D "allwinner,sun8i-a23"; #address-cells =3D <1>; #size-cells =3D <0>; =20 --=20 2.35.1 From nobody Tue Apr 28 18:21:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DA3AC433EF for ; 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Tue, 31 May 2022 00:50:51 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec Cc: Russell King , Samuel Holland , Bartosz Dudziak , Bjorn Andersson , Krzysztof Kozlowski , Lorenzo Pieralisi , Luca Weiss , Maxime Ripard , Rob Herring , Robin Murphy , Stephan Gerhold , Thierry Reding , Vinod Koul , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/3] dt-bindings: arm: Remove obsolete CPU enable methods Date: Mon, 30 May 2022 23:50:38 -0500 Message-Id: <20220531045038.42230-4-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220531045038.42230-1-samuel@sholland.org> References: <20220531045038.42230-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" U-Boot has provided PSCI on Allwinner A31 and A23/A33 since May 2015, commit 014414f53695 ("ARM: sunxi: Enable PSCI for sun8i"). Since we can assume PSCI is available on these platforms, they no longer need custom CPU enable methods. Signed-off-by: Samuel Holland Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index ed04650291a8..94527187a85a 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -195,8 +195,6 @@ properties: # On ARM 32-bit systems this property is optional - enum: - actions,s500-smp - - allwinner,sun6i-a31 - - allwinner,sun8i-a23 - allwinner,sun9i-a80-smp - allwinner,sun8i-a83t-smp - amlogic,meson8-smp --=20 2.35.1