From nobody Tue Apr 28 18:16:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6370C433EF for ; Mon, 30 May 2022 12:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236244AbiE3M5R (ORCPT ); Mon, 30 May 2022 08:57:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236224AbiE3M5O (ORCPT ); Mon, 30 May 2022 08:57:14 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01A0EDE97; Mon, 30 May 2022 05:57:12 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24UB4KFc012162; Mon, 30 May 2022 05:57:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=oYO13XbBYLyDLrEfDsgv1ohh53H8w+Fz/FYNKcSq9yI=; b=GjjA1ziOnzt4ur10Gfq2c15BMHazksFMSOLtWRFAU8Uqloc+LQNWaKQCE9z2ESbYQTeF skVtDEXsYfetN0FTT1TwzS8FWPBCph+ttf3YQV6Q+3KGVLtpcHTK2gTM1FiUZlk71r7x zh8H8RA6bnzLLv6q4/oHk4ks6HcKtnd+j8YDW+oSIUObECXE0RpD4RPT8BpxFF2F7qNs jEqixAONjgW64ssNcH+uTd5YBKuH8QsIk5OKQj3OKYVGMxLyFPllaQmEVEhQpJj82qf8 gtauRmH6Eh014coZqGher0UdSMandON5UP7D3omDUFjFim/t5I8wuYI9niIVCV07IP1s kg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gbk8n5fc5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 30 May 2022 05:57:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 30 May 2022 05:57:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 30 May 2022 05:57:01 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id B3C863F7048; Mon, 30 May 2022 05:57:00 -0700 (PDT) From: Piyush Malgujar To: , CC: , , , , Piyush Malgujar , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni Subject: [PATCH v2 1/3] net: mdio: mdio-thunder: stop toggling SMI clock on idle Date: Mon, 30 May 2022 05:53:26 -0700 Message-ID: <20220530125329.30717-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220530125329.30717-1-pmalgujar@marvell.com> References: <20220530125329.30717-1-pmalgujar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: gq0OF6O3plAHcXdXigZaoxn07hpx5dE7 X-Proofpoint-GUID: gq0OF6O3plAHcXdXigZaoxn07hpx5dE7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-30_04,2022-05-30_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SMI clock should be running only for the time when there are transactions on the bus. Signed-off-by: Damian Eppel Signed-off-by: Piyush Malgujar --- drivers/net/mdio/mdio-thunder.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/mdio/mdio-thunder.c b/drivers/net/mdio/mdio-thunde= r.c index 822d2cdd2f3599025f3e79d4243337c18114c951..715c835ace785da345ac037177b= 0f291678e4c47 100644 --- a/drivers/net/mdio/mdio-thunder.c +++ b/drivers/net/mdio/mdio-thunder.c @@ -58,6 +58,7 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, struct resource r; struct mii_bus *mii_bus; struct cavium_mdiobus *bus; + union cvmx_smix_clk smi_clk; union cvmx_smix_en smi_en; =20 /* If it is not an OF node we cannot handle it yet, so @@ -87,6 +88,10 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pde= v, bus->register_base =3D nexus->bar0 + r.start - pci_resource_start(pdev, 0); =20 + smi_clk.u64 =3D oct_mdio_readq(bus->register_base + SMI_CLK); + smi_clk.s.clk_idle =3D 1; + oct_mdio_writeq(smi_clk.u64, bus->register_base + SMI_CLK); + smi_en.u64 =3D 0; smi_en.s.en =3D 1; oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN); --=20 2.17.1 From nobody Tue Apr 28 18:16:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 727D3C4332F for ; Mon, 30 May 2022 12:57:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236224AbiE3M5j (ORCPT ); Mon, 30 May 2022 08:57:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236290AbiE3M5g (ORCPT ); Mon, 30 May 2022 08:57:36 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73085101CE; Mon, 30 May 2022 05:57:32 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24UCDg4J004646; Mon, 30 May 2022 05:57:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=KUOaiXdtrNFz+pU87J94GmVNlBDbYQuMw0tvy80h41Y=; b=grBir0/uqiS4o45ISjuhi+2NgHk5NVmZ7/RBUYL11sU1EIA4KoUAsayW9nxMZH1wulCH QHyufc4k9p/XGuEAFiVVwsKkoFpi2Vu0Kf9xHfKUlIRl6Mc0yvZwSUq7sztOQgfx8am5 LwdLvPobQp56TBx0HlvggQNSgTHVoD0goWIYHe/TNTez7rhB9q25fXvIaMemOx3hFlNU YX+QtCwVEdWGRmXX3Vc4lU44hvTHI5mkAzBpcIXId74OpefKUQAFySeyr8MsoBkqBIm2 qVzzr7z20pSep6IJqNDb+Xkhw5fRgNLbnUjJwkOj7HnKDmVZ86WqWwQCEx8xIInw2/7J wQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gbk8n5fd8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 30 May 2022 05:57:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 30 May 2022 05:57:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 30 May 2022 05:57:21 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id CFA7F3F7048; Mon, 30 May 2022 05:57:20 -0700 (PDT) From: Piyush Malgujar To: , CC: , , , , Piyush Malgujar , "David S. Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Rob Herring , Andrew Lunn , Heiner Kallweit , Russell King Subject: [PATCH v2 2/3] dt-bindings: net: cavium-mdio.txt: add clock-frequency attribute Date: Mon, 30 May 2022 05:53:27 -0700 Message-ID: <20220530125329.30717-3-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220530125329.30717-1-pmalgujar@marvell.com> References: <20220530125329.30717-1-pmalgujar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: OyHbLr-8lWooY_zkqHNwv509e02rDhId X-Proofpoint-GUID: OyHbLr-8lWooY_zkqHNwv509e02rDhId X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-30_04,2022-05-30_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to configure MDIO clock frequency via DTS Signed-off-by: Damian Eppel Signed-off-by: Piyush Malgujar --- Documentation/devicetree/bindings/net/cavium-mdio.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Docume= ntation/devicetree/bindings/net/cavium-mdio.txt index 020df08b8a30f4df80766bb90e100ae6210a777b..638c341966a80823b9eb2f33b94= 7f38110907cc1 100644 --- a/Documentation/devicetree/bindings/net/cavium-mdio.txt +++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt @@ -41,6 +41,9 @@ Properties: =20 - reg: The PCI device and function numbers of the nexus device. =20 +- clock-frequency: MDIO bus clock frequency in Hz. It defaults to 3.125 MH= z and + and not to standard 2.5 MHz for Marvell Octeon family. + - #address-cells: Must be <2>. =20 - #size-cells: Must be <2>. @@ -64,6 +67,7 @@ Example: #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0x87e0 0x05003800 0x0 0x30>; + clock-frequency =3D <3125000>; =20 ethernet-phy@0 { ... @@ -75,6 +79,7 @@ Example: #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0x87e0 0x05003880 0x0 0x30>; + clock-frequency =3D <3125000>; =20 ethernet-phy@0 { ... --=20 2.17.1 From nobody Tue Apr 28 18:16:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0F5FC433F5 for ; Mon, 30 May 2022 12:58:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236260AbiE3M56 (ORCPT ); Mon, 30 May 2022 08:57:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236254AbiE3M54 (ORCPT ); Mon, 30 May 2022 08:57:56 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFC00DF0D; Mon, 30 May 2022 05:57:55 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24UC20jm010899; Mon, 30 May 2022 05:57:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=DHPwQM3EoZAYOMrTULFucAAFNaQSwNNJwNpzOvB+juM=; b=dMQJnJzQ5NQk1AeaWZCDa70gne3/2tOHUrOttxElRN+GsivJxkWokiwfV8d0UrUxOtwV o0vWWvc2XkhKyk8wcN3H81LCRfxDJz2pmhuWxQ+1HKYostRE5NyTuuJl36evzHDB4Jyp PGyUZ+g+ldPE3Dc7KZrCbMZM6YI43ALXcMiNo61SENP1lADoaFxywhgAul+fty4sNb2Q srZhdzKAbQ8J6NMsQPa3lto6DjBXlzq5IGf2oRj5LM16REAVJj3JYLwvvWhALgeoiCu9 uttgaYDJQbp+gBCSrzVFMMJhqywZUSkTcBoCwW6iyYEREd6qhBjIO3OYMx2XsXkFd/qJ Wg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gbh3pdrrr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 30 May 2022 05:57:37 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 May 2022 05:57:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 30 May 2022 05:57:36 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id C82F23F7048; Mon, 30 May 2022 05:57:35 -0700 (PDT) From: Piyush Malgujar To: , CC: , , , , Piyush Malgujar , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni Subject: [PATCH v2 3/3] net: mdio: mdio-thunder: support for clock-freq attribute Date: Mon, 30 May 2022 05:53:28 -0700 Message-ID: <20220530125329.30717-4-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220530125329.30717-1-pmalgujar@marvell.com> References: <20220530125329.30717-1-pmalgujar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: RsXBWQOEP4gosMau-E17IVTLOcZiAxba X-Proofpoint-ORIG-GUID: RsXBWQOEP4gosMau-E17IVTLOcZiAxba X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-30_04,2022-05-30_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Added functionality to modify clock frequency via DTS entry. Signed-off-by: Damian Eppel Signed-off-by: Piyush Malgujar --- drivers/net/mdio/mdio-cavium.h | 1 + drivers/net/mdio/mdio-thunder.c | 63 +++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/net/mdio/mdio-cavium.h b/drivers/net/mdio/mdio-cavium.h index a2245d436f5dae4d6424b7c7bfca0aa969a3b3ad..ed4c48d8a38bd80e6a169f7a6d9= 0c1f2a0daccfc 100644 --- a/drivers/net/mdio/mdio-cavium.h +++ b/drivers/net/mdio/mdio-cavium.h @@ -92,6 +92,7 @@ struct cavium_mdiobus { struct mii_bus *mii_bus; void __iomem *register_base; enum cavium_mdiobus_mode mode; + u32 clk_freq; }; =20 #ifdef CONFIG_CAVIUM_OCTEON_SOC diff --git a/drivers/net/mdio/mdio-thunder.c b/drivers/net/mdio/mdio-thunde= r.c index 715c835ace785da345ac037177b0f291678e4c47..7ea6ef0a23f3f5d7df76e3a7aed= 007ed847f9140 100644 --- a/drivers/net/mdio/mdio-thunder.c +++ b/drivers/net/mdio/mdio-thunder.c @@ -14,11 +14,56 @@ =20 #include "mdio-cavium.h" =20 +#define PHASE_MIN 3 +#define PHASE_DFLT 16 + struct thunder_mdiobus_nexus { void __iomem *bar0; struct cavium_mdiobus *buses[4]; }; =20 +static inline u32 clk_freq(u32 phase) +{ + return (100000000U / (2 * (phase))); +} + +static inline u32 calc_sample(u32 phase) +{ + return (2 * (phase) - 3); +} + +static u32 _config_clk(u32 req_freq, u32 *phase, u32 *sample) +{ + unsigned int p; + u32 freq =3D 0, freq_prev; + + for (p =3D PHASE_MIN; p < PHASE_DFLT; p++) { + freq_prev =3D freq; + freq =3D clk_freq(p); + + if (req_freq >=3D freq) + break; + } + + if (p =3D=3D PHASE_DFLT) + freq =3D clk_freq(PHASE_DFLT); + + if (p =3D=3D PHASE_MIN || p =3D=3D PHASE_DFLT) + goto out; + + /* Check which clock value from the identified range + * is closer to the requested value + */ + if ((freq_prev - req_freq) < (req_freq - freq)) { + p =3D p - 1; + freq =3D freq_prev; + } +out: + *phase =3D p; + *sample =3D calc_sample(p); + return freq; +} + static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -56,6 +101,7 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pde= v, i =3D 0; device_for_each_child_node(&pdev->dev, fwn) { struct resource r; + u32 req_clk_freq; struct mii_bus *mii_bus; struct cavium_mdiobus *bus; union cvmx_smix_clk smi_clk; @@ -90,6 +136,23 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pd= ev, =20 smi_clk.u64 =3D oct_mdio_readq(bus->register_base + SMI_CLK); smi_clk.s.clk_idle =3D 1; + + if (!of_property_read_u32(node, "clock-frequency", &req_clk_freq)) { + u32 phase, sample; + + dev_dbg(&pdev->dev, "requested bus clock frequency=3D%d\n", + req_clk_freq); + + bus->clk_freq =3D _config_clk(req_clk_freq, + &phase, &sample); + + smi_clk.s.phase =3D phase; + smi_clk.s.sample_hi =3D (sample >> 4) & 0x1f; + smi_clk.s.sample =3D sample & 0xf; + } else { + bus->clk_freq =3D clk_freq(PHASE_DFLT); + } + oct_mdio_writeq(smi_clk.u64, bus->register_base + SMI_CLK); =20 smi_en.u64 =3D 0; --=20 2.17.1