From nobody Tue Apr 28 19:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3AD0C4332F for ; Mon, 30 May 2022 10:10:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235114AbiE3KKq (ORCPT ); Mon, 30 May 2022 06:10:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233749AbiE3KKm (ORCPT ); Mon, 30 May 2022 06:10:42 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC1AA7B9DE; Mon, 30 May 2022 03:10:41 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 24UAAc0u128823; Mon, 30 May 2022 05:10:38 -0500 DKIM-Signature: v=1; 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Mon, 30 May 2022 05:10:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 24UAAaZo027696; Mon, 30 May 2022 05:10:37 -0500 From: Rahul T R To: , , , , CC: , , , , , , , Rahul T R Subject: [PATCH v4 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property Date: Mon, 30 May 2022 15:40:29 +0530 Message-ID: <20220530101031.11357-2-r-ravikumar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220530101031.11357-1-r-ravikumar@ti.com> References: <20220530101031.11357-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a pattern property for clock-controller, also update the example with a clock-controller node Signed-off-by: Rahul T R Reviewed-by: Krzysztof Kozlowski --- .../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controll= er.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.= yaml index fa86691ebf16..73cffc45e056 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -48,6 +48,12 @@ patternProperties: description: This is the SERDES lane control mux. =20 + "^clock-controller@[0-9a-f]+$": + type: object + $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml# + description: + Clock provider for TI EHRPWM nodes. + required: - compatible - reg @@ -79,5 +85,11 @@ examples: <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; /* SERDES4 lane0/1/2/3 select */ }; + + clock-controller@4140 { + compatible =3D "ti,am654-ehrpwm-tbclk", "syscon"; + reg =3D <0x4140 0x18>; + #clock-cells =3D <1>; + }; }; ... --=20 2.17.1 From nobody Tue Apr 28 19:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0369C433EF for ; Mon, 30 May 2022 10:10:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235137AbiE3KK5 (ORCPT ); Mon, 30 May 2022 06:10:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235104AbiE3KKo (ORCPT ); Mon, 30 May 2022 06:10:44 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B6617B9CD; Mon, 30 May 2022 03:10:43 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 24UAAexd128833; Mon, 30 May 2022 05:10:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1653905440; bh=Cm/WTKOlldbkP44G+tdNcj1+LV6mVnmxMofMT1CSrxs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cn7lzY5dQMKePgVG3Y3V75kHu4lLwgA7pJ3WMVOAGo/jpted+wK7mgsw5nG002RXB SjxUPVyNDGjLcXKU1Xac0YVUGNqjiG35hJFQ9/QPZDwYKs0XH6weZiOFfKAZr3GcHr irK9vAU5FF8Y+CONaS4LTWURRAcYjBB8lM8g+PCM= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 24UAAe0u017197 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 30 May 2022 05:10:40 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 30 May 2022 05:10:39 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 30 May 2022 05:10:39 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 24UAAcKa071835; Mon, 30 May 2022 05:10:39 -0500 From: Rahul T R To: , , , , CC: , , , , , , , Vijay Pothukuchi , Rahul T R Subject: [PATCH v4 2/3] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs Date: Mon, 30 May 2022 15:40:30 +0530 Message-ID: <20220530101031.11357-3-r-ravikumar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220530101031.11357-1-r-ravikumar@ti.com> References: <20220530101031.11357-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vijay Pothukuchi Add dts nodes for 6 EHRPWM instances on SoC Signed-off-by: Vijay Pothukuchi Signed-off-by: Rahul T R --- .../dts/ti/k3-j721e-common-proc-board.dts | 24 +++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 ++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 +++++++ 3 files changed, 109 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2bc26a296496..f7d02fa4d6fc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -995,3 +995,27 @@ &main_mcan13 { status =3D "disabled"; }; + +&main_ehrpwm0 { + status =3D "disabled"; +}; + +&main_ehrpwm1 { + status =3D "disabled"; +}; + +&main_ehrpwm2 { + status =3D "disabled"; +}; + +&main_ehrpwm3 { + status =3D "disabled"; +}; + +&main_ehrpwm4 { + status =3D "disabled"; +}; + +&main_ehrpwm5 { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 43b6cf5791ee..1ee00b73905d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -66,7 +66,67 @@ #mux-control-cells =3D <1>; mux-reg-masks =3D <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible =3D "ti,am654-ehrpwm-tbclk", "syscon"; + reg =3D <0x4140 0x18>; + #clock-cells =3D <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x0 0x3000000 0x0 0x100>; + power-domains =3D <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x0 0x3010000 0x0 0x100>; + power-domains =3D <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x0 0x3020000 0x0 0x100>; + power-domains =3D <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x0 0x3030000 0x0 0x100>; + power-domains =3D <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x0 0x3040000 0x0 0x100>; + power-domains =3D <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; + clock-names =3D "tbclk", "fck"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible =3D "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x0 0x3050000 0x0 0x100>; + power-domains =3D <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; + clock-names =3D "tbclk", "fck"; }; =20 gic500: interrupt-controller@1800000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 80358cba6954..98a55778f3fe 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1129,3 +1129,27 @@ memory-region =3D <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; + +&main_ehrpwm0 { + status =3D "disabled"; +}; + +&main_ehrpwm1 { + status =3D "disabled"; +}; + +&main_ehrpwm2 { + status =3D "disabled"; +}; + +&main_ehrpwm3 { + status =3D "disabled"; +}; + +&main_ehrpwm4 { + status =3D "disabled"; +}; + +&main_ehrpwm5 { + status =3D "disabled"; +}; --=20 2.17.1 From nobody Tue Apr 28 19:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB8B3C433F5 for ; Mon, 30 May 2022 10:11:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235126AbiE3KLQ (ORCPT ); Mon, 30 May 2022 06:11:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235119AbiE3KKq (ORCPT ); Mon, 30 May 2022 06:10:46 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 956C37B9E2; Mon, 30 May 2022 03:10:45 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 24UAAgX5035369; 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Mon, 30 May 2022 05:10:41 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 24UAAebm071877; Mon, 30 May 2022 05:10:41 -0500 From: Rahul T R To: , , , , CC: , , , , , , , Sinthu Raja , Rahul T R Subject: [PATCH v4 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Date: Mon, 30 May 2022 15:40:31 +0530 Message-ID: <20220530101031.11357-4-r-ravikumar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220530101031.11357-1-r-ravikumar@ti.com> References: <20220530101031.11357-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sinthu Raja Add pinmux required to bring out i2c5, ehrpwm 2 and 3 and gpios on 40 pin RPi header on sk board Signed-off-by: Sinthu Raja Signed-off-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 89 ++++++++++++++++++++++---- 1 file changed, 78 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 98a55778f3fe..b913b18ae133 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -400,6 +400,57 @@ J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_S= CL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_S= DA */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ + >; + }; + + rpi_header_ehrpwm2_pins_default: rpi-header-ehrpwm2-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x178, PIN_INPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */ + J721E_IOPAD(0x17c, PIN_INPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */ + >; + }; + + rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x18c, PIN_INPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */ + J721E_IOPAD(0x190, PIN_INPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */ + >; + }; }; =20 &wkup_pmx0 { @@ -631,11 +682,6 @@ status =3D "disabled"; }; =20 -&main_i2c5 { - /* Brought out on RPi Header */ - status =3D "disabled"; -}; - &main_i2c6 { /* Unused */ status =3D "disabled"; @@ -1138,18 +1184,39 @@ status =3D "disabled"; }; =20 -&main_ehrpwm2 { +&main_ehrpwm4 { status =3D "disabled"; }; =20 -&main_ehrpwm3 { +&main_ehrpwm5 { status =3D "disabled"; }; =20 -&main_ehrpwm4 { - status =3D "disabled"; +&main_gpio0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rpi_header_gpio0_pins_default>; }; =20 -&main_ehrpwm5 { - status =3D "disabled"; +&main_gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rpi_header_gpio1_pins_default>; +}; + +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&main_ehrpwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rpi_header_ehrpwm2_pins_default>; + status =3D "okay"; +}; + +&main_ehrpwm3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rpi_header_ehrpwm3_pins_default>; + status =3D "okay"; }; --=20 2.17.1