From nobody Thu Apr 30 09:41:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09A10C433F5 for ; Fri, 27 May 2022 05:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243112AbiE0FSC (ORCPT ); Fri, 27 May 2022 01:18:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243040AbiE0FR4 (ORCPT ); Fri, 27 May 2022 01:17:56 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62B503136F for ; Thu, 26 May 2022 22:17:55 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id c2so3237539plh.2 for ; Thu, 26 May 2022 22:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bL6Df2//IX4pFAb3Mx3gzCPAvEMkloxMnWPx42+jX1U=; b=d7xy2wQwMsehdJ8/csAbRhdFHRV18FJbDigzTsdFFlSSx18qbpjC0am5y6/QiAfpcj nmlTpbhkNfvsqn0wbUmI3ZITCQuL5/Jhr8HQX26cMTHpYFzMYmIZBaZARS6wYNjGB3vU OM3OxoDyqQREhDzMtEfgnp8bf9uA5r1Z1yvF1AaU9kC8grC/YiEGX9KxN1vSwu4JFUMA rmdwqsfr4uTr1haJds9+Khdj+hSRoPEHGohpTWp+q3IMM7bL7ZNnmkMq0I8ea2v61M7g CltUt6/M4IpCeVd43fOOoANadsC8yFQ8YCa6835W/ofGDyfCsSyDgY0UTwE2aBlEEdbF 5KWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bL6Df2//IX4pFAb3Mx3gzCPAvEMkloxMnWPx42+jX1U=; b=vo53qI8V/HShVYVowuA51SzX/xPLj1VkOhj5hS2I5X1ID3+WBp7ZNCtSX68EjJqog3 Vsl7bCt7ZqLl+KaSM7T5b01VRnKLIkR/xG34qy+U3yLiFqVqfThfcWfWF75sPRTQj2cF n1/VI0INXrRWNjOHoiPCYKOwRzOxxP4r7V5pU5L2ZtmZrAGv/QGW5p/3+XO37Tsjm1bi FHmVWrd5993ZQgb/l5qsU+yRzGrHzjMPeWubANboiiMkU47RBXqgqr+UgcTIZ1eMX8oe JTSekh36IJE3aVc/xEg1kVQm9FS/1I9tiSxjQsFExxosTi5deYti21KS5vS+fvab1eqt fqjg== X-Gm-Message-State: AOAM531ifyWWJLCHmP5sA3OwRxzC3KidA7dg8yMiwcFverO2MXUvvTXh 0+VnEKV0kuftdB23tG4I2kNKQA== X-Google-Smtp-Source: ABdhPJxU939mlWe9n1bFBHQ99ErpSK3PeMu6xqSEXm+Yj6j7Li6zpY/7t6s9OhrsV8MSR7T1bqxiew== X-Received: by 2002:a17:903:228d:b0:163:8b78:c3c8 with SMTP id b13-20020a170903228d00b001638b78c3c8mr3585464plh.27.1653628674882; Thu, 26 May 2022 22:17:54 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id j34-20020a634a62000000b003c14af5063fsm2459003pgl.87.2022.05.26.22.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 22:17:54 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V3 1/5] riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 Date: Fri, 27 May 2022 10:47:39 +0530 Message-Id: <20220527051743.2829940-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527051743.2829940-1-sunilvl@ventanamicro.com> References: <20220527051743.2829940-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. Modify the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sb= i.c index 4f5a6f84e2a4..efa0f0816634 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -65,7 +65,7 @@ static int sbi_hsm_hart_get_status(unsigned long hartid) static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) { unsigned long boot_addr =3D __pa_symbol(secondary_start_sbi); - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); unsigned long hsm_data; struct sbi_hart_boot_data *bdata =3D &per_cpu(boot_data, cpuid); =20 @@ -107,7 +107,7 @@ static void sbi_cpu_stop(void) static int sbi_cpu_is_stopped(unsigned int cpuid) { int rc; - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); =20 rc =3D sbi_hsm_hart_get_status(hartid); =20 --=20 2.25.1 From nobody Thu Apr 30 09:41:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6DDBC433F5 for ; Fri, 27 May 2022 05:18:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243479AbiE0FSK (ORCPT ); Fri, 27 May 2022 01:18:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243101AbiE0FSB (ORCPT ); Fri, 27 May 2022 01:18:01 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C318F3138D for ; Thu, 26 May 2022 22:17:59 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id f18so3267775plg.0 for ; Thu, 26 May 2022 22:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a527G06H+rTZVQ9Z54L95xKvwRXeKSz+Vdkmm5vxnGU=; b=TzZc0MO6AfCtlteb9bCnmlhRJEVJvMRF3GI1QjfK6DuAUuzHwL6zhWECRnZ2JZl1JY Z77nIxa0np9ZOkDHvyfgQcFFUI8ptER4ES5juS2cPeaqTUslq9lNPZC+U7FuXLRK6TWd Qzy9wZ479GcfvWsXR1xDEHZK6oA7zDhwdg1oONTDxoMqhfpHKcUIQmqt+549nrdZWid7 ln0vEhIAy3enxkwU+BHpwnK85yTozOM3ylbmNXqK0dC0fv4bMhROtEtVaeyM1tW4lBXP PK8nbF9aa4gb1QSDcJQE5slBaG9QgWoDlQ+mHUizYCzh/JBX14DiPHQMLGLnFIvMhK9B 342Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a527G06H+rTZVQ9Z54L95xKvwRXeKSz+Vdkmm5vxnGU=; b=IvT8tcDhn6BjLWgTmwO6ZJuV6FF8Dqukel7w+7bpkXz9728r2wRXgzdNAwsaEPC6s9 zqm46TJdswXAjWNgEKhnBA4o+I6ZwforXlF7zh+m2mTHHEBzN6y0o9cTJUiIZTYzYQng Ep9r8ZEpU4XtEULs9IQ39V4yd3sppkvl+53+REW49DVxFkuEcUyYwmckSPkRMX4m9xrl huFgQXCA810cRGJy0KFXr+M4W2IcJEcTEuKKJY4zsx05XQgEJwhDM39aS+vFbkNRRMY/ 5xWfJsyhfKethfs7funA2JJl+KUtMh0UkEaKPipWfyzLOtff5rqEOnSAh0KyvFcXriKD oexg== X-Gm-Message-State: AOAM530S+dFs1UoEiT/RZoOO+Eyl//rnBXOeTNS9V641wmg9NiFiBHgi TBbiu6JTs2NNuNjh6189P3qsCQ== X-Google-Smtp-Source: ABdhPJww0P7BfKdwPMxOyVsREAc1pWap5/VTK+ciOW5Olpxk9SeJR3sDpMVAMRIM6moUHTH/ZUTdXw== X-Received: by 2002:a17:902:cecc:b0:162:4d5c:3eac with SMTP id d12-20020a170902cecc00b001624d5c3eacmr15415645plg.82.1653628679351; Thu, 26 May 2022 22:17:59 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id j34-20020a634a62000000b003c14af5063fsm2459003pgl.87.2022.05.26.22.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 22:17:58 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L , stable@vger.kernel.org Subject: [PATCH V3 2/5] riscv: spinwait: Fix hartid variable type Date: Fri, 27 May 2022 10:47:40 +0530 Message-Id: <20220527051743.2829940-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527051743.2829940-1-sunilvl@ventanamicro.com> References: <20220527051743.2829940-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid variable is of type int but compared with ULONG_MAX(INVALID_HARTID). This issue is fixed by changing the hartid variable type to unsigned long. Fixes: c78f94f35cf6 ("RISC-V: Use __cpu_up_stack/task_pointer only for spin= wait method") Cc: stable@vger.kernel.org Signed-off-by: Sunil V L Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu_ops_spinwait.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_o= ps_spinwait.c index 346847f6c41c..3ade9152a3c7 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".da= ta"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); =20 /* * The hartid must be less than NR_CPUS to avoid out-of-bound access @@ -27,7 +27,7 @@ static void cpu_update_secondary_bootdata(unsigned int cp= uid, * spinwait booting is not the recommended approach for any platforms * booting Linux in S-mode and can be disabled in the future. */ - if (hartid =3D=3D INVALID_HARTID || hartid >=3D NR_CPUS) + if (hartid =3D=3D INVALID_HARTID || hartid >=3D (unsigned long) NR_CPUS) return; =20 /* Make sure tidle is updated */ --=20 2.25.1 From nobody Thu Apr 30 09:41:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D1FC433EF for ; Fri, 27 May 2022 05:18:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243040AbiE0FSV (ORCPT ); Fri, 27 May 2022 01:18:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243253AbiE0FSI (ORCPT ); Fri, 27 May 2022 01:18:08 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 014DA3190C for ; Thu, 26 May 2022 22:18:03 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id m14-20020a17090a414e00b001df77d29587so6207289pjg.2 for ; Thu, 26 May 2022 22:18:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y6kuVNgzuJS/Kj6UaKHoVmtYOVzfNBOjCT817HUi7zA=; b=oJAxQxrd2Jt3TYFo94eMzAsBg8hvvQFF9aSeDB/A+fB8tsaMUMkb5IXJQ6HbX9tmmG tUSqV6uLdpCmBe0FHOICUI8YT/ufNZwQV802XZm4u4C/1nFYr++PzjYw5y3G6Zce3sWB F7vMcSuSqs8tppVLuq1oV/IAlVKYTyMcJB2E1dpzFsygxMNja78Uul1LhCqSOu/Ip2+I a3pH5HExzRPDEunHrqQRDdBYpqOvPIy6lZlf/4aS+gqLkozivrjUKEPg49r1z9BQgHGt sfINzzPOQ4cjOG4T3yMFHP7HeAiUzw32D2U7CUiBF384S//wJoT/oe+c9OrUV5xIXfIF 20jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y6kuVNgzuJS/Kj6UaKHoVmtYOVzfNBOjCT817HUi7zA=; b=EJlQdy53K3brFmttpyIsBC0Ben5m3WRGfilYcsNYj7CJAV+zO5sxogZNHyyw/S7cq1 ZP5FmejgkTTTSLOyAoUvVqwIyYCB0BnJq0IZr1xXpxpZSK2K1HfrAcfuEbgnXmr8a6/9 G9UhFx2wSOntVw/k4XHPyA+NwglR8lsquP+Lg3AroKMJrfTGQ7XTZNnVExgDNNRxfczt 9Hlz/z27AdfdL0i87hqCD8l7pZj/PUvXAOOan/nwnto2dr9tYKMpVkqW9nFJyeIHQckA gMbA5PHUqt5Np1u6WrejD7FEXO10GNqU1zv1LlXsEtiesOMquDhbuc5Wm1nNwEdScP1j Ws3w== X-Gm-Message-State: AOAM530+c1yH7ya5QgXcmIuJFU/7FBO//lGMNkqO3fMOFrcF+HU0sX4V Bui2PV8EYYCMnVE7l0gHXNQATQ== X-Google-Smtp-Source: ABdhPJxNHAA7YtmlpCTaoLU9Je5eUyJxrNCvecvMqG8B873dWMhvfzophWQNCIAWw+WYsWH8YLAzrg== X-Received: by 2002:a17:902:c1c6:b0:163:8394:9d34 with SMTP id c6-20020a170902c1c600b0016383949d34mr4742595plc.78.1653628683388; Thu, 26 May 2022 22:18:03 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id j34-20020a634a62000000b003c14af5063fsm2459003pgl.87.2022.05.26.22.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 22:18:03 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V3 3/5] riscv: smp: Add 64bit hartid support on RV64 Date: Fri, 27 May 2022 10:47:41 +0530 Message-Id: <20220527051743.2829940-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527051743.2829940-1-sunilvl@ventanamicro.com> References: <20220527051743.2829940-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. Modify the hartid parameter in riscv_hartid_to_cpuid() as unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/include/asm/smp.h | 4 ++-- arch/riscv/kernel/smp.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 23170c933d73..d3443be7eedc 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mas= k); /* Hook for the generic smp_call_function_single() routine. */ void arch_send_call_function_single_ipi(int cpu); =20 -int riscv_hartid_to_cpuid(int hartid); +int riscv_hartid_to_cpuid(unsigned long hartid); =20 /* Set custom IPI operations */ void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int= prec) { } =20 -static inline int riscv_hartid_to_cpuid(int hartid) +static inline int riscv_hartid_to_cpuid(unsigned long hartid) { if (hartid =3D=3D boot_cpu_hartid) return 0; diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b5d30ea92292..018e7dc45df6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -47,7 +47,7 @@ static struct { unsigned long bits ____cacheline_aligned; } ipi_data[NR_CPUS] __cacheline_aligned; =20 -int riscv_hartid_to_cpuid(int hartid) +int riscv_hartid_to_cpuid(unsigned long hartid) { int i; =20 @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid) if (cpuid_to_hartid_map(i) =3D=3D hartid) return i; =20 - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); return -ENOENT; } =20 --=20 2.25.1 From nobody Thu Apr 30 09:41:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8BDDC433F5 for ; Fri, 27 May 2022 05:18:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243553AbiE0FSa (ORCPT ); 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Thu, 26 May 2022 22:18:07 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V3 4/5] riscv: cpu: Add 64bit hartid support on RV64 Date: Fri, 27 May 2022 10:47:42 +0530 Message-Id: <20220527051743.2829940-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527051743.2829940-1-sunilvl@ventanamicro.com> References: <20220527051743.2829940-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. Add support for 64bit hartid in riscv_of_processor_hartid() and update its callers. Signed-off-by: Sunil V L Reviewed-by: Atish Patra --- arch/riscv/include/asm/processor.h | 4 ++-- arch/riscv/kernel/cpu.c | 26 +++++++++++++++----------- arch/riscv/kernel/cpufeature.c | 6 ++++-- arch/riscv/kernel/smpboot.c | 9 +++++---- drivers/clocksource/timer-riscv.c | 15 ++++++++------- drivers/irqchip/irq-riscv-intc.c | 7 ++++--- drivers/irqchip/irq-sifive-plic.c | 7 ++++--- 7 files changed, 42 insertions(+), 32 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 0749924d9e55..99fae9398506 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,8 +75,8 @@ static inline void wait_for_interrupt(void) } =20 struct device_node; -int riscv_of_processor_hartid(struct device_node *node); -int riscv_of_parent_hartid(struct device_node *node); +int riscv_of_processor_hartid(struct device_node *node, unsigned long *har= tid); +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid= ); =20 extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struc= t *src); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..477a33b34c95 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -14,37 +14,36 @@ * Returns the hart ID of the given device tree node, or -ENODEV if the no= de * isn't an enabled and valid RISC-V hart node. */ -int riscv_of_processor_hartid(struct device_node *node) +int riscv_of_processor_hartid(struct device_node *node, unsigned long *har= t) { const char *isa; - u32 hart; =20 if (!of_device_is_compatible(node, "riscv")) { pr_warn("Found incompatible CPU\n"); return -ENODEV; } =20 - hart =3D of_get_cpu_hwid(node, 0); - if (hart =3D=3D ~0U) { + *hart =3D (unsigned long) of_get_cpu_hwid(node, 0); + if (*hart =3D=3D ~0UL) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; } =20 if (!of_device_is_available(node)) { - pr_info("CPU with hartid=3D%d is not available\n", hart); + pr_info("CPU with hartid=3D%lu is not available\n", *hart); return -ENODEV; } =20 if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=3D%d has no \"riscv,isa\" property\n", hart); + pr_warn("CPU with hartid=3D%lu has no \"riscv,isa\" property\n", *hart); return -ENODEV; } if (isa[0] !=3D 'r' || isa[1] !=3D 'v') { - pr_warn("CPU with hartid=3D%d has an invalid ISA of \"%s\"\n", hart, isa= ); + pr_warn("CPU with hartid=3D%lu has an invalid ISA of \"%s\"\n", *hart, i= sa); return -ENODEV; } =20 - return hart; + return 0; } =20 /* @@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node) * To achieve this, we walk up the DT tree until we find an active * RISC-V core (HART) node and extract the cpuid from it. */ -int riscv_of_parent_hartid(struct device_node *node) +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) { + int rc; + for (; node; node =3D node->parent) { - if (of_device_is_compatible(node, "riscv")) - return riscv_of_processor_hartid(node); + if (of_device_is_compatible(node, "riscv")) { + rc =3D riscv_of_processor_hartid(node, hartid); + if (!rc) + return 0; + } } =20 return -1; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..49c05bd9352d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -67,8 +67,9 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; + int i, j, rc; static unsigned long isa2hwcap[256] =3D {0}; + unsigned long hartid; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; isa2hwcap['m'] =3D isa2hwcap['M'] =3D COMPAT_HWCAP_ISA_M; @@ -86,7 +87,8 @@ void __init riscv_fill_hwcap(void) DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; =20 - if (riscv_of_processor_hartid(node) < 0) + rc =3D riscv_of_processor_hartid(node, &hartid); + if (rc < 0) continue; =20 if (of_property_read_string(node, "riscv,isa", &isa)) { diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..4336610a19ee 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -76,15 +76,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) void __init setup_smp(void) { struct device_node *dn; - int hart; + unsigned long hart; bool found_boot_cpu =3D false; int cpuid =3D 1; + int rc; =20 cpu_set_ops(0); =20 for_each_of_cpu_node(dn) { - hart =3D riscv_of_processor_hartid(dn); - if (hart < 0) + rc =3D riscv_of_processor_hartid(dn, &hart); + if (rc < 0) continue; =20 if (hart =3D=3D cpuid_to_hartid_map(0)) { @@ -94,7 +95,7 @@ void __init setup_smp(void) continue; } if (cpuid >=3D NR_CPUS) { - pr_warn("Invalid cpuid [%d] for hartid [%d]\n", + pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", cpuid, hart); continue; } diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 1767f8bf2013..55142c27f0bc 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, voi= d *dev_id) =20 static int __init riscv_timer_init_dt(struct device_node *n) { - int cpuid, hartid, error; + int cpuid, error; + unsigned long hartid; struct device_node *child; struct irq_domain *domain; =20 - hartid =3D riscv_of_processor_hartid(n); - if (hartid < 0) { - pr_warn("Not valid hartid for node [%pOF] error =3D [%d]\n", + error =3D riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Not valid hartid for node [%pOF] error =3D [%lu]\n", n, hartid); - return hartid; + return error; } =20 cpuid =3D riscv_hartid_to_cpuid(hartid); if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); return cpuid; } =20 @@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_nod= e *n) return -ENODEV; } =20 - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", + pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", __func__, cpuid, hartid); error =3D clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index b65bd8878d4f..499e5f81b3fe 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_op= s =3D { static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc, hartid; + int rc; + unsigned long hartid; =20 - hartid =3D riscv_of_parent_hartid(node); - if (hartid < 0) { + rc =3D riscv_of_parent_hartid(node, &hartid); + if (rc < 0) { pr_warn("unable to find hart id for %pOF\n", node); return 0; } diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index bb87e4c3b88e..4710d9741f36 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -317,7 +317,8 @@ static int __init plic_init(struct device_node *node, for (i =3D 0; i < nr_contexts; i++) { struct of_phandle_args parent; irq_hw_number_t hwirq; - int cpu, hartid; + int cpu; + unsigned long hartid; =20 if (of_irq_parse_one(node, i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); @@ -341,8 +342,8 @@ static int __init plic_init(struct device_node *node, continue; } =20 - hartid =3D riscv_of_parent_hartid(parent.np); - if (hartid < 0) { + error =3D riscv_of_parent_hartid(parent.np, &hartid); + if (error < 0) { pr_warn("failed to parse hart ID for context %d.\n", i); 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Thu, 26 May 2022 22:18:11 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id j34-20020a634a62000000b003c14af5063fsm2459003pgl.87.2022.05.26.22.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 22:18:11 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V3 5/5] riscv/efi_stub: Add 64bit boot-hartid support on RV64 Date: Fri, 27 May 2022 10:47:43 +0530 Message-Id: <20220527051743.2829940-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527051743.2829940-1-sunilvl@ventanamicro.com> References: <20220527051743.2829940-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The boot-hartid can be a 64bit value on RV64 platforms but the "boot-hartid" in DT is assumed to be 32bit only. Detect the size of the "boot-hartid" in DT and use 32bit or 64bit read appropriately. Signed-off-by: Sunil V L --- drivers/firmware/efi/libstub/riscv-stub.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/e= fi/libstub/riscv-stub.c index 9e85e58d1f27..b450ebf95977 100644 --- a/drivers/firmware/efi/libstub/riscv-stub.c +++ b/drivers/firmware/efi/libstub/riscv-stub.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 #include "efistub.h" =20 @@ -29,7 +30,7 @@ static int get_boot_hartid_from_fdt(void) { const void *fdt; int chosen_node, len; - const fdt32_t *prop; + const void *prop; =20 fdt =3D get_efi_config_table(DEVICE_TREE_GUID); if (!fdt) @@ -40,10 +41,16 @@ static int get_boot_hartid_from_fdt(void) return -EINVAL; =20 prop =3D fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); - if (!prop || len !=3D sizeof(u32)) + if (!prop) + return -EINVAL; + + if (len =3D=3D sizeof(u32)) + hartid =3D (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); + else if (len =3D=3D sizeof(u64)) + hartid =3D (unsigned long) fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)= ); + else return -EINVAL; =20 - hartid =3D fdt32_to_cpu(*prop); return 0; } =20 --=20 2.25.1