From nobody Tue Dec 23 10:47:52 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96A14C433EF for ; Fri, 27 May 2022 04:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238560AbiE0Eac (ORCPT ); Fri, 27 May 2022 00:30:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241943AbiE0E36 (ORCPT ); Fri, 27 May 2022 00:29:58 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADB46EC33F for ; Thu, 26 May 2022 21:29:56 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id s14so3150090plk.8 for ; Thu, 26 May 2022 21:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PGyMM2fCHEPDPTo3f1L77jTuUtX2Qs605Nd7DQvcVL8=; b=WCviYB4oHNo8OjkmxySSNqpahg6CH5EJo9BSJ+0C+BhRXfwBmN6euX916TU/AVOphx VuX5pvkUSSXrGdAY2IE/A7gBl5HC2DPcK0Dj+1OTC4+lwqu7lC5LtTRZS06LnsmNSh1h D+8ti+044oZ76Ux5Wno9EmMGIRiomm8RkTsJEsEpy05Hs7qXQwFduK1cXfKw84JSYrPF KgZlx4rD+ccL0vT52cPYzFpT03pY4B+hzXUwRPyHtWnObOutgG2PQteNFv/ovSWkg3ck b/KTWrmSwy1cjYIxB/eF/VaLt33N3VKxXTWVzb2PKLP8VRaMY20T65wtpN/vh/VxwmZP kPUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PGyMM2fCHEPDPTo3f1L77jTuUtX2Qs605Nd7DQvcVL8=; b=Dp1VmSQD470dWVC/4yNwOqyml4LAJ0x78Qt2VKJn/3e564+zJ7nhL/EtPDwdtESYpX eNvn8mCatFskq4bEs0KzGcmrI6HHaDjC68kbV01bPFfL0lWuqltBKbK5/QhYY8zZlcoL 8MD2EfWQP/JtDfBlAmJGLzHeJ07IZmxRK+IaqUem4O/VGEDFRJogbebEImbVbNC89xPj PJKxp9mJh9DbcGrE3KWEw1qNb6XOgLzzA6gxCT0pmL4CGw2anEZhtWULYy8bA6UA41fv MCSwAWGMbVR7AF4pUoECi4unl4xwrlrWNh/LfJ6PhSvmYoaTFEx2qYyGAkbubK/5UaeC KSHA== X-Gm-Message-State: AOAM533SgCuy0sSJxtmKm4dJxtcKrqvLvn6LPJhQGvVRLacMjFPWABIf 8e0cqgLm27pq3mmKE0a+CRCZymdZDzWWeA== X-Google-Smtp-Source: ABdhPJzFPD8cs7ZuK6APWQK76iXRZUSFt5yFJ8vtFEx0+aPBg86flIe0KEDvQCWD7WqeremAYzT7fQ== X-Received: by 2002:a17:902:c2d0:b0:15a:2344:f8a4 with SMTP id c16-20020a170902c2d000b0015a2344f8a4mr40912686pla.28.1653625795766; Thu, 26 May 2022 21:29:55 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id y63-20020a638a42000000b003fadfd7be5asm2352307pgd.18.2022.05.26.21.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 21:29:55 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Jisheng Zhang , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v4 4/4] RISC-V: KVM: Support sstc extension Date: Thu, 26 May 2022 21:29:37 -0700 Message-Id: <20220527042937.1124009-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527042937.1124009-1-atishp@rivosinc.com> References: <20220527042937.1124009-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sstc extension allows the guest to program the vstimecmp CSR directly instead of making an SBI call to the hypervisor to program the next event. The timer interrupt is also directly injected to the guest by the hardware in this case. To maintain backward compatibility, the hypervisors also update the vstimecmp in an SBI set_time call if the hardware supports it. Thus, the older kernels in guest also take advantage of the sstc extension. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/main.c | 12 +- arch/riscv/kvm/vcpu.c | 5 +- arch/riscv/kvm/vcpu_timer.c | 144 +++++++++++++++++++++++- 5 files changed, 161 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/a= sm/kvm_vcpu_timer.h index 375281eb49e0..a24a265f3ccb 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -28,6 +28,11 @@ struct kvm_vcpu_timer { u64 next_cycles; /* Underlying hrtimer instance */ struct hrtimer hrt; + + /* Flag to check if sstc is enabled or not */ + bool sstc_enabled; + /* A function pointer to switch between stimecmp or hrtimer at runtime */ + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles); }; =20 int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles); @@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu); int kvm_riscv_guest_timer_init(struct kvm *kvm); - +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu); #endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 92bd469e2ba6..d2f02ba1947a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_H, KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 2e5ca43c8c49..83c4db7fc35f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque) =20 int kvm_arch_hardware_enable(void) { - unsigned long hideleg, hedeleg; + unsigned long hideleg, hedeleg, henvcfg; =20 hedeleg =3D 0; hedeleg |=3D (1UL << EXC_INST_MISALIGNED); @@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void) =20 csr_write(CSR_HCOUNTEREN, -1UL); =20 + if (riscv_isa_extension_available(NULL, SSTC)) { +#ifdef CONFIG_64BIT + henvcfg =3D csr_read(CSR_HENVCFG); + csr_write(CSR_HENVCFG, henvcfg | 1UL<arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); =20 + kvm_riscv_vcpu_timer_save(vcpu); + csr->vsstatus =3D csr_read(CSR_VSSTATUS); csr->vsie =3D csr_read(CSR_VSIE); csr->vstvec =3D csr_read(CSR_VSTVEC); diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 5c4c37ff2d48..6c7a1a81eafd 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_t= imer *t) return 0; } =20 -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncyc= les) +{ +#if defined(CONFIG_32BIT) + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF); + csr_write(CSR_VSTIMECMPH, ncycles >> 32); +#else + csr_write(CSR_VSTIMECMP, ncycles); +#endif + return 0; +} + +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycle= s) { struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; struct kvm_guest_timer *gt =3D &vcpu->kvm->arch.timer; @@ -88,6 +99,65 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcp= u, u64 ncycles) return 0; } =20 +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +{ + struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; + + return t->timer_next_event(vcpu, ncycles); +} + +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer = *h) +{ + u64 delta_ns; + struct kvm_vcpu_timer *t =3D container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu =3D container_of(t, struct kvm_vcpu, arch.timer); + struct kvm_guest_timer *gt =3D &vcpu->kvm->arch.timer; + + if (kvm_riscv_current_cycles(gt) < t->next_cycles) { + delta_ns =3D kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t); + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns)); + return HRTIMER_RESTART; + } + + t->next_set =3D false; + kvm_vcpu_kick(vcpu); + + return HRTIMER_NORESTART; +} + +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; + struct kvm_guest_timer *gt =3D &vcpu->kvm->arch.timer; + + if (!kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t) || + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER)) + return true; + else + return false; +} + +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; + struct kvm_guest_timer *gt =3D &vcpu->kvm->arch.timer; + u64 delta_ns; + + if (!t->init_done) + return; + + delta_ns =3D kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t); + if (delta_ns) { + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL); + t->next_set =3D true; + } +} + +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} + int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -180,10 +250,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) return -EINVAL; =20 hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - t->hrt.function =3D kvm_riscv_vcpu_hrtimer_expired; t->init_done =3D true; t->next_set =3D false; =20 + /* Enable sstc for every vcpu if available in hardware */ + if (riscv_isa_extension_available(NULL, SSTC)) { + t->sstc_enabled =3D true; + t->hrt.function =3D kvm_riscv_vcpu_vstimer_expired; + t->timer_next_event =3D kvm_riscv_vcpu_update_vstimecmp; + } else { + t->sstc_enabled =3D false; + t->hrt.function =3D kvm_riscv_vcpu_hrtimer_expired; + t->timer_next_event =3D kvm_riscv_vcpu_update_hrtimer; + } + return 0; } =20 @@ -199,21 +279,73 @@ int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu) =20 int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) { + struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; + + t->next_cycles =3D -1ULL; return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); } =20 -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu) { struct kvm_guest_timer *gt =3D &vcpu->kvm->arch.timer; =20 -#ifdef CONFIG_64BIT - csr_write(CSR_HTIMEDELTA, gt->time_delta); -#else +#if defined(CONFIG_32BIT) csr_write(CSR_HTIMEDELTA, (u32)(gt->time_delta)); csr_write(CSR_HTIMEDELTAH, (u32)(gt->time_delta >> 32)); +#else + csr_write(CSR_HTIMEDELTA, gt->time_delta); #endif } =20 +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; + + kvm_riscv_vcpu_update_timedelta(vcpu); + + if (!t->sstc_enabled) + return; + + csr =3D &vcpu->arch.guest_csr; +#if defined(CONFIG_32BIT) + csr_write(CSR_VSTIMECMP, (u32)t->next_cycles); + csr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32)); +#else + csr_write(CSR_VSTIMECMP, t->next_cycles); +#endif + + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + kvm_riscv_vcpu_timer_unblocking(vcpu); +} + +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t =3D &vcpu->arch.timer; + + if (!t->sstc_enabled) + return; + + csr =3D &vcpu->arch.guest_csr; + t =3D &vcpu->arch.timer; +#if defined(CONFIG_32BIT) + t->next_cycles =3D csr_read(CSR_VSTIMECMP); + t->next_cycles |=3D (u64)csr_read(CSR_VSTIMECMPH) << 32; +#else + t->next_cycles =3D csr_read(CSR_VSTIMECMP); +#endif + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + if (kvm_vcpu_is_blocking(vcpu)) + kvm_riscv_vcpu_timer_blocking(vcpu); +} + int kvm_riscv_guest_timer_init(struct kvm *kvm) { struct kvm_guest_timer *gt =3D &kvm->arch.timer; --=20 2.25.1