From nobody Fri May 1 08:39:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1520C433F5 for ; Thu, 26 May 2022 10:11:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346970AbiEZKLu (ORCPT ); Thu, 26 May 2022 06:11:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346960AbiEZKLo (ORCPT ); Thu, 26 May 2022 06:11:44 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4ACFE10EC for ; Thu, 26 May 2022 03:11:43 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id n10so1340322pjh.5 for ; Thu, 26 May 2022 03:11:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R1Oz1yAZDHQvhQh2SWx4vMTfkt8zOrGF2iQud75B5Lk=; b=MeBvlYLKJh6EnE4Nk4fnvlwLHRYUqSTpb3CTh8pn85TV32ZdSCclJiU4pcvaTDtwkA RZbKn8P//rgHWSQg9zJ8xqvTjG1wd8fm2yEN7plSFM4jAukcfO5ZPNZLN62yaHGP446f OsYZwKq12ORSAtDuUkFSQa3gr9WaXe7cH1K+StKOeIZS26YGAlqMye3q8lokxQ5dSMcF jKEKvVeOJ9qWyneCm3ObTYXlMLJK1mEq5SeCL4CISyt3QDyZVcMYYWoKUkSRXRt/iNOJ y+BTc8jKia4Tyw239NwQz9dEOEI5n8gY6PO71NKx3vrvGN9W1RCwgirGLD4gqqsJjqf3 ohBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R1Oz1yAZDHQvhQh2SWx4vMTfkt8zOrGF2iQud75B5Lk=; b=7hrOVCH9iofrklw1ufgyPFRo9o38M4ZYbybKRPX2cOEap86T77pwg8mBtYiU55ZnH5 eCS4Volaxk2Tbi/JVQdEciAFsSxGBnY3qoyuQ7ystOD6+cBbhVLQ2ZJocEODZSrc1u0J 3o/US9hM8RgFYLQidXaV4xocGfBugDeDVgyF7uq8aBrcn8zobf2hFuZnNt3kTkRBEiqp vkjp+LYHrgeZ1LHrkzauRhnBJyBcyAFHMQNW4pwcrdeCLDkmxdTFhQeNgn+lLSEFnZyz fZGqS0jNOksL3ixS9lNP56Ud8vQqzBRYVUBKXrv/lMCL6J/7uQy+wU20ZCVvTDLVeYM6 MBgQ== X-Gm-Message-State: AOAM5317YEUO491rFM5YzFTRbYavdIg26IBC7Z90+N/AecJazdFWBR1S Gm+KhgcYGJjYVFmO0WDAHbOUVif4WnTg+kbF X-Google-Smtp-Source: ABdhPJyAv5zPzU2IwZPeCQVSm/VsddqxuggiHGPcUvNa4rsGUhxfdC58ncib9zaXi0NWNziwb/aigQ== X-Received: by 2002:a17:902:8bca:b0:15f:28b6:ad46 with SMTP id r10-20020a1709028bca00b0015f28b6ad46mr37153228plo.69.1653559902867; Thu, 26 May 2022 03:11:42 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:42 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid Date: Thu, 26 May 2022 15:41:27 +0530 Message-Id: <20220526101131.2340729-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sb= i.c index 4f5a6f84e2a4..efa0f0816634 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -65,7 +65,7 @@ static int sbi_hsm_hart_get_status(unsigned long hartid) static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) { unsigned long boot_addr =3D __pa_symbol(secondary_start_sbi); - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); unsigned long hsm_data; struct sbi_hart_boot_data *bdata =3D &per_cpu(boot_data, cpuid); =20 @@ -107,7 +107,7 @@ static void sbi_cpu_stop(void) static int sbi_cpu_is_stopped(unsigned int cpuid) { int rc; - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); =20 rc =3D sbi_hsm_hart_get_status(hartid); =20 --=20 2.25.1 From nobody Fri May 1 08:39:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE418C433EF for ; Thu, 26 May 2022 10:11:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346974AbiEZKLz (ORCPT ); Thu, 26 May 2022 06:11:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346972AbiEZKLu (ORCPT ); Thu, 26 May 2022 06:11:50 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BB021145 for ; Thu, 26 May 2022 03:11:47 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id cs3-20020a17090af50300b001e0808b5838so1349695pjb.1 for ; Thu, 26 May 2022 03:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wbBG7lEDJH2LFVXucK5oQ/R2hCfil/fSiH5Kza4Gi8k=; b=V5XR0cYmYpPHz45TXlrQdMJrLi9mC6lsy2W+x/KJ31gATxWb3Jcl0MrAB+D24bI7f3 4cWVas5pCyylxxCZLBWe4mQfSoke/VDU2WYlrymgElTYZAOaG723fCyOoELiQShkPJOT 1JZwGsy0Lp23kfxFyXK4dhbP3HKfGwYOKkJB0bxLkU+akzyGUbizbF/W22JUzStz/kvb /YZE17RoALpfuH1WSU7xai3fAWdlXw2P6hUoIe1PwT4W09BwfsX4JWi9svdHWlFZSnTi XZgvOErgNi8zbTcAf6Ej1LPhdSLC9CuCpS7dDMCmuN5koT27cwVrnYTiCV3TrhPaZwT8 /aOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wbBG7lEDJH2LFVXucK5oQ/R2hCfil/fSiH5Kza4Gi8k=; b=4h0y+7hxUYLdtVZxu6Bt2p/UET5DKt+jYdvbxOEANlRKikn7SpBpCXfPzmljUa7w4i sKL7lWkxqnHER8qdTwOtWMu/eU+yrLIX6WboTrQiRhYbhd+x6HELFEZ+o9bcfWJQAwp/ ++gze/tRnP8n/ASsEHWeNFM6Ym0siLuKfv8nxHmSkzegmvZMa6yd9OhefO/jOd2berfT ufEmsV88+D7IBGLMRl6tN5LiOCtfgXiSC/c0jf9jLzGaZsVVHbaN/a/5jr35f48/UfHq npcxL2NVv2ytsmdphN0KiEQ8GN2EuQiPkxQ1xkhK5rvSM0Y6MrJ5qeAEcshTnM4L6+Z6 BH+A== X-Gm-Message-State: AOAM533O0Q6iP4qtdxUKOm3xiybrCZN+a7oEkb8ssUG2MS+B6pn4zRbQ nFv64YT5u/DyCeiLlAgg86QsEQ== X-Google-Smtp-Source: ABdhPJwr+qQVKMcopGMW+cRM74SlJB+kkVtaSsSNVzIL44tSlSNiDBT302sF2fUP6vTOWuit+8GjCQ== X-Received: by 2002:a17:902:d50e:b0:163:80b4:30a3 with SMTP id b14-20020a170902d50e00b0016380b430a3mr937520plg.159.1653559907098; Thu, 26 May 2022 03:11:47 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:46 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L , stable@vger.kernel.org Subject: [PATCH V2 2/5] riscv: spinwait: Fix hartid variable type Date: Thu, 26 May 2022 15:41:28 +0530 Message-Id: <20220526101131.2340729-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid variable is of type int but compared with ULONG_MAX(INVALID_HARTID). This issue is fixed by changing the hartid variable type to unsigned long. Fixes: c78f94f35cf6 ("RISC-V: Use __cpu_up_stack/task_pointer only for spin= wait method") Cc: stable@vger.kernel.org Signed-off-by: Sunil V L Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu_ops_spinwait.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_o= ps_spinwait.c index 346847f6c41c..3ade9152a3c7 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".da= ta"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); =20 /* * The hartid must be less than NR_CPUS to avoid out-of-bound access @@ -27,7 +27,7 @@ static void cpu_update_secondary_bootdata(unsigned int cp= uid, * spinwait booting is not the recommended approach for any platforms * booting Linux in S-mode and can be disabled in the future. */ - if (hartid =3D=3D INVALID_HARTID || hartid >=3D NR_CPUS) + if (hartid =3D=3D INVALID_HARTID || hartid >=3D (unsigned long) NR_CPUS) return; =20 /* Make sure tidle is updated */ --=20 2.25.1 From nobody Fri May 1 08:39:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91F5BC433EF for ; Thu, 26 May 2022 10:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346982AbiEZKMF (ORCPT ); Thu, 26 May 2022 06:12:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346988AbiEZKL4 (ORCPT ); Thu, 26 May 2022 06:11:56 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD1051113 for ; Thu, 26 May 2022 03:11:51 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id n8so1079787plh.1 for ; Thu, 26 May 2022 03:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3wURJ7f8wK/rYX1AWremJ6WWxVIvdF4W4fcHK+urU4Y=; b=lGJPvC3W+KdDytFN09EumhPJrVSmrwGdIlDlX0GeN/DoMzCv8kpUJVZJ3ZwxjFOOW3 bc3zhkW3fIOhwGJRYktfEaa6VNws2H+5LeTtokOCeN7bGS0nVMAdKnCv/A1bWKN7GVQg 7l9zc2sLOaEwGo/OCT8s09I3+rVZEiuGWAX6JEr/moa/ahGPNGvoq2coD9OCgH0p2ybK 8um1khDECGbpWGLs20DbAfVxDv4gd4sfJt1KiyrK9oeHpJtqHsj7m3s4qUAA3EYTiml1 RcZeE0Hm7CulTjv7sdEW5sdjPx+nXybfeWjLOZxocdhADUQdz6Ry1qcD3twvtA/wV+mt n8aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3wURJ7f8wK/rYX1AWremJ6WWxVIvdF4W4fcHK+urU4Y=; b=8LaKR+uHpG0pw/4jMQHWc5dAWbh/Q/ju3jWw3g8DFL/TKcO1U1ymYBsepX3wZ6HENq cC0bEtLTU/3IjRLR2ecyIiBsN6Kr1E3XoSfICjBG40qfpXxVL1JzczB2LwK6N8GwiWsU Lq+lADPDtF+3bjqM9K1b2BjC7MET9KO9LnZM2ImjRmIvyCDegLJyE1VchojXz7RUp4tk XUxgRVnfKmsjCqvj1wcWgKGeNRxZ+9t2HDgAzP8psqGztUIsgV5LKNn0yHwiXUQZV5Xn m3GuHUBi3rE2HygWzBp5tPYOBIsbTqZ4nibiB5GQeaOhhD5t8BIWhhPOyiAApE5B1udq qSGQ== X-Gm-Message-State: AOAM530YV6toQ4hgV/GX2JAPLubTnwLSklWHeGSm1s4NhqQ5/kx3jA5d RVjE7AkJtLyzB7+lh3mvFHXXMA== X-Google-Smtp-Source: ABdhPJyHqPUWM6TLaBadwtJgoFX8sqXAz9turIY6bW9WSl9x0ZGa0cM73mxFnfgICJ1iaqcFQ+3yLw== X-Received: by 2002:a17:902:e14c:b0:163:86e0:2137 with SMTP id d12-20020a170902e14c00b0016386e02137mr122325pla.89.1653559911140; Thu, 26 May 2022 03:11:51 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:50 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 3/5] riscv: smp: Support for 64bit hartid Date: Thu, 26 May 2022 15:41:29 +0530 Message-Id: <20220526101131.2340729-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid parameter in riscv_hartid_to_cpuid() as unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/include/asm/smp.h | 4 ++-- arch/riscv/kernel/smp.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 23170c933d73..d3443be7eedc 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mas= k); /* Hook for the generic smp_call_function_single() routine. */ void arch_send_call_function_single_ipi(int cpu); =20 -int riscv_hartid_to_cpuid(int hartid); +int riscv_hartid_to_cpuid(unsigned long hartid); =20 /* Set custom IPI operations */ void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int= prec) { } =20 -static inline int riscv_hartid_to_cpuid(int hartid) +static inline int riscv_hartid_to_cpuid(unsigned long hartid) { if (hartid =3D=3D boot_cpu_hartid) return 0; diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b5d30ea92292..018e7dc45df6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -47,7 +47,7 @@ static struct { unsigned long bits ____cacheline_aligned; } ipi_data[NR_CPUS] __cacheline_aligned; =20 -int riscv_hartid_to_cpuid(int hartid) +int riscv_hartid_to_cpuid(unsigned long hartid) { int i; =20 @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid) if (cpuid_to_hartid_map(i) =3D=3D hartid) return i; =20 - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); return -ENOENT; } =20 --=20 2.25.1 From nobody Fri May 1 08:39:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B3A2C433EF for ; Thu, 26 May 2022 10:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347026AbiEZKM2 (ORCPT ); Thu, 26 May 2022 06:12:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346962AbiEZKMA (ORCPT ); Thu, 26 May 2022 06:12:00 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79203117E for ; Thu, 26 May 2022 03:11:56 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id x2-20020a17090a1f8200b001e07a64c461so4002433pja.4 for ; Thu, 26 May 2022 03:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K4/jbxyTjaVENdJUeS7U2YJP8/xoYroH7rqKl9F4SxI=; b=ROt7I3Nyr9Q+gowE5eM3uNJ8euXDR5tzpkgOGfYUOtOAcGLm231qu9f9ZfmSSvXSHw NTb1HFQZQ+eqfw3XPO7CZ2/yFfi5qGqik5i3Nxfblr1QjDVw9GQzc5Iud5pT/R9UuzZk ilsjgiimc3WQ3Wst8Ki+8/n26mtVA9dQxWcuUz2c4yygXmsIOIbQbaDoCl10JaO0GBmj WXkDeUd/UJ5U+/fqHWKDbEWX2mylX8PtCoo4Cg9MV/Rh0oa8p/Yo4pKdZfE//mZYDLyo zOFdV/vO+e8FzIklplLayB7HFvPXbg7Z0y+AWZDnYWpaq9WI6mo2fM/EHdcRnW2skZeA pplQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K4/jbxyTjaVENdJUeS7U2YJP8/xoYroH7rqKl9F4SxI=; b=jhZRg7MF27cF+ROCgTw7GuAogneN/o+icApNTL3EwYtmvSq7zd3/SKFT1srPpIzh2M ePGj3/BaOJFNKs425chWijDfHs+kjmZWM4ZK9i0EjCmc6nvxduyEeemO4olrFdumos8Q lYbqopKTjSFOj7+xfvqdwelDti1/9eOdrq0FhYZ69hglrS/xsk7XvaJyFWljLXfz0g6u G73ZdnJIFugaIKh5rx5Hck98OJI+DoOKv+voDB6oeZLKgeZcShp1/BAvh4YWZAH2AN9v fm431cL0BXVXyi4kxRZfFapCR37sy8jV4XW9L6prrh5oHK6CsIQsMTv0Nz5TU2ZKSFbz bghQ== X-Gm-Message-State: AOAM530VRstpy8ibTnZ9f9MvLb7zyamW749JFU0Tx7kyvVCarqUwC3De C40Sa34YvA85LKvtnSRg9r9jIWf97hprsChN X-Google-Smtp-Source: ABdhPJyhNh+f2oWMXxABwW+fRsFqwZH+cOKOcVHtaehlPykQPu0fAjtvz9npvu9D57G/VIMaJVpokg== X-Received: by 2002:a17:902:7606:b0:161:df31:68f2 with SMTP id k6-20020a170902760600b00161df3168f2mr34397649pll.151.1653559915347; Thu, 26 May 2022 03:11:55 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:54 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 4/5] riscv: cpu: Support for 64bit hartid Date: Thu, 26 May 2022 15:41:30 +0530 Message-Id: <20220526101131.2340729-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds support for 64bit hartid in riscv_of_processor_hartid() - Separate return value and status code. - Make hartid variable type as unsigned long. - Update the callers. Signed-off-by: Sunil V L Reviewed-by: Atish Patra --- arch/riscv/include/asm/processor.h | 4 ++-- arch/riscv/kernel/cpu.c | 26 +++++++++++++++----------- arch/riscv/kernel/cpufeature.c | 6 ++++-- arch/riscv/kernel/smpboot.c | 9 +++++---- drivers/clocksource/timer-riscv.c | 15 ++++++++------- drivers/irqchip/irq-riscv-intc.c | 7 ++++--- drivers/irqchip/irq-sifive-plic.c | 7 ++++--- 7 files changed, 42 insertions(+), 32 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 0749924d9e55..99fae9398506 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,8 +75,8 @@ static inline void wait_for_interrupt(void) } =20 struct device_node; -int riscv_of_processor_hartid(struct device_node *node); -int riscv_of_parent_hartid(struct device_node *node); +int riscv_of_processor_hartid(struct device_node *node, unsigned long *har= tid); +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid= ); =20 extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struc= t *src); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..477a33b34c95 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -14,37 +14,36 @@ * Returns the hart ID of the given device tree node, or -ENODEV if the no= de * isn't an enabled and valid RISC-V hart node. */ -int riscv_of_processor_hartid(struct device_node *node) +int riscv_of_processor_hartid(struct device_node *node, unsigned long *har= t) { const char *isa; - u32 hart; =20 if (!of_device_is_compatible(node, "riscv")) { pr_warn("Found incompatible CPU\n"); return -ENODEV; } =20 - hart =3D of_get_cpu_hwid(node, 0); - if (hart =3D=3D ~0U) { + *hart =3D (unsigned long) of_get_cpu_hwid(node, 0); + if (*hart =3D=3D ~0UL) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; } =20 if (!of_device_is_available(node)) { - pr_info("CPU with hartid=3D%d is not available\n", hart); + pr_info("CPU with hartid=3D%lu is not available\n", *hart); return -ENODEV; } =20 if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=3D%d has no \"riscv,isa\" property\n", hart); + pr_warn("CPU with hartid=3D%lu has no \"riscv,isa\" property\n", *hart); return -ENODEV; } if (isa[0] !=3D 'r' || isa[1] !=3D 'v') { - pr_warn("CPU with hartid=3D%d has an invalid ISA of \"%s\"\n", hart, isa= ); + pr_warn("CPU with hartid=3D%lu has an invalid ISA of \"%s\"\n", *hart, i= sa); return -ENODEV; } =20 - return hart; + return 0; } =20 /* @@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node) * To achieve this, we walk up the DT tree until we find an active * RISC-V core (HART) node and extract the cpuid from it. */ -int riscv_of_parent_hartid(struct device_node *node) +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) { + int rc; + for (; node; node =3D node->parent) { - if (of_device_is_compatible(node, "riscv")) - return riscv_of_processor_hartid(node); + if (of_device_is_compatible(node, "riscv")) { + rc =3D riscv_of_processor_hartid(node, hartid); + if (!rc) + return 0; + } } =20 return -1; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..49c05bd9352d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -67,8 +67,9 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; + int i, j, rc; static unsigned long isa2hwcap[256] =3D {0}; + unsigned long hartid; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; isa2hwcap['m'] =3D isa2hwcap['M'] =3D COMPAT_HWCAP_ISA_M; @@ -86,7 +87,8 @@ void __init riscv_fill_hwcap(void) DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; =20 - if (riscv_of_processor_hartid(node) < 0) + rc =3D riscv_of_processor_hartid(node, &hartid); + if (rc < 0) continue; =20 if (of_property_read_string(node, "riscv,isa", &isa)) { diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..4336610a19ee 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -76,15 +76,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) void __init setup_smp(void) { struct device_node *dn; - int hart; + unsigned long hart; bool found_boot_cpu =3D false; int cpuid =3D 1; + int rc; =20 cpu_set_ops(0); =20 for_each_of_cpu_node(dn) { - hart =3D riscv_of_processor_hartid(dn); - if (hart < 0) + rc =3D riscv_of_processor_hartid(dn, &hart); + if (rc < 0) continue; =20 if (hart =3D=3D cpuid_to_hartid_map(0)) { @@ -94,7 +95,7 @@ void __init setup_smp(void) continue; } if (cpuid >=3D NR_CPUS) { - pr_warn("Invalid cpuid [%d] for hartid [%d]\n", + pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", cpuid, hart); continue; } diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 1767f8bf2013..55142c27f0bc 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, voi= d *dev_id) =20 static int __init riscv_timer_init_dt(struct device_node *n) { - int cpuid, hartid, error; + int cpuid, error; + unsigned long hartid; struct device_node *child; struct irq_domain *domain; =20 - hartid =3D riscv_of_processor_hartid(n); - if (hartid < 0) { - pr_warn("Not valid hartid for node [%pOF] error =3D [%d]\n", + error =3D riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Not valid hartid for node [%pOF] error =3D [%lu]\n", n, hartid); - return hartid; + return error; } =20 cpuid =3D riscv_hartid_to_cpuid(hartid); if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); return cpuid; } =20 @@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_nod= e *n) return -ENODEV; } =20 - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", + pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", __func__, cpuid, hartid); error =3D clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index b65bd8878d4f..499e5f81b3fe 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_op= s =3D { static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc, hartid; + int rc; + unsigned long hartid; =20 - hartid =3D riscv_of_parent_hartid(node); - if (hartid < 0) { + rc =3D riscv_of_parent_hartid(node, &hartid); + if (rc < 0) { pr_warn("unable to find hart id for %pOF\n", node); return 0; } diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index bb87e4c3b88e..4710d9741f36 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -317,7 +317,8 @@ static int __init plic_init(struct device_node *node, for (i =3D 0; i < nr_contexts; i++) { struct of_phandle_args parent; irq_hw_number_t hwirq; - int cpu, hartid; + int cpu; + unsigned long hartid; =20 if (of_irq_parse_one(node, i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); @@ -341,8 +342,8 @@ static int __init plic_init(struct device_node *node, continue; } =20 - hartid =3D riscv_of_parent_hartid(parent.np); - if (hartid < 0) { + error =3D riscv_of_parent_hartid(parent.np, &hartid); + if (error < 0) { pr_warn("failed to parse hart ID for context %d.\n", i); continue; } --=20 2.25.1 From nobody Fri May 1 08:39:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ED3FC433F5 for ; Thu, 26 May 2022 10:12:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347021AbiEZKMM (ORCPT ); Thu, 26 May 2022 06:12:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347010AbiEZKMG (ORCPT ); Thu, 26 May 2022 06:12:06 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DADF721BC for ; Thu, 26 May 2022 03:11:59 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id qe5-20020a17090b4f8500b001e26126abccso197442pjb.0 for ; Thu, 26 May 2022 03:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2nXJi7PiDDt9d1NL5JWtAPFwSienZjCWVKHwZcbhaBc=; b=JOR9LUUFNgj0IhaBYyG+l5lZ0VF9aY94nwBPk8vRUqj9RK+tdsptxfK3s5B99lnFXk 2ccRWc8trH74wUOJ225CGHcpTKEsX6ZzpUjc9JKnZV+6ZpPFVKTgKN0tMyqFUu9NIv5s SjbVlc6K3Cb4zoXyIamBmKjv/NuHbpn5zZE8I+rMWqlqP8gytbUKBiPlVmalQJoENPVJ E0Y615jRLoSaQgCZZ71FCsFsF0sAcF1J5QF36Fe7frEj/tXj+rdciwQp3nGid8lzS5kX D1T5HG613dqG7U8xRPU7+o3Ixt+rfgmhXvITxe1fuQ4PEweHuRsDjHSohwiIS43nevOS ltiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2nXJi7PiDDt9d1NL5JWtAPFwSienZjCWVKHwZcbhaBc=; b=gHV2oNZvgFhvegmvrXJqEkU3gGYUOWIFyN0n/bzFGRL7YWxDrhMkVPBxpvDdBGYGNv YC6HFdlCHd5/RkqUyzOxEiWh/hBH5IS2jlPgZK/wcacq+lLNkPhihrnG3CU+/i3riQw8 yYIW6E9pZAb/6a7uG0lQ50fkZ31EvBd3mKVzigKjU+PJrjVfGkAxgVfJlIbabW4AWHrH nv5zD8wuLOlApb6sAtsLWHvw5Nu1buzK1zoS5LE4hrD2k/USk94Phu2Ub2kVy98SiBBi aP1mOjmM2QUPcCUuN/OJZOmxsbeOLI2Oz4lxcUETqhJPp7NxYGliZEugqlP9jCcSZAAd o2dw== X-Gm-Message-State: AOAM533OOK4mJOSqxrKHO1q/BqWtIgIQVcfTsS84yO36XAUYRtHUJKrs 74r+rPPeoq/BO9xJml2chB+2Nw== X-Google-Smtp-Source: ABdhPJzk38UFvmZ2o5iGTIUaOlnX9TN0YPEZTK04SPZov7Zl3y6PwSIE61Oh2DmJjFw+uDJ03NumjQ== X-Received: by 2002:a17:90a:408f:b0:1d1:d1ba:2abb with SMTP id l15-20020a17090a408f00b001d1d1ba2abbmr1833141pjg.152.1653559919412; Thu, 26 May 2022 03:11:59 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:59 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 5/5] riscv/efi_stub: Support for 64bit boot-hartid Date: Thu, 26 May 2022 15:41:31 +0530 Message-Id: <20220526101131.2340729-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The boot-hartid can be a 64bit value on RV64 platforms. Currently, the "boot-hartid" in DT is assumed to be 32bit only. This patch detects the size of the "boot-hartid" and uses 32bit or 64bit FDT reads appropriately. Signed-off-by: Sunil V L --- drivers/firmware/efi/libstub/riscv-stub.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/e= fi/libstub/riscv-stub.c index 9e85e58d1f27..b450ebf95977 100644 --- a/drivers/firmware/efi/libstub/riscv-stub.c +++ b/drivers/firmware/efi/libstub/riscv-stub.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 #include "efistub.h" =20 @@ -29,7 +30,7 @@ static int get_boot_hartid_from_fdt(void) { const void *fdt; int chosen_node, len; - const fdt32_t *prop; + const void *prop; =20 fdt =3D get_efi_config_table(DEVICE_TREE_GUID); if (!fdt) @@ -40,10 +41,16 @@ static int get_boot_hartid_from_fdt(void) return -EINVAL; =20 prop =3D fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); - if (!prop || len !=3D sizeof(u32)) + if (!prop) + return -EINVAL; + + if (len =3D=3D sizeof(u32)) + hartid =3D (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); + else if (len =3D=3D sizeof(u64)) + hartid =3D (unsigned long) fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)= ); + else return -EINVAL; =20 - hartid =3D fdt32_to_cpu(*prop); return 0; } =20 --=20 2.25.1